209 lines
7.7 KiB
C
209 lines
7.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_DMA_CH_4_REGS_H_
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#define ASIC_REG_DMA_CH_4_REGS_H_
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/*
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*****************************************
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* DMA_CH_4 (Prototype: DMA_CH)
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*****************************************
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*/
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#define mmDMA_CH_4_CFG0 0x421000
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#define mmDMA_CH_4_CFG1 0x421004
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#define mmDMA_CH_4_ERRMSG_ADDR_LO 0x421008
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#define mmDMA_CH_4_ERRMSG_ADDR_HI 0x42100C
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#define mmDMA_CH_4_ERRMSG_WDATA 0x421010
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#define mmDMA_CH_4_RD_COMP_ADDR_LO 0x421014
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#define mmDMA_CH_4_RD_COMP_ADDR_HI 0x421018
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#define mmDMA_CH_4_RD_COMP_WDATA 0x42101C
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#define mmDMA_CH_4_WR_COMP_ADDR_LO 0x421020
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#define mmDMA_CH_4_WR_COMP_ADDR_HI 0x421024
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#define mmDMA_CH_4_WR_COMP_WDATA 0x421028
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#define mmDMA_CH_4_LDMA_SRC_ADDR_LO 0x42102C
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#define mmDMA_CH_4_LDMA_SRC_ADDR_HI 0x421030
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#define mmDMA_CH_4_LDMA_DST_ADDR_LO 0x421034
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#define mmDMA_CH_4_LDMA_DST_ADDR_HI 0x421038
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#define mmDMA_CH_4_LDMA_TSIZE 0x42103C
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#define mmDMA_CH_4_COMIT_TRANSFER 0x421040
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#define mmDMA_CH_4_STS0 0x421044
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#define mmDMA_CH_4_STS1 0x421048
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#define mmDMA_CH_4_STS2 0x42104C
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#define mmDMA_CH_4_STS3 0x421050
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#define mmDMA_CH_4_STS4 0x421054
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#define mmDMA_CH_4_SRC_ADDR_LO_STS 0x421058
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#define mmDMA_CH_4_SRC_ADDR_HI_STS 0x42105C
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#define mmDMA_CH_4_SRC_TSIZE_STS 0x421060
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#define mmDMA_CH_4_DST_ADDR_LO_STS 0x421064
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#define mmDMA_CH_4_DST_ADDR_HI_STS 0x421068
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#define mmDMA_CH_4_DST_TSIZE_STS 0x42106C
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#define mmDMA_CH_4_RD_RATE_LIM_EN 0x421070
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#define mmDMA_CH_4_RD_RATE_LIM_RST_TOKEN 0x421074
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#define mmDMA_CH_4_RD_RATE_LIM_SAT 0x421078
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#define mmDMA_CH_4_RD_RATE_LIM_TOUT 0x42107C
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#define mmDMA_CH_4_WR_RATE_LIM_EN 0x421080
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#define mmDMA_CH_4_WR_RATE_LIM_RST_TOKEN 0x421084
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#define mmDMA_CH_4_WR_RATE_LIM_SAT 0x421088
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#define mmDMA_CH_4_WR_RATE_LIM_TOUT 0x42108C
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#define mmDMA_CH_4_CFG2 0x421090
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#define mmDMA_CH_4_TDMA_CTL 0x421100
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#define mmDMA_CH_4_TDMA_SRC_BASE_ADDR_LO 0x421104
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#define mmDMA_CH_4_TDMA_SRC_BASE_ADDR_HI 0x421108
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#define mmDMA_CH_4_TDMA_SRC_ROI_BASE_0 0x42110C
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#define mmDMA_CH_4_TDMA_SRC_ROI_SIZE_0 0x421110
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#define mmDMA_CH_4_TDMA_SRC_VALID_ELEMENTS_0 0x421114
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#define mmDMA_CH_4_TDMA_SRC_START_OFFSET_0 0x421118
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#define mmDMA_CH_4_TDMA_SRC_STRIDE_0 0x42111C
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#define mmDMA_CH_4_TDMA_SRC_ROI_BASE_1 0x421120
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#define mmDMA_CH_4_TDMA_SRC_ROI_SIZE_1 0x421124
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#define mmDMA_CH_4_TDMA_SRC_VALID_ELEMENTS_1 0x421128
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#define mmDMA_CH_4_TDMA_SRC_START_OFFSET_1 0x42112C
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#define mmDMA_CH_4_TDMA_SRC_STRIDE_1 0x421130
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#define mmDMA_CH_4_TDMA_SRC_ROI_BASE_2 0x421134
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#define mmDMA_CH_4_TDMA_SRC_ROI_SIZE_2 0x421138
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#define mmDMA_CH_4_TDMA_SRC_VALID_ELEMENTS_2 0x42113C
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#define mmDMA_CH_4_TDMA_SRC_START_OFFSET_2 0x421140
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#define mmDMA_CH_4_TDMA_SRC_STRIDE_2 0x421144
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#define mmDMA_CH_4_TDMA_SRC_ROI_BASE_3 0x421148
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#define mmDMA_CH_4_TDMA_SRC_ROI_SIZE_3 0x42114C
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#define mmDMA_CH_4_TDMA_SRC_VALID_ELEMENTS_3 0x421150
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#define mmDMA_CH_4_TDMA_SRC_START_OFFSET_3 0x421154
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#define mmDMA_CH_4_TDMA_SRC_STRIDE_3 0x421158
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#define mmDMA_CH_4_TDMA_SRC_ROI_BASE_4 0x42115C
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#define mmDMA_CH_4_TDMA_SRC_ROI_SIZE_4 0x421160
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#define mmDMA_CH_4_TDMA_SRC_VALID_ELEMENTS_4 0x421164
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#define mmDMA_CH_4_TDMA_SRC_START_OFFSET_4 0x421168
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#define mmDMA_CH_4_TDMA_SRC_STRIDE_4 0x42116C
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#define mmDMA_CH_4_TDMA_DST_BASE_ADDR_LO 0x421170
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#define mmDMA_CH_4_TDMA_DST_BASE_ADDR_HI 0x421174
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#define mmDMA_CH_4_TDMA_DST_ROI_BASE_0 0x421178
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#define mmDMA_CH_4_TDMA_DST_ROI_SIZE_0 0x42117C
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#define mmDMA_CH_4_TDMA_DST_VALID_ELEMENTS_0 0x421180
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#define mmDMA_CH_4_TDMA_DST_START_OFFSET_0 0x421184
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#define mmDMA_CH_4_TDMA_DST_STRIDE_0 0x421188
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#define mmDMA_CH_4_TDMA_DST_ROI_BASE_1 0x42118C
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#define mmDMA_CH_4_TDMA_DST_ROI_SIZE_1 0x421190
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#define mmDMA_CH_4_TDMA_DST_VALID_ELEMENTS_1 0x421194
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#define mmDMA_CH_4_TDMA_DST_START_OFFSET_1 0x421198
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#define mmDMA_CH_4_TDMA_DST_STRIDE_1 0x42119C
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#define mmDMA_CH_4_TDMA_DST_ROI_BASE_2 0x4211A0
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#define mmDMA_CH_4_TDMA_DST_ROI_SIZE_2 0x4211A4
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#define mmDMA_CH_4_TDMA_DST_VALID_ELEMENTS_2 0x4211A8
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#define mmDMA_CH_4_TDMA_DST_START_OFFSET_2 0x4211AC
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#define mmDMA_CH_4_TDMA_DST_STRIDE_2 0x4211B0
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#define mmDMA_CH_4_TDMA_DST_ROI_BASE_3 0x4211B4
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#define mmDMA_CH_4_TDMA_DST_ROI_SIZE_3 0x4211B8
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#define mmDMA_CH_4_TDMA_DST_VALID_ELEMENTS_3 0x4211BC
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#define mmDMA_CH_4_TDMA_DST_START_OFFSET_3 0x4211C0
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#define mmDMA_CH_4_TDMA_DST_STRIDE_3 0x4211C4
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#define mmDMA_CH_4_TDMA_DST_ROI_BASE_4 0x4211C8
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#define mmDMA_CH_4_TDMA_DST_ROI_SIZE_4 0x4211CC
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#define mmDMA_CH_4_TDMA_DST_VALID_ELEMENTS_4 0x4211D0
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#define mmDMA_CH_4_TDMA_DST_START_OFFSET_4 0x4211D4
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#define mmDMA_CH_4_TDMA_DST_STRIDE_4 0x4211D8
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#define mmDMA_CH_4_MEM_INIT_BUSY 0x4211FC
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#endif /* ASIC_REG_DMA_CH_4_REGS_H_ */
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