209 lines
10 KiB
C
209 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_DMA_NRTR_MASKS_H_
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#define ASIC_REG_DMA_NRTR_MASKS_H_
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/*
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*****************************************
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* DMA_NRTR (Prototype: IF_NRTR)
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*****************************************
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*/
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/* DMA_NRTR_HBW_MAX_CRED */
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#define DMA_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
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#define DMA_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
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#define DMA_NRTR_HBW_MAX_CRED_WR_RS_SHIFT 8
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#define DMA_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
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#define DMA_NRTR_HBW_MAX_CRED_RD_RQ_SHIFT 16
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#define DMA_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
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#define DMA_NRTR_HBW_MAX_CRED_RD_RS_SHIFT 24
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#define DMA_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
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/* DMA_NRTR_LBW_MAX_CRED */
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#define DMA_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
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#define DMA_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
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#define DMA_NRTR_LBW_MAX_CRED_WR_RS_SHIFT 8
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#define DMA_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
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#define DMA_NRTR_LBW_MAX_CRED_RD_RQ_SHIFT 16
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#define DMA_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
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#define DMA_NRTR_LBW_MAX_CRED_RD_RS_SHIFT 24
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#define DMA_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
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/* DMA_NRTR_DBG_E_ARB */
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#define DMA_NRTR_DBG_E_ARB_W_SHIFT 0
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#define DMA_NRTR_DBG_E_ARB_W_MASK 0x7
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#define DMA_NRTR_DBG_E_ARB_S_SHIFT 8
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#define DMA_NRTR_DBG_E_ARB_S_MASK 0x700
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#define DMA_NRTR_DBG_E_ARB_N_SHIFT 16
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#define DMA_NRTR_DBG_E_ARB_N_MASK 0x70000
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#define DMA_NRTR_DBG_E_ARB_L_SHIFT 24
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#define DMA_NRTR_DBG_E_ARB_L_MASK 0x7000000
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/* DMA_NRTR_DBG_W_ARB */
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#define DMA_NRTR_DBG_W_ARB_E_SHIFT 0
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#define DMA_NRTR_DBG_W_ARB_E_MASK 0x7
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#define DMA_NRTR_DBG_W_ARB_S_SHIFT 8
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#define DMA_NRTR_DBG_W_ARB_S_MASK 0x700
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#define DMA_NRTR_DBG_W_ARB_N_SHIFT 16
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#define DMA_NRTR_DBG_W_ARB_N_MASK 0x70000
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#define DMA_NRTR_DBG_W_ARB_L_SHIFT 24
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#define DMA_NRTR_DBG_W_ARB_L_MASK 0x7000000
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/* DMA_NRTR_DBG_N_ARB */
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#define DMA_NRTR_DBG_N_ARB_W_SHIFT 0
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#define DMA_NRTR_DBG_N_ARB_W_MASK 0x7
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#define DMA_NRTR_DBG_N_ARB_E_SHIFT 8
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#define DMA_NRTR_DBG_N_ARB_E_MASK 0x700
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#define DMA_NRTR_DBG_N_ARB_S_SHIFT 16
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#define DMA_NRTR_DBG_N_ARB_S_MASK 0x70000
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#define DMA_NRTR_DBG_N_ARB_L_SHIFT 24
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#define DMA_NRTR_DBG_N_ARB_L_MASK 0x7000000
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/* DMA_NRTR_DBG_S_ARB */
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#define DMA_NRTR_DBG_S_ARB_W_SHIFT 0
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#define DMA_NRTR_DBG_S_ARB_W_MASK 0x7
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#define DMA_NRTR_DBG_S_ARB_E_SHIFT 8
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#define DMA_NRTR_DBG_S_ARB_E_MASK 0x700
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#define DMA_NRTR_DBG_S_ARB_N_SHIFT 16
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#define DMA_NRTR_DBG_S_ARB_N_MASK 0x70000
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#define DMA_NRTR_DBG_S_ARB_L_SHIFT 24
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#define DMA_NRTR_DBG_S_ARB_L_MASK 0x7000000
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/* DMA_NRTR_DBG_L_ARB */
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#define DMA_NRTR_DBG_L_ARB_W_SHIFT 0
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#define DMA_NRTR_DBG_L_ARB_W_MASK 0x7
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#define DMA_NRTR_DBG_L_ARB_E_SHIFT 8
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#define DMA_NRTR_DBG_L_ARB_E_MASK 0x700
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#define DMA_NRTR_DBG_L_ARB_S_SHIFT 16
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#define DMA_NRTR_DBG_L_ARB_S_MASK 0x70000
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#define DMA_NRTR_DBG_L_ARB_N_SHIFT 24
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#define DMA_NRTR_DBG_L_ARB_N_MASK 0x7000000
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/* DMA_NRTR_DBG_E_ARB_MAX */
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#define DMA_NRTR_DBG_E_ARB_MAX_CREDIT_SHIFT 0
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#define DMA_NRTR_DBG_E_ARB_MAX_CREDIT_MASK 0x3F
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/* DMA_NRTR_DBG_W_ARB_MAX */
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#define DMA_NRTR_DBG_W_ARB_MAX_CREDIT_SHIFT 0
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#define DMA_NRTR_DBG_W_ARB_MAX_CREDIT_MASK 0x3F
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/* DMA_NRTR_DBG_N_ARB_MAX */
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#define DMA_NRTR_DBG_N_ARB_MAX_CREDIT_SHIFT 0
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#define DMA_NRTR_DBG_N_ARB_MAX_CREDIT_MASK 0x3F
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/* DMA_NRTR_DBG_S_ARB_MAX */
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#define DMA_NRTR_DBG_S_ARB_MAX_CREDIT_SHIFT 0
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#define DMA_NRTR_DBG_S_ARB_MAX_CREDIT_MASK 0x3F
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/* DMA_NRTR_DBG_L_ARB_MAX */
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#define DMA_NRTR_DBG_L_ARB_MAX_CREDIT_SHIFT 0
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#define DMA_NRTR_DBG_L_ARB_MAX_CREDIT_MASK 0x3F
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/* DMA_NRTR_SPLIT_COEF */
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#define DMA_NRTR_SPLIT_COEF_VAL_SHIFT 0
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#define DMA_NRTR_SPLIT_COEF_VAL_MASK 0xFFFF
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/* DMA_NRTR_SPLIT_CFG */
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#define DMA_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_SHIFT 0
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#define DMA_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_MASK 0x1
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#define DMA_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_SHIFT 1
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#define DMA_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_MASK 0x2
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#define DMA_NRTR_SPLIT_CFG_DEFAULT_MESH_SHIFT 2
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#define DMA_NRTR_SPLIT_CFG_DEFAULT_MESH_MASK 0xC
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#define DMA_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_SHIFT 4
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#define DMA_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_MASK 0x10
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#define DMA_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_SHIFT 5
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#define DMA_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_MASK 0x20
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#define DMA_NRTR_SPLIT_CFG_B2B_OPT_SHIFT 6
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#define DMA_NRTR_SPLIT_CFG_B2B_OPT_MASK 0x1C0
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/* DMA_NRTR_SPLIT_RD_SAT */
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#define DMA_NRTR_SPLIT_RD_SAT_VAL_SHIFT 0
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#define DMA_NRTR_SPLIT_RD_SAT_VAL_MASK 0xFFFF
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/* DMA_NRTR_SPLIT_RD_RST_TOKEN */
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#define DMA_NRTR_SPLIT_RD_RST_TOKEN_VAL_SHIFT 0
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#define DMA_NRTR_SPLIT_RD_RST_TOKEN_VAL_MASK 0xFFFF
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/* DMA_NRTR_SPLIT_RD_TIMEOUT */
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#define DMA_NRTR_SPLIT_RD_TIMEOUT_VAL_SHIFT 0
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#define DMA_NRTR_SPLIT_RD_TIMEOUT_VAL_MASK 0xFFFFFFFF
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/* DMA_NRTR_SPLIT_WR_SAT */
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#define DMA_NRTR_SPLIT_WR_SAT_VAL_SHIFT 0
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#define DMA_NRTR_SPLIT_WR_SAT_VAL_MASK 0xFFFF
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/* DMA_NRTR_WPLIT_WR_TST_TOLEN */
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#define DMA_NRTR_WPLIT_WR_TST_TOLEN_VAL_SHIFT 0
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#define DMA_NRTR_WPLIT_WR_TST_TOLEN_VAL_MASK 0xFFFF
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/* DMA_NRTR_SPLIT_WR_TIMEOUT */
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#define DMA_NRTR_SPLIT_WR_TIMEOUT_VAL_SHIFT 0
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#define DMA_NRTR_SPLIT_WR_TIMEOUT_VAL_MASK 0xFFFFFFFF
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/* DMA_NRTR_HBW_RANGE_HIT */
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#define DMA_NRTR_HBW_RANGE_HIT_IND_SHIFT 0
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#define DMA_NRTR_HBW_RANGE_HIT_IND_MASK 0xFF
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/* DMA_NRTR_HBW_RANGE_MASK_L */
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#define DMA_NRTR_HBW_RANGE_MASK_L_VAL_SHIFT 0
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#define DMA_NRTR_HBW_RANGE_MASK_L_VAL_MASK 0xFFFFFFFF
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/* DMA_NRTR_HBW_RANGE_MASK_H */
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#define DMA_NRTR_HBW_RANGE_MASK_H_VAL_SHIFT 0
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#define DMA_NRTR_HBW_RANGE_MASK_H_VAL_MASK 0x3FFFF
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/* DMA_NRTR_HBW_RANGE_BASE_L */
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#define DMA_NRTR_HBW_RANGE_BASE_L_VAL_SHIFT 0
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#define DMA_NRTR_HBW_RANGE_BASE_L_VAL_MASK 0xFFFFFFFF
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/* DMA_NRTR_HBW_RANGE_BASE_H */
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#define DMA_NRTR_HBW_RANGE_BASE_H_VAL_SHIFT 0
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#define DMA_NRTR_HBW_RANGE_BASE_H_VAL_MASK 0x3FFFF
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/* DMA_NRTR_LBW_RANGE_HIT */
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#define DMA_NRTR_LBW_RANGE_HIT_IND_SHIFT 0
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#define DMA_NRTR_LBW_RANGE_HIT_IND_MASK 0xFFFF
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/* DMA_NRTR_LBW_RANGE_MASK */
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#define DMA_NRTR_LBW_RANGE_MASK_VAL_SHIFT 0
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#define DMA_NRTR_LBW_RANGE_MASK_VAL_MASK 0x3FFFFFF
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/* DMA_NRTR_LBW_RANGE_BASE */
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#define DMA_NRTR_LBW_RANGE_BASE_VAL_SHIFT 0
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#define DMA_NRTR_LBW_RANGE_BASE_VAL_MASK 0x3FFFFFF
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/* DMA_NRTR_RGLTR */
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#define DMA_NRTR_RGLTR_WR_EN_SHIFT 0
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#define DMA_NRTR_RGLTR_WR_EN_MASK 0x1
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#define DMA_NRTR_RGLTR_RD_EN_SHIFT 4
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#define DMA_NRTR_RGLTR_RD_EN_MASK 0x10
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/* DMA_NRTR_RGLTR_WR_RESULT */
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#define DMA_NRTR_RGLTR_WR_RESULT_VAL_SHIFT 0
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#define DMA_NRTR_RGLTR_WR_RESULT_VAL_MASK 0xFF
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/* DMA_NRTR_RGLTR_RD_RESULT */
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#define DMA_NRTR_RGLTR_RD_RESULT_VAL_SHIFT 0
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#define DMA_NRTR_RGLTR_RD_RESULT_VAL_MASK 0xFF
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/* DMA_NRTR_SCRAMB_EN */
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#define DMA_NRTR_SCRAMB_EN_VAL_SHIFT 0
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#define DMA_NRTR_SCRAMB_EN_VAL_MASK 0x1
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/* DMA_NRTR_NON_LIN_SCRAMB */
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#define DMA_NRTR_NON_LIN_SCRAMB_EN_SHIFT 0
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#define DMA_NRTR_NON_LIN_SCRAMB_EN_MASK 0x1
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#endif /* ASIC_REG_DMA_NRTR_MASKS_H_ */
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