179 lines
6.5 KiB
C
179 lines
6.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_DMA_QM_0_REGS_H_
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#define ASIC_REG_DMA_QM_0_REGS_H_
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/*
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*****************************************
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* DMA_QM_0 (Prototype: QMAN)
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*****************************************
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*/
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#define mmDMA_QM_0_GLBL_CFG0 0x400000
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#define mmDMA_QM_0_GLBL_CFG1 0x400004
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#define mmDMA_QM_0_GLBL_PROT 0x400008
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#define mmDMA_QM_0_GLBL_ERR_CFG 0x40000C
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#define mmDMA_QM_0_GLBL_ERR_ADDR_LO 0x400010
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#define mmDMA_QM_0_GLBL_ERR_ADDR_HI 0x400014
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#define mmDMA_QM_0_GLBL_ERR_WDATA 0x400018
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#define mmDMA_QM_0_GLBL_SECURE_PROPS 0x40001C
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#define mmDMA_QM_0_GLBL_NON_SECURE_PROPS 0x400020
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#define mmDMA_QM_0_GLBL_STS0 0x400024
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#define mmDMA_QM_0_GLBL_STS1 0x400028
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#define mmDMA_QM_0_PQ_BASE_LO 0x400060
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#define mmDMA_QM_0_PQ_BASE_HI 0x400064
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#define mmDMA_QM_0_PQ_SIZE 0x400068
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#define mmDMA_QM_0_PQ_PI 0x40006C
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#define mmDMA_QM_0_PQ_CI 0x400070
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#define mmDMA_QM_0_PQ_CFG0 0x400074
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#define mmDMA_QM_0_PQ_CFG1 0x400078
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#define mmDMA_QM_0_PQ_ARUSER 0x40007C
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#define mmDMA_QM_0_PQ_PUSH0 0x400080
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#define mmDMA_QM_0_PQ_PUSH1 0x400084
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#define mmDMA_QM_0_PQ_PUSH2 0x400088
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#define mmDMA_QM_0_PQ_PUSH3 0x40008C
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#define mmDMA_QM_0_PQ_STS0 0x400090
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#define mmDMA_QM_0_PQ_STS1 0x400094
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#define mmDMA_QM_0_PQ_RD_RATE_LIM_EN 0x4000A0
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#define mmDMA_QM_0_PQ_RD_RATE_LIM_RST_TOKEN 0x4000A4
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#define mmDMA_QM_0_PQ_RD_RATE_LIM_SAT 0x4000A8
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#define mmDMA_QM_0_PQ_RD_RATE_LIM_TOUT 0x4000AC
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#define mmDMA_QM_0_CQ_CFG0 0x4000B0
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#define mmDMA_QM_0_CQ_CFG1 0x4000B4
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#define mmDMA_QM_0_CQ_ARUSER 0x4000B8
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#define mmDMA_QM_0_CQ_PTR_LO 0x4000C0
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#define mmDMA_QM_0_CQ_PTR_HI 0x4000C4
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#define mmDMA_QM_0_CQ_TSIZE 0x4000C8
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#define mmDMA_QM_0_CQ_CTL 0x4000CC
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#define mmDMA_QM_0_CQ_PTR_LO_STS 0x4000D4
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#define mmDMA_QM_0_CQ_PTR_HI_STS 0x4000D8
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#define mmDMA_QM_0_CQ_TSIZE_STS 0x4000DC
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#define mmDMA_QM_0_CQ_CTL_STS 0x4000E0
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#define mmDMA_QM_0_CQ_STS0 0x4000E4
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#define mmDMA_QM_0_CQ_STS1 0x4000E8
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#define mmDMA_QM_0_CQ_RD_RATE_LIM_EN 0x4000F0
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#define mmDMA_QM_0_CQ_RD_RATE_LIM_RST_TOKEN 0x4000F4
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#define mmDMA_QM_0_CQ_RD_RATE_LIM_SAT 0x4000F8
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#define mmDMA_QM_0_CQ_RD_RATE_LIM_TOUT 0x4000FC
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#define mmDMA_QM_0_CQ_IFIFO_CNT 0x400108
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#define mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO 0x400120
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#define mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI 0x400124
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#define mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO 0x400128
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#define mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI 0x40012C
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#define mmDMA_QM_0_CP_MSG_BASE2_ADDR_LO 0x400130
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#define mmDMA_QM_0_CP_MSG_BASE2_ADDR_HI 0x400134
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#define mmDMA_QM_0_CP_MSG_BASE3_ADDR_LO 0x400138
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#define mmDMA_QM_0_CP_MSG_BASE3_ADDR_HI 0x40013C
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#define mmDMA_QM_0_CP_LDMA_TSIZE_OFFSET 0x400140
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#define mmDMA_QM_0_CP_LDMA_SRC_BASE_LO_OFFSET 0x400144
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#define mmDMA_QM_0_CP_LDMA_SRC_BASE_HI_OFFSET 0x400148
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#define mmDMA_QM_0_CP_LDMA_DST_BASE_LO_OFFSET 0x40014C
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#define mmDMA_QM_0_CP_LDMA_DST_BASE_HI_OFFSET 0x400150
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#define mmDMA_QM_0_CP_LDMA_COMMIT_OFFSET 0x400154
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#define mmDMA_QM_0_CP_FENCE0_RDATA 0x400158
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#define mmDMA_QM_0_CP_FENCE1_RDATA 0x40015C
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#define mmDMA_QM_0_CP_FENCE2_RDATA 0x400160
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#define mmDMA_QM_0_CP_FENCE3_RDATA 0x400164
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#define mmDMA_QM_0_CP_FENCE0_CNT 0x400168
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#define mmDMA_QM_0_CP_FENCE1_CNT 0x40016C
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#define mmDMA_QM_0_CP_FENCE2_CNT 0x400170
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#define mmDMA_QM_0_CP_FENCE3_CNT 0x400174
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#define mmDMA_QM_0_CP_STS 0x400178
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#define mmDMA_QM_0_CP_CURRENT_INST_LO 0x40017C
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#define mmDMA_QM_0_CP_CURRENT_INST_HI 0x400180
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#define mmDMA_QM_0_CP_BARRIER_CFG 0x400184
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#define mmDMA_QM_0_CP_DBG_0 0x400188
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#define mmDMA_QM_0_PQ_BUF_ADDR 0x400300
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#define mmDMA_QM_0_PQ_BUF_RDATA 0x400304
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#define mmDMA_QM_0_CQ_BUF_ADDR 0x400308
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#define mmDMA_QM_0_CQ_BUF_RDATA 0x40030C
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#endif /* ASIC_REG_DMA_QM_0_REGS_H_ */
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