179 lines
6.5 KiB
C
179 lines
6.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_DMA_QM_2_REGS_H_
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#define ASIC_REG_DMA_QM_2_REGS_H_
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/*
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*****************************************
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* DMA_QM_2 (Prototype: QMAN)
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*****************************************
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*/
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#define mmDMA_QM_2_GLBL_CFG0 0x410000
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#define mmDMA_QM_2_GLBL_CFG1 0x410004
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#define mmDMA_QM_2_GLBL_PROT 0x410008
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#define mmDMA_QM_2_GLBL_ERR_CFG 0x41000C
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#define mmDMA_QM_2_GLBL_ERR_ADDR_LO 0x410010
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#define mmDMA_QM_2_GLBL_ERR_ADDR_HI 0x410014
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#define mmDMA_QM_2_GLBL_ERR_WDATA 0x410018
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#define mmDMA_QM_2_GLBL_SECURE_PROPS 0x41001C
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#define mmDMA_QM_2_GLBL_NON_SECURE_PROPS 0x410020
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#define mmDMA_QM_2_GLBL_STS0 0x410024
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#define mmDMA_QM_2_GLBL_STS1 0x410028
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#define mmDMA_QM_2_PQ_BASE_LO 0x410060
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#define mmDMA_QM_2_PQ_BASE_HI 0x410064
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#define mmDMA_QM_2_PQ_SIZE 0x410068
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#define mmDMA_QM_2_PQ_PI 0x41006C
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#define mmDMA_QM_2_PQ_CI 0x410070
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#define mmDMA_QM_2_PQ_CFG0 0x410074
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#define mmDMA_QM_2_PQ_CFG1 0x410078
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#define mmDMA_QM_2_PQ_ARUSER 0x41007C
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#define mmDMA_QM_2_PQ_PUSH0 0x410080
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#define mmDMA_QM_2_PQ_PUSH1 0x410084
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#define mmDMA_QM_2_PQ_PUSH2 0x410088
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#define mmDMA_QM_2_PQ_PUSH3 0x41008C
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#define mmDMA_QM_2_PQ_STS0 0x410090
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#define mmDMA_QM_2_PQ_STS1 0x410094
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#define mmDMA_QM_2_PQ_RD_RATE_LIM_EN 0x4100A0
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#define mmDMA_QM_2_PQ_RD_RATE_LIM_RST_TOKEN 0x4100A4
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#define mmDMA_QM_2_PQ_RD_RATE_LIM_SAT 0x4100A8
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#define mmDMA_QM_2_PQ_RD_RATE_LIM_TOUT 0x4100AC
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#define mmDMA_QM_2_CQ_CFG0 0x4100B0
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#define mmDMA_QM_2_CQ_CFG1 0x4100B4
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#define mmDMA_QM_2_CQ_ARUSER 0x4100B8
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#define mmDMA_QM_2_CQ_PTR_LO 0x4100C0
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#define mmDMA_QM_2_CQ_PTR_HI 0x4100C4
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#define mmDMA_QM_2_CQ_TSIZE 0x4100C8
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#define mmDMA_QM_2_CQ_CTL 0x4100CC
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#define mmDMA_QM_2_CQ_PTR_LO_STS 0x4100D4
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#define mmDMA_QM_2_CQ_PTR_HI_STS 0x4100D8
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#define mmDMA_QM_2_CQ_TSIZE_STS 0x4100DC
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#define mmDMA_QM_2_CQ_CTL_STS 0x4100E0
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#define mmDMA_QM_2_CQ_STS0 0x4100E4
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#define mmDMA_QM_2_CQ_STS1 0x4100E8
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#define mmDMA_QM_2_CQ_RD_RATE_LIM_EN 0x4100F0
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#define mmDMA_QM_2_CQ_RD_RATE_LIM_RST_TOKEN 0x4100F4
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#define mmDMA_QM_2_CQ_RD_RATE_LIM_SAT 0x4100F8
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#define mmDMA_QM_2_CQ_RD_RATE_LIM_TOUT 0x4100FC
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#define mmDMA_QM_2_CQ_IFIFO_CNT 0x410108
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#define mmDMA_QM_2_CP_MSG_BASE0_ADDR_LO 0x410120
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#define mmDMA_QM_2_CP_MSG_BASE0_ADDR_HI 0x410124
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#define mmDMA_QM_2_CP_MSG_BASE1_ADDR_LO 0x410128
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#define mmDMA_QM_2_CP_MSG_BASE1_ADDR_HI 0x41012C
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#define mmDMA_QM_2_CP_MSG_BASE2_ADDR_LO 0x410130
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#define mmDMA_QM_2_CP_MSG_BASE2_ADDR_HI 0x410134
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#define mmDMA_QM_2_CP_MSG_BASE3_ADDR_LO 0x410138
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#define mmDMA_QM_2_CP_MSG_BASE3_ADDR_HI 0x41013C
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#define mmDMA_QM_2_CP_LDMA_TSIZE_OFFSET 0x410140
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#define mmDMA_QM_2_CP_LDMA_SRC_BASE_LO_OFFSET 0x410144
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#define mmDMA_QM_2_CP_LDMA_SRC_BASE_HI_OFFSET 0x410148
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#define mmDMA_QM_2_CP_LDMA_DST_BASE_LO_OFFSET 0x41014C
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#define mmDMA_QM_2_CP_LDMA_DST_BASE_HI_OFFSET 0x410150
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#define mmDMA_QM_2_CP_LDMA_COMMIT_OFFSET 0x410154
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#define mmDMA_QM_2_CP_FENCE0_RDATA 0x410158
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#define mmDMA_QM_2_CP_FENCE1_RDATA 0x41015C
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#define mmDMA_QM_2_CP_FENCE2_RDATA 0x410160
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#define mmDMA_QM_2_CP_FENCE3_RDATA 0x410164
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#define mmDMA_QM_2_CP_FENCE0_CNT 0x410168
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#define mmDMA_QM_2_CP_FENCE1_CNT 0x41016C
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#define mmDMA_QM_2_CP_FENCE2_CNT 0x410170
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#define mmDMA_QM_2_CP_FENCE3_CNT 0x410174
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#define mmDMA_QM_2_CP_STS 0x410178
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#define mmDMA_QM_2_CP_CURRENT_INST_LO 0x41017C
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#define mmDMA_QM_2_CP_CURRENT_INST_HI 0x410180
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#define mmDMA_QM_2_CP_BARRIER_CFG 0x410184
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#define mmDMA_QM_2_CP_DBG_0 0x410188
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#define mmDMA_QM_2_PQ_BUF_ADDR 0x410300
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#define mmDMA_QM_2_PQ_BUF_RDATA 0x410304
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#define mmDMA_QM_2_CQ_BUF_ADDR 0x410308
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#define mmDMA_QM_2_CQ_BUF_RDATA 0x41030C
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#endif /* ASIC_REG_DMA_QM_2_REGS_H_ */
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