179 lines
6.5 KiB
C
179 lines
6.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_DMA_QM_3_REGS_H_
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#define ASIC_REG_DMA_QM_3_REGS_H_
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/*
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*****************************************
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* DMA_QM_3 (Prototype: QMAN)
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*****************************************
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*/
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#define mmDMA_QM_3_GLBL_CFG0 0x418000
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#define mmDMA_QM_3_GLBL_CFG1 0x418004
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#define mmDMA_QM_3_GLBL_PROT 0x418008
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#define mmDMA_QM_3_GLBL_ERR_CFG 0x41800C
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#define mmDMA_QM_3_GLBL_ERR_ADDR_LO 0x418010
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#define mmDMA_QM_3_GLBL_ERR_ADDR_HI 0x418014
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#define mmDMA_QM_3_GLBL_ERR_WDATA 0x418018
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#define mmDMA_QM_3_GLBL_SECURE_PROPS 0x41801C
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#define mmDMA_QM_3_GLBL_NON_SECURE_PROPS 0x418020
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#define mmDMA_QM_3_GLBL_STS0 0x418024
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#define mmDMA_QM_3_GLBL_STS1 0x418028
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#define mmDMA_QM_3_PQ_BASE_LO 0x418060
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#define mmDMA_QM_3_PQ_BASE_HI 0x418064
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#define mmDMA_QM_3_PQ_SIZE 0x418068
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#define mmDMA_QM_3_PQ_PI 0x41806C
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#define mmDMA_QM_3_PQ_CI 0x418070
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#define mmDMA_QM_3_PQ_CFG0 0x418074
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#define mmDMA_QM_3_PQ_CFG1 0x418078
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#define mmDMA_QM_3_PQ_ARUSER 0x41807C
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#define mmDMA_QM_3_PQ_PUSH0 0x418080
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#define mmDMA_QM_3_PQ_PUSH1 0x418084
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#define mmDMA_QM_3_PQ_PUSH2 0x418088
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#define mmDMA_QM_3_PQ_PUSH3 0x41808C
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#define mmDMA_QM_3_PQ_STS0 0x418090
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#define mmDMA_QM_3_PQ_STS1 0x418094
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#define mmDMA_QM_3_PQ_RD_RATE_LIM_EN 0x4180A0
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#define mmDMA_QM_3_PQ_RD_RATE_LIM_RST_TOKEN 0x4180A4
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#define mmDMA_QM_3_PQ_RD_RATE_LIM_SAT 0x4180A8
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#define mmDMA_QM_3_PQ_RD_RATE_LIM_TOUT 0x4180AC
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#define mmDMA_QM_3_CQ_CFG0 0x4180B0
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#define mmDMA_QM_3_CQ_CFG1 0x4180B4
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#define mmDMA_QM_3_CQ_ARUSER 0x4180B8
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#define mmDMA_QM_3_CQ_PTR_LO 0x4180C0
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#define mmDMA_QM_3_CQ_PTR_HI 0x4180C4
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#define mmDMA_QM_3_CQ_TSIZE 0x4180C8
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#define mmDMA_QM_3_CQ_CTL 0x4180CC
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#define mmDMA_QM_3_CQ_PTR_LO_STS 0x4180D4
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#define mmDMA_QM_3_CQ_PTR_HI_STS 0x4180D8
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#define mmDMA_QM_3_CQ_TSIZE_STS 0x4180DC
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#define mmDMA_QM_3_CQ_CTL_STS 0x4180E0
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#define mmDMA_QM_3_CQ_STS0 0x4180E4
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#define mmDMA_QM_3_CQ_STS1 0x4180E8
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#define mmDMA_QM_3_CQ_RD_RATE_LIM_EN 0x4180F0
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#define mmDMA_QM_3_CQ_RD_RATE_LIM_RST_TOKEN 0x4180F4
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#define mmDMA_QM_3_CQ_RD_RATE_LIM_SAT 0x4180F8
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#define mmDMA_QM_3_CQ_RD_RATE_LIM_TOUT 0x4180FC
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#define mmDMA_QM_3_CQ_IFIFO_CNT 0x418108
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#define mmDMA_QM_3_CP_MSG_BASE0_ADDR_LO 0x418120
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#define mmDMA_QM_3_CP_MSG_BASE0_ADDR_HI 0x418124
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#define mmDMA_QM_3_CP_MSG_BASE1_ADDR_LO 0x418128
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#define mmDMA_QM_3_CP_MSG_BASE1_ADDR_HI 0x41812C
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#define mmDMA_QM_3_CP_MSG_BASE2_ADDR_LO 0x418130
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#define mmDMA_QM_3_CP_MSG_BASE2_ADDR_HI 0x418134
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#define mmDMA_QM_3_CP_MSG_BASE3_ADDR_LO 0x418138
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#define mmDMA_QM_3_CP_MSG_BASE3_ADDR_HI 0x41813C
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#define mmDMA_QM_3_CP_LDMA_TSIZE_OFFSET 0x418140
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#define mmDMA_QM_3_CP_LDMA_SRC_BASE_LO_OFFSET 0x418144
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#define mmDMA_QM_3_CP_LDMA_SRC_BASE_HI_OFFSET 0x418148
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#define mmDMA_QM_3_CP_LDMA_DST_BASE_LO_OFFSET 0x41814C
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#define mmDMA_QM_3_CP_LDMA_DST_BASE_HI_OFFSET 0x418150
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#define mmDMA_QM_3_CP_LDMA_COMMIT_OFFSET 0x418154
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#define mmDMA_QM_3_CP_FENCE0_RDATA 0x418158
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#define mmDMA_QM_3_CP_FENCE1_RDATA 0x41815C
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#define mmDMA_QM_3_CP_FENCE2_RDATA 0x418160
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#define mmDMA_QM_3_CP_FENCE3_RDATA 0x418164
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#define mmDMA_QM_3_CP_FENCE0_CNT 0x418168
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#define mmDMA_QM_3_CP_FENCE1_CNT 0x41816C
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#define mmDMA_QM_3_CP_FENCE2_CNT 0x418170
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#define mmDMA_QM_3_CP_FENCE3_CNT 0x418174
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#define mmDMA_QM_3_CP_STS 0x418178
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#define mmDMA_QM_3_CP_CURRENT_INST_LO 0x41817C
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#define mmDMA_QM_3_CP_CURRENT_INST_HI 0x418180
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#define mmDMA_QM_3_CP_BARRIER_CFG 0x418184
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#define mmDMA_QM_3_CP_DBG_0 0x418188
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#define mmDMA_QM_3_PQ_BUF_ADDR 0x418300
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#define mmDMA_QM_3_PQ_BUF_RDATA 0x418304
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#define mmDMA_QM_3_CQ_BUF_ADDR 0x418308
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#define mmDMA_QM_3_CQ_BUF_RDATA 0x41830C
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#endif /* ASIC_REG_DMA_QM_3_REGS_H_ */
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