331 lines
12 KiB
C
331 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_MME5_RTR_REGS_H_
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#define ASIC_REG_MME5_RTR_REGS_H_
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/*
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*****************************************
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* MME5_RTR (Prototype: MME_RTR)
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*****************************************
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*/
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#define mmMME5_RTR_HBW_RD_RQ_E_ARB 0x140100
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#define mmMME5_RTR_HBW_RD_RQ_W_ARB 0x140104
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#define mmMME5_RTR_HBW_RD_RQ_N_ARB 0x140108
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#define mmMME5_RTR_HBW_RD_RQ_S_ARB 0x14010C
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#define mmMME5_RTR_HBW_RD_RQ_L_ARB 0x140110
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#define mmMME5_RTR_HBW_E_ARB_MAX 0x140120
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#define mmMME5_RTR_HBW_W_ARB_MAX 0x140124
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#define mmMME5_RTR_HBW_N_ARB_MAX 0x140128
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#define mmMME5_RTR_HBW_S_ARB_MAX 0x14012C
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#define mmMME5_RTR_HBW_L_ARB_MAX 0x140130
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#define mmMME5_RTR_HBW_RD_RS_MAX_CREDIT 0x140140
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#define mmMME5_RTR_HBW_WR_RQ_MAX_CREDIT 0x140144
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#define mmMME5_RTR_HBW_RD_RQ_MAX_CREDIT 0x140148
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#define mmMME5_RTR_HBW_RD_RS_E_ARB 0x140150
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#define mmMME5_RTR_HBW_RD_RS_W_ARB 0x140154
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#define mmMME5_RTR_HBW_RD_RS_N_ARB 0x140158
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#define mmMME5_RTR_HBW_RD_RS_S_ARB 0x14015C
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#define mmMME5_RTR_HBW_RD_RS_L_ARB 0x140160
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#define mmMME5_RTR_HBW_WR_RQ_E_ARB 0x140170
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#define mmMME5_RTR_HBW_WR_RQ_W_ARB 0x140174
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#define mmMME5_RTR_HBW_WR_RQ_N_ARB 0x140178
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#define mmMME5_RTR_HBW_WR_RQ_S_ARB 0x14017C
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#define mmMME5_RTR_HBW_WR_RQ_L_ARB 0x140180
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#define mmMME5_RTR_HBW_WR_RS_E_ARB 0x140190
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#define mmMME5_RTR_HBW_WR_RS_W_ARB 0x140194
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#define mmMME5_RTR_HBW_WR_RS_N_ARB 0x140198
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#define mmMME5_RTR_HBW_WR_RS_S_ARB 0x14019C
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#define mmMME5_RTR_HBW_WR_RS_L_ARB 0x1401A0
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#define mmMME5_RTR_LBW_RD_RQ_E_ARB 0x140200
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#define mmMME5_RTR_LBW_RD_RQ_W_ARB 0x140204
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#define mmMME5_RTR_LBW_RD_RQ_N_ARB 0x140208
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#define mmMME5_RTR_LBW_RD_RQ_S_ARB 0x14020C
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#define mmMME5_RTR_LBW_RD_RQ_L_ARB 0x140210
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#define mmMME5_RTR_LBW_E_ARB_MAX 0x140220
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#define mmMME5_RTR_LBW_W_ARB_MAX 0x140224
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#define mmMME5_RTR_LBW_N_ARB_MAX 0x140228
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#define mmMME5_RTR_LBW_S_ARB_MAX 0x14022C
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#define mmMME5_RTR_LBW_L_ARB_MAX 0x140230
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#define mmMME5_RTR_LBW_SRAM_MAX_CREDIT 0x140240
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#define mmMME5_RTR_LBW_RD_RS_E_ARB 0x140250
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#define mmMME5_RTR_LBW_RD_RS_W_ARB 0x140254
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#define mmMME5_RTR_LBW_RD_RS_N_ARB 0x140258
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#define mmMME5_RTR_LBW_RD_RS_S_ARB 0x14025C
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#define mmMME5_RTR_LBW_RD_RS_L_ARB 0x140260
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#define mmMME5_RTR_LBW_WR_RQ_E_ARB 0x140270
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#define mmMME5_RTR_LBW_WR_RQ_W_ARB 0x140274
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#define mmMME5_RTR_LBW_WR_RQ_N_ARB 0x140278
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#define mmMME5_RTR_LBW_WR_RQ_S_ARB 0x14027C
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#define mmMME5_RTR_LBW_WR_RQ_L_ARB 0x140280
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#define mmMME5_RTR_LBW_WR_RS_E_ARB 0x140290
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#define mmMME5_RTR_LBW_WR_RS_W_ARB 0x140294
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#define mmMME5_RTR_LBW_WR_RS_N_ARB 0x140298
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#define mmMME5_RTR_LBW_WR_RS_S_ARB 0x14029C
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#define mmMME5_RTR_LBW_WR_RS_L_ARB 0x1402A0
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#define mmMME5_RTR_DBG_E_ARB 0x140300
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#define mmMME5_RTR_DBG_W_ARB 0x140304
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#define mmMME5_RTR_DBG_N_ARB 0x140308
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#define mmMME5_RTR_DBG_S_ARB 0x14030C
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#define mmMME5_RTR_DBG_L_ARB 0x140310
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#define mmMME5_RTR_DBG_E_ARB_MAX 0x140320
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#define mmMME5_RTR_DBG_W_ARB_MAX 0x140324
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#define mmMME5_RTR_DBG_N_ARB_MAX 0x140328
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#define mmMME5_RTR_DBG_S_ARB_MAX 0x14032C
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#define mmMME5_RTR_DBG_L_ARB_MAX 0x140330
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#define mmMME5_RTR_SPLIT_COEF_0 0x140400
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#define mmMME5_RTR_SPLIT_COEF_1 0x140404
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#define mmMME5_RTR_SPLIT_COEF_2 0x140408
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#define mmMME5_RTR_SPLIT_COEF_3 0x14040C
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#define mmMME5_RTR_SPLIT_COEF_4 0x140410
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#define mmMME5_RTR_SPLIT_COEF_5 0x140414
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#define mmMME5_RTR_SPLIT_COEF_6 0x140418
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#define mmMME5_RTR_SPLIT_COEF_7 0x14041C
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#define mmMME5_RTR_SPLIT_COEF_8 0x140420
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#define mmMME5_RTR_SPLIT_COEF_9 0x140424
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#define mmMME5_RTR_SPLIT_CFG 0x140440
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#define mmMME5_RTR_SPLIT_RD_SAT 0x140444
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#define mmMME5_RTR_SPLIT_RD_RST_TOKEN 0x140448
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#define mmMME5_RTR_SPLIT_RD_TIMEOUT_0 0x14044C
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#define mmMME5_RTR_SPLIT_RD_TIMEOUT_1 0x140450
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#define mmMME5_RTR_SPLIT_WR_SAT 0x140454
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#define mmMME5_RTR_WPLIT_WR_TST_TOLEN 0x140458
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#define mmMME5_RTR_SPLIT_WR_TIMEOUT_0 0x14045C
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#define mmMME5_RTR_SPLIT_WR_TIMEOUT_1 0x140460
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#define mmMME5_RTR_HBW_RANGE_HIT 0x140470
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#define mmMME5_RTR_HBW_RANGE_MASK_L_0 0x140480
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#define mmMME5_RTR_HBW_RANGE_MASK_L_1 0x140484
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#define mmMME5_RTR_HBW_RANGE_MASK_L_2 0x140488
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#define mmMME5_RTR_HBW_RANGE_MASK_L_3 0x14048C
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#define mmMME5_RTR_HBW_RANGE_MASK_L_4 0x140490
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#define mmMME5_RTR_HBW_RANGE_MASK_L_5 0x140494
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#define mmMME5_RTR_HBW_RANGE_MASK_L_6 0x140498
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#define mmMME5_RTR_HBW_RANGE_MASK_L_7 0x14049C
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#define mmMME5_RTR_HBW_RANGE_MASK_H_0 0x1404A0
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#define mmMME5_RTR_HBW_RANGE_MASK_H_1 0x1404A4
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#define mmMME5_RTR_HBW_RANGE_MASK_H_2 0x1404A8
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#define mmMME5_RTR_HBW_RANGE_MASK_H_3 0x1404AC
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#define mmMME5_RTR_HBW_RANGE_MASK_H_4 0x1404B0
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#define mmMME5_RTR_HBW_RANGE_MASK_H_5 0x1404B4
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#define mmMME5_RTR_HBW_RANGE_MASK_H_6 0x1404B8
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#define mmMME5_RTR_HBW_RANGE_MASK_H_7 0x1404BC
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#define mmMME5_RTR_HBW_RANGE_BASE_L_0 0x1404C0
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#define mmMME5_RTR_HBW_RANGE_BASE_L_1 0x1404C4
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#define mmMME5_RTR_HBW_RANGE_BASE_L_2 0x1404C8
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#define mmMME5_RTR_HBW_RANGE_BASE_L_3 0x1404CC
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#define mmMME5_RTR_HBW_RANGE_BASE_L_4 0x1404D0
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#define mmMME5_RTR_HBW_RANGE_BASE_L_5 0x1404D4
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#define mmMME5_RTR_HBW_RANGE_BASE_L_6 0x1404D8
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#define mmMME5_RTR_HBW_RANGE_BASE_L_7 0x1404DC
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#define mmMME5_RTR_HBW_RANGE_BASE_H_0 0x1404E0
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#define mmMME5_RTR_HBW_RANGE_BASE_H_1 0x1404E4
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#define mmMME5_RTR_HBW_RANGE_BASE_H_2 0x1404E8
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#define mmMME5_RTR_HBW_RANGE_BASE_H_3 0x1404EC
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#define mmMME5_RTR_HBW_RANGE_BASE_H_4 0x1404F0
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#define mmMME5_RTR_HBW_RANGE_BASE_H_5 0x1404F4
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#define mmMME5_RTR_HBW_RANGE_BASE_H_6 0x1404F8
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#define mmMME5_RTR_HBW_RANGE_BASE_H_7 0x1404FC
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#define mmMME5_RTR_LBW_RANGE_HIT 0x140500
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#define mmMME5_RTR_LBW_RANGE_MASK_0 0x140510
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#define mmMME5_RTR_LBW_RANGE_MASK_1 0x140514
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#define mmMME5_RTR_LBW_RANGE_MASK_2 0x140518
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#define mmMME5_RTR_LBW_RANGE_MASK_3 0x14051C
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#define mmMME5_RTR_LBW_RANGE_MASK_4 0x140520
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#define mmMME5_RTR_LBW_RANGE_MASK_5 0x140524
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#define mmMME5_RTR_LBW_RANGE_MASK_6 0x140528
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#define mmMME5_RTR_LBW_RANGE_MASK_7 0x14052C
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#define mmMME5_RTR_LBW_RANGE_MASK_8 0x140530
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#define mmMME5_RTR_LBW_RANGE_MASK_9 0x140534
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#define mmMME5_RTR_LBW_RANGE_MASK_10 0x140538
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#define mmMME5_RTR_LBW_RANGE_MASK_11 0x14053C
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#define mmMME5_RTR_LBW_RANGE_MASK_12 0x140540
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#define mmMME5_RTR_LBW_RANGE_MASK_13 0x140544
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#define mmMME5_RTR_LBW_RANGE_MASK_14 0x140548
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#define mmMME5_RTR_LBW_RANGE_MASK_15 0x14054C
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#define mmMME5_RTR_LBW_RANGE_BASE_0 0x140550
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#define mmMME5_RTR_LBW_RANGE_BASE_1 0x140554
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#define mmMME5_RTR_LBW_RANGE_BASE_2 0x140558
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#define mmMME5_RTR_LBW_RANGE_BASE_3 0x14055C
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#define mmMME5_RTR_LBW_RANGE_BASE_4 0x140560
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#define mmMME5_RTR_LBW_RANGE_BASE_5 0x140564
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#define mmMME5_RTR_LBW_RANGE_BASE_6 0x140568
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#define mmMME5_RTR_LBW_RANGE_BASE_7 0x14056C
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#define mmMME5_RTR_LBW_RANGE_BASE_8 0x140570
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#define mmMME5_RTR_LBW_RANGE_BASE_9 0x140574
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#define mmMME5_RTR_LBW_RANGE_BASE_10 0x140578
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#define mmMME5_RTR_LBW_RANGE_BASE_11 0x14057C
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#define mmMME5_RTR_LBW_RANGE_BASE_12 0x140580
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#define mmMME5_RTR_LBW_RANGE_BASE_13 0x140584
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#define mmMME5_RTR_LBW_RANGE_BASE_14 0x140588
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#define mmMME5_RTR_LBW_RANGE_BASE_15 0x14058C
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#define mmMME5_RTR_RGLTR 0x140590
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#define mmMME5_RTR_RGLTR_WR_RESULT 0x140594
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#define mmMME5_RTR_RGLTR_RD_RESULT 0x140598
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#define mmMME5_RTR_SCRAMB_EN 0x140600
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#define mmMME5_RTR_NON_LIN_SCRAMB 0x140604
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#endif /* ASIC_REG_MME5_RTR_REGS_H_ */
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