Jean-Philippe Brucker f6c86a41e1 irqchip/gic-v3: Change unsigned types for AArch32 compatibility ... This patch does a few simple compatibility-related changes: - change the system register access prototypes to their actual size, - homogenise mpidr accesses with unsigned long, - force the 64bit register values to unsigned long long. Note: the list registers are 64bit on GICv3, but the AArch32 vGIC driver will need to split their values into two 32bit registers: LRn and LRCn. Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>		2015-10-09 23:11:52 +01:00
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arm-gic-acpi.h
arm-gic-v3.h	irqchip/gic-v3: Change unsigned types for AArch32 compatibility	2015-10-09 23:11:52 +01:00
arm-gic.h	ARM:	2015-09-10 16:42:49 -07:00
arm-vic.h
chained_irq.h
ingenic.h	MIPS/IRQCHIP: Move Ingenic SoC intc driver to drivers/irqchip	2015-06-21 21:53:10 +02:00
irq-omap-intc.h
irq-sa11x0.h	ARM: 8367/1: sa1100: prepare for moving irq driver to drivers/irqchip	2015-05-28 14:40:03 +01:00
metag-ext.h
metag.h
mips-gic.h	IRQCHIP: irq-mips-gic: Add support for CM3 64-bit timer irqs	2015-08-26 15:23:17 +02:00
mmp.h
mxs.h
versatile-fpga.h
xtensa-mx.h
xtensa-pic.h