529e5fbcd8
Pull late ARM updates from Russell King:
"Here is the late set of ARM updates for this merge window; in here is:
- The ARM parts of the broadcast timer support, core parts merged
through tglx's tree. This was left over from the previous merge to
allow the dependency on tglx's tree to be resolved.
- A fix to the VFP code which shows up on Raspberry Pi's, as well as
fixing the fallout from a previous commit in this area.
- A number of smaller fixes scattered throughout the ARM tree"
* 'for-linus' of git://git.linaro.org/people/rmk/linux-arm:
ARM: Fix broken commit 0cc41e4a21 corrupting kernel messages
ARM: fix scheduling while atomic warning in alignment handling code
ARM: VFP: fix emulation of second VFP instruction
ARM: 7656/1: uImage: Error out on build of multiplatform without LOADADDR
ARM: 7640/1: memory: tegra_ahb_enable_smmu() depends on TEGRA_IOMMU_SMMU
ARM: 7654/1: Preserve L_PTE_VALID in pte_modify()
ARM: 7653/2: do not scale loops_per_jiffy when using a constant delay clock
ARM: 7651/1: remove unused smp_timer_broadcast #define
292 lines
7.4 KiB
C
292 lines
7.4 KiB
C
/*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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* Copyright (C) 2011 Google, Inc.
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*
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* Author:
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* Jay Cheng <jacheng@nvidia.com>
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* James Wylder <james.wylder@motorola.com>
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* Benoit Goby <benoit@android.com>
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* Colin Cross <ccross@android.com>
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* Hiroshi DOYU <hdoyu@nvidia.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/tegra-ahb.h>
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#define DRV_NAME "tegra-ahb"
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#define AHB_ARBITRATION_DISABLE 0x00
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#define AHB_ARBITRATION_PRIORITY_CTRL 0x04
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#define AHB_PRIORITY_WEIGHT(x) (((x) & 0x7) << 29)
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#define PRIORITY_SELECT_USB BIT(6)
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#define PRIORITY_SELECT_USB2 BIT(18)
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#define PRIORITY_SELECT_USB3 BIT(17)
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#define AHB_GIZMO_AHB_MEM 0x0c
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#define ENB_FAST_REARBITRATE BIT(2)
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#define DONT_SPLIT_AHB_WR BIT(7)
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#define AHB_GIZMO_APB_DMA 0x10
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#define AHB_GIZMO_IDE 0x18
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#define AHB_GIZMO_USB 0x1c
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#define AHB_GIZMO_AHB_XBAR_BRIDGE 0x20
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#define AHB_GIZMO_CPU_AHB_BRIDGE 0x24
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#define AHB_GIZMO_COP_AHB_BRIDGE 0x28
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#define AHB_GIZMO_XBAR_APB_CTLR 0x2c
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#define AHB_GIZMO_VCP_AHB_BRIDGE 0x30
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#define AHB_GIZMO_NAND 0x3c
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#define AHB_GIZMO_SDMMC4 0x44
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#define AHB_GIZMO_XIO 0x48
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#define AHB_GIZMO_BSEV 0x60
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#define AHB_GIZMO_BSEA 0x70
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#define AHB_GIZMO_NOR 0x74
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#define AHB_GIZMO_USB2 0x78
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#define AHB_GIZMO_USB3 0x7c
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#define IMMEDIATE BIT(18)
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#define AHB_GIZMO_SDMMC1 0x80
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#define AHB_GIZMO_SDMMC2 0x84
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#define AHB_GIZMO_SDMMC3 0x88
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#define AHB_MEM_PREFETCH_CFG_X 0xd8
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#define AHB_ARBITRATION_XBAR_CTRL 0xdc
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#define AHB_MEM_PREFETCH_CFG3 0xe0
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#define AHB_MEM_PREFETCH_CFG4 0xe4
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#define AHB_MEM_PREFETCH_CFG1 0xec
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#define AHB_MEM_PREFETCH_CFG2 0xf0
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#define PREFETCH_ENB BIT(31)
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#define MST_ID(x) (((x) & 0x1f) << 26)
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#define AHBDMA_MST_ID MST_ID(5)
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#define USB_MST_ID MST_ID(6)
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#define USB2_MST_ID MST_ID(18)
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#define USB3_MST_ID MST_ID(17)
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#define ADDR_BNDRY(x) (((x) & 0xf) << 21)
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#define INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
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#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID 0xf8
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#define AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE BIT(17)
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static struct platform_driver tegra_ahb_driver;
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static const u32 tegra_ahb_gizmo[] = {
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AHB_ARBITRATION_DISABLE,
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AHB_ARBITRATION_PRIORITY_CTRL,
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AHB_GIZMO_AHB_MEM,
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AHB_GIZMO_APB_DMA,
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AHB_GIZMO_IDE,
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AHB_GIZMO_USB,
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AHB_GIZMO_AHB_XBAR_BRIDGE,
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AHB_GIZMO_CPU_AHB_BRIDGE,
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AHB_GIZMO_COP_AHB_BRIDGE,
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AHB_GIZMO_XBAR_APB_CTLR,
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AHB_GIZMO_VCP_AHB_BRIDGE,
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AHB_GIZMO_NAND,
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AHB_GIZMO_SDMMC4,
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AHB_GIZMO_XIO,
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AHB_GIZMO_BSEV,
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AHB_GIZMO_BSEA,
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AHB_GIZMO_NOR,
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AHB_GIZMO_USB2,
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AHB_GIZMO_USB3,
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AHB_GIZMO_SDMMC1,
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AHB_GIZMO_SDMMC2,
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AHB_GIZMO_SDMMC3,
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AHB_MEM_PREFETCH_CFG_X,
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AHB_ARBITRATION_XBAR_CTRL,
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AHB_MEM_PREFETCH_CFG3,
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AHB_MEM_PREFETCH_CFG4,
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AHB_MEM_PREFETCH_CFG1,
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AHB_MEM_PREFETCH_CFG2,
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AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID,
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};
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struct tegra_ahb {
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void __iomem *regs;
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struct device *dev;
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u32 ctx[0];
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};
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static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset)
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{
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return readl(ahb->regs + offset);
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}
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static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset)
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{
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writel(value, ahb->regs + offset);
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}
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#ifdef CONFIG_TEGRA_IOMMU_SMMU
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static int tegra_ahb_match_by_smmu(struct device *dev, void *data)
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{
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struct tegra_ahb *ahb = dev_get_drvdata(dev);
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struct device_node *dn = data;
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return (ahb->dev->of_node == dn) ? 1 : 0;
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}
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int tegra_ahb_enable_smmu(struct device_node *dn)
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{
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struct device *dev;
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u32 val;
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struct tegra_ahb *ahb;
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dev = driver_find_device(&tegra_ahb_driver.driver, NULL, dn,
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tegra_ahb_match_by_smmu);
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if (!dev)
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return -EPROBE_DEFER;
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ahb = dev_get_drvdata(dev);
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val = gizmo_readl(ahb, AHB_ARBITRATION_XBAR_CTRL);
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val |= AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE;
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gizmo_writel(ahb, val, AHB_ARBITRATION_XBAR_CTRL);
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return 0;
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}
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EXPORT_SYMBOL(tegra_ahb_enable_smmu);
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#endif
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#ifdef CONFIG_PM_SLEEP
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static int tegra_ahb_suspend(struct device *dev)
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{
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int i;
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struct tegra_ahb *ahb = dev_get_drvdata(dev);
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for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
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ahb->ctx[i] = gizmo_readl(ahb, tegra_ahb_gizmo[i]);
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return 0;
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}
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static int tegra_ahb_resume(struct device *dev)
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{
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int i;
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struct tegra_ahb *ahb = dev_get_drvdata(dev);
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for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
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gizmo_writel(ahb, ahb->ctx[i], tegra_ahb_gizmo[i]);
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return 0;
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}
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#endif
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static UNIVERSAL_DEV_PM_OPS(tegra_ahb_pm,
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tegra_ahb_suspend,
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tegra_ahb_resume, NULL);
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static void tegra_ahb_gizmo_init(struct tegra_ahb *ahb)
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{
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u32 val;
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val = gizmo_readl(ahb, AHB_GIZMO_AHB_MEM);
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val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
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gizmo_writel(ahb, val, AHB_GIZMO_AHB_MEM);
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val = gizmo_readl(ahb, AHB_GIZMO_USB);
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val |= IMMEDIATE;
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gizmo_writel(ahb, val, AHB_GIZMO_USB);
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val = gizmo_readl(ahb, AHB_GIZMO_USB2);
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val |= IMMEDIATE;
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gizmo_writel(ahb, val, AHB_GIZMO_USB2);
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val = gizmo_readl(ahb, AHB_GIZMO_USB3);
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val |= IMMEDIATE;
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gizmo_writel(ahb, val, AHB_GIZMO_USB3);
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val = gizmo_readl(ahb, AHB_ARBITRATION_PRIORITY_CTRL);
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val |= PRIORITY_SELECT_USB |
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PRIORITY_SELECT_USB2 |
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PRIORITY_SELECT_USB3 |
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AHB_PRIORITY_WEIGHT(7);
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gizmo_writel(ahb, val, AHB_ARBITRATION_PRIORITY_CTRL);
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val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG1);
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val &= ~MST_ID(~0);
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val |= PREFETCH_ENB |
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AHBDMA_MST_ID |
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ADDR_BNDRY(0xc) |
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INACTIVITY_TIMEOUT(0x1000);
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gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG1);
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val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG2);
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val &= ~MST_ID(~0);
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val |= PREFETCH_ENB |
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USB_MST_ID |
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ADDR_BNDRY(0xc) |
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INACTIVITY_TIMEOUT(0x1000);
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gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG2);
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val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG3);
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val &= ~MST_ID(~0);
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val |= PREFETCH_ENB |
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USB3_MST_ID |
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ADDR_BNDRY(0xc) |
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INACTIVITY_TIMEOUT(0x1000);
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gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG3);
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val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG4);
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val &= ~MST_ID(~0);
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val |= PREFETCH_ENB |
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USB2_MST_ID |
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ADDR_BNDRY(0xc) |
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INACTIVITY_TIMEOUT(0x1000);
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gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG4);
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}
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static int tegra_ahb_probe(struct platform_device *pdev)
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{
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struct resource *res;
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struct tegra_ahb *ahb;
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size_t bytes;
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bytes = sizeof(*ahb) + sizeof(u32) * ARRAY_SIZE(tegra_ahb_gizmo);
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ahb = devm_kzalloc(&pdev->dev, bytes, GFP_KERNEL);
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if (!ahb)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENODEV;
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ahb->regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(ahb->regs))
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return PTR_ERR(ahb->regs);
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ahb->dev = &pdev->dev;
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platform_set_drvdata(pdev, ahb);
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tegra_ahb_gizmo_init(ahb);
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return 0;
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}
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static const struct of_device_id tegra_ahb_of_match[] = {
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{ .compatible = "nvidia,tegra30-ahb", },
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{ .compatible = "nvidia,tegra20-ahb", },
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{},
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};
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static struct platform_driver tegra_ahb_driver = {
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.probe = tegra_ahb_probe,
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.driver = {
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.name = DRV_NAME,
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.owner = THIS_MODULE,
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.of_match_table = tegra_ahb_of_match,
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.pm = &tegra_ahb_pm,
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},
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};
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module_platform_driver(tegra_ahb_driver);
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MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
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MODULE_DESCRIPTION("Tegra AHB driver");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:" DRV_NAME);
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