53 lines
2.6 KiB
JSON
53 lines
2.6 KiB
JSON
[
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{
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"PublicDescription": "lpddr4 mek board bandwidth usage",
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"BriefDescription": "imx8qm: percentage of bandwidth usage for ddr0",
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"MetricName": "imx8qm-ddr0-bandwidth-usage",
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"MetricExpr": "(( imx8_ddr0\\/read\\-cycles\\/ + imx8_ddr0\\/write\\-cycles\\/) * 4 * 4 / duration_time) / (800 * 1000000 * 4 * 4)",
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"MetricGroup": "i.MX8QM_DDR_MON",
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"ScaleUnit": "1e2%",
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"SocName": "i.MX8QM"
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},
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{
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"PublicDescription": "Calculate bytes all masters read from DDR based on read-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 4 bytes of each beat if DDR burst width is 32 bit.",
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"BriefDescription": "imx8qm: bytes of all masters read from ddr0",
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"MetricName": "imx8qm-ddr0-all-r",
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"MetricExpr": "imx8_ddr0\\/read\\-cycles\\/ * 4 * 4",
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"MetricGroup": "i.MX8QM_DDR_MON",
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"SocName": "i.MX8QM"
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},
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{
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"PublicDescription": "Calculate bytes all masters wirte to DDR based on write-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 4 bytes of each beat if DDR burst width is 32 bit.",
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"BriefDescription": "imx8qm: bytes of all masters write to ddr0",
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"MetricName": "imx8qm-ddr0-all-w",
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"MetricExpr": "imx8_ddr0\\/write\\-cycles\\/ * 4 * 4",
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"MetricGroup": "i.MX8QM_DDR_MON",
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"SocName": "i.MX8QM"
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},
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{
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"PublicDescription": "lpddr4 mek board bandwidth usage",
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"BriefDescription": "imx8qm: percentage of bandwidth usage for ddr1",
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"MetricName": "imx8qm-ddr1-bandwidth-usage",
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"MetricExpr": "(( imx8_ddr1\\/read\\-cycles\\/ + imx8_ddr1\\/write\\-cycles\\/) * 4 * 4 / duration_time) / (800 * 1000000 * 4 * 4)",
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"MetricGroup": "i.MX8QM_DDR_MON",
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"ScaleUnit": "1e2%",
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"SocName": "i.MX8QM"
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},
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{
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"PublicDescription": "Calculate bytes all masters read from DDR based on read-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 4 bytes of each beat if DDR burst width is 32 bit.",
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"BriefDescription": "imx8qm: bytes of all masters read from ddr1",
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"MetricName": "imx8qm-ddr1-all-r",
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"MetricExpr": "imx8_ddr1\\/read\\-cycles\\/ * 4 * 4",
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"MetricGroup": "i.MX8QM_DDR_MON",
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"SocName": "i.MX8QM"
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},
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{
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"PublicDescription": "Calculate bytes all masters wirte to DDR based on write-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 4 bytes of each beat if DDR burst width is 32 bit.",
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"BriefDescription": "imx8qm: bytes of all masters write to ddr1",
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"MetricName": "imx8qm-ddr1-all-w",
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"MetricExpr": "imx8_ddr1\\/write\\-cycles\\/ * 4 * 4",
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"MetricGroup": "i.MX8QM_DDR_MON",
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"SocName": "i.MX8QM"
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}
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]
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