3489d5067a
Use the common DAI DMA data struct for tegra, this allows us to use the common helper function to configure the DMA slave config based on the DAI DMA data. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
164 lines
7.5 KiB
C
164 lines
7.5 KiB
C
/*
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* tegra20_i2s.h - Definitions for Tegra20 I2S driver
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*
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* Author: Stephen Warren <swarren@nvidia.com>
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* Copyright (C) 2010,2012 - NVIDIA, Inc.
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*
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* Based on code copyright/by:
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*
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* Copyright (c) 2009-2010, NVIDIA Corporation.
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* Scott Peterson <speterson@nvidia.com>
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*
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* Copyright (C) 2010 Google, Inc.
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* Iliyan Malchev <malchev@google.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#ifndef __TEGRA20_I2S_H__
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#define __TEGRA20_I2S_H__
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#include "tegra_pcm.h"
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/* Register offsets from TEGRA20_I2S1_BASE and TEGRA20_I2S2_BASE */
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#define TEGRA20_I2S_CTRL 0x00
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#define TEGRA20_I2S_STATUS 0x04
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#define TEGRA20_I2S_TIMING 0x08
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#define TEGRA20_I2S_FIFO_SCR 0x0c
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#define TEGRA20_I2S_PCM_CTRL 0x10
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#define TEGRA20_I2S_NW_CTRL 0x14
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#define TEGRA20_I2S_TDM_CTRL 0x20
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#define TEGRA20_I2S_TDM_TX_RX_CTRL 0x24
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#define TEGRA20_I2S_FIFO1 0x40
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#define TEGRA20_I2S_FIFO2 0x80
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/* Fields in TEGRA20_I2S_CTRL */
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#define TEGRA20_I2S_CTRL_FIFO2_TX_ENABLE (1 << 30)
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#define TEGRA20_I2S_CTRL_FIFO1_ENABLE (1 << 29)
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#define TEGRA20_I2S_CTRL_FIFO2_ENABLE (1 << 28)
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#define TEGRA20_I2S_CTRL_FIFO1_RX_ENABLE (1 << 27)
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#define TEGRA20_I2S_CTRL_FIFO_LPBK_ENABLE (1 << 26)
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#define TEGRA20_I2S_CTRL_MASTER_ENABLE (1 << 25)
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#define TEGRA20_I2S_LRCK_LEFT_LOW 0
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#define TEGRA20_I2S_LRCK_RIGHT_LOW 1
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#define TEGRA20_I2S_CTRL_LRCK_SHIFT 24
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#define TEGRA20_I2S_CTRL_LRCK_MASK (1 << TEGRA20_I2S_CTRL_LRCK_SHIFT)
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#define TEGRA20_I2S_CTRL_LRCK_L_LOW (TEGRA20_I2S_LRCK_LEFT_LOW << TEGRA20_I2S_CTRL_LRCK_SHIFT)
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#define TEGRA20_I2S_CTRL_LRCK_R_LOW (TEGRA20_I2S_LRCK_RIGHT_LOW << TEGRA20_I2S_CTRL_LRCK_SHIFT)
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#define TEGRA20_I2S_BIT_FORMAT_I2S 0
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#define TEGRA20_I2S_BIT_FORMAT_RJM 1
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#define TEGRA20_I2S_BIT_FORMAT_LJM 2
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#define TEGRA20_I2S_BIT_FORMAT_DSP 3
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#define TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT 10
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#define TEGRA20_I2S_CTRL_BIT_FORMAT_MASK (3 << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
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#define TEGRA20_I2S_CTRL_BIT_FORMAT_I2S (TEGRA20_I2S_BIT_FORMAT_I2S << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
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#define TEGRA20_I2S_CTRL_BIT_FORMAT_RJM (TEGRA20_I2S_BIT_FORMAT_RJM << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
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#define TEGRA20_I2S_CTRL_BIT_FORMAT_LJM (TEGRA20_I2S_BIT_FORMAT_LJM << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
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#define TEGRA20_I2S_CTRL_BIT_FORMAT_DSP (TEGRA20_I2S_BIT_FORMAT_DSP << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
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#define TEGRA20_I2S_BIT_SIZE_16 0
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#define TEGRA20_I2S_BIT_SIZE_20 1
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#define TEGRA20_I2S_BIT_SIZE_24 2
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#define TEGRA20_I2S_BIT_SIZE_32 3
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#define TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT 8
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#define TEGRA20_I2S_CTRL_BIT_SIZE_MASK (3 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
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#define TEGRA20_I2S_CTRL_BIT_SIZE_16 (TEGRA20_I2S_BIT_SIZE_16 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
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#define TEGRA20_I2S_CTRL_BIT_SIZE_20 (TEGRA20_I2S_BIT_SIZE_20 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
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#define TEGRA20_I2S_CTRL_BIT_SIZE_24 (TEGRA20_I2S_BIT_SIZE_24 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
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#define TEGRA20_I2S_CTRL_BIT_SIZE_32 (TEGRA20_I2S_BIT_SIZE_32 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
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#define TEGRA20_I2S_FIFO_16_LSB 0
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#define TEGRA20_I2S_FIFO_20_LSB 1
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#define TEGRA20_I2S_FIFO_24_LSB 2
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#define TEGRA20_I2S_FIFO_32 3
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#define TEGRA20_I2S_FIFO_PACKED 7
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#define TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT 4
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#define TEGRA20_I2S_CTRL_FIFO_FORMAT_MASK (7 << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
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#define TEGRA20_I2S_CTRL_FIFO_FORMAT_16_LSB (TEGRA20_I2S_FIFO_16_LSB << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
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#define TEGRA20_I2S_CTRL_FIFO_FORMAT_20_LSB (TEGRA20_I2S_FIFO_20_LSB << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
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#define TEGRA20_I2S_CTRL_FIFO_FORMAT_24_LSB (TEGRA20_I2S_FIFO_24_LSB << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
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#define TEGRA20_I2S_CTRL_FIFO_FORMAT_32 (TEGRA20_I2S_FIFO_32 << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
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#define TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED (TEGRA20_I2S_FIFO_PACKED << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
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#define TEGRA20_I2S_CTRL_IE_FIFO1_ERR (1 << 3)
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#define TEGRA20_I2S_CTRL_IE_FIFO2_ERR (1 << 2)
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#define TEGRA20_I2S_CTRL_QE_FIFO1 (1 << 1)
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#define TEGRA20_I2S_CTRL_QE_FIFO2 (1 << 0)
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/* Fields in TEGRA20_I2S_STATUS */
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#define TEGRA20_I2S_STATUS_FIFO1_RDY (1 << 31)
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#define TEGRA20_I2S_STATUS_FIFO2_RDY (1 << 30)
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#define TEGRA20_I2S_STATUS_FIFO1_BSY (1 << 29)
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#define TEGRA20_I2S_STATUS_FIFO2_BSY (1 << 28)
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#define TEGRA20_I2S_STATUS_FIFO1_ERR (1 << 3)
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#define TEGRA20_I2S_STATUS_FIFO2_ERR (1 << 2)
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#define TEGRA20_I2S_STATUS_QS_FIFO1 (1 << 1)
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#define TEGRA20_I2S_STATUS_QS_FIFO2 (1 << 0)
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/* Fields in TEGRA20_I2S_TIMING */
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#define TEGRA20_I2S_TIMING_NON_SYM_ENABLE (1 << 12)
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#define TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT 0
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#define TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US 0x7ff
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#define TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK (TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US << TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT)
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/* Fields in TEGRA20_I2S_FIFO_SCR */
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#define TEGRA20_I2S_FIFO_SCR_FIFO2_FULL_EMPTY_COUNT_SHIFT 24
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#define TEGRA20_I2S_FIFO_SCR_FIFO1_FULL_EMPTY_COUNT_SHIFT 16
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#define TEGRA20_I2S_FIFO_SCR_FIFO_FULL_EMPTY_COUNT_MASK 0x3f
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#define TEGRA20_I2S_FIFO_SCR_FIFO2_CLR (1 << 12)
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#define TEGRA20_I2S_FIFO_SCR_FIFO1_CLR (1 << 8)
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#define TEGRA20_I2S_FIFO_ATN_LVL_ONE_SLOT 0
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#define TEGRA20_I2S_FIFO_ATN_LVL_FOUR_SLOTS 1
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#define TEGRA20_I2S_FIFO_ATN_LVL_EIGHT_SLOTS 2
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#define TEGRA20_I2S_FIFO_ATN_LVL_TWELVE_SLOTS 3
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#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT 4
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#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_MASK (3 << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
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#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_ONE_SLOT (TEGRA20_I2S_FIFO_ATN_LVL_ONE_SLOT << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
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#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_FOUR_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
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#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_EIGHT_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_EIGHT_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
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#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_TWELVE_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_TWELVE_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
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#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT 0
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#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_MASK (3 << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
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#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_ONE_SLOT (TEGRA20_I2S_FIFO_ATN_LVL_ONE_SLOT << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
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#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_FOUR_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
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#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_EIGHT_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_EIGHT_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
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#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_TWELVE_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_TWELVE_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
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struct tegra20_i2s {
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struct snd_soc_dai_driver dai;
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struct clk *clk_i2s;
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struct snd_dmaengine_dai_dma_data capture_dma_data;
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struct snd_dmaengine_dai_dma_data playback_dma_data;
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struct regmap *regmap;
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};
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#endif
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