d23f3839fe
Add pcie1 dt node in order for the controller to operate in endpoint mode. However since none of the dra7 based boards have slots configured to operate in endpoint mode, keep EP mode disabled. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
570 lines
13 KiB
Plaintext
570 lines
13 KiB
Plaintext
/*
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* Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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#include "dra72x.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clk/ti-dra7-atl.h>
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/ {
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compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
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aliases {
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display0 = &hdmi0;
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};
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chosen {
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stdout-path = &uart1;
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};
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evm_12v0: fixedregulator-evm12v0 {
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/* main supply */
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compatible = "regulator-fixed";
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regulator-name = "evm_12v0";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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regulator-always-on;
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regulator-boot-on;
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};
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evm_5v0: fixedregulator-evm5v0 {
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/* Output 1 of TPS43351QDAPRQ1 on dra72-evm */
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/* Output 1 of LM5140QRWGTQ1 on dra71-evm */
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compatible = "regulator-fixed";
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regulator-name = "evm_5v0";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&evm_12v0>;
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regulator-always-on;
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regulator-boot-on;
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};
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vsys_3v3: fixedregulator-vsys3v3 {
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/* Output 2 of TPS43351QDAPRQ1 on dra72-evm */
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/* Output 2 of LM5140QRWGTQ1 on dra71-evm */
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compatible = "regulator-fixed";
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regulator-name = "vsys_3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&evm_12v0>;
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regulator-always-on;
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regulator-boot-on;
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};
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evm_3v3_sw: fixedregulator-evm_3v3 {
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/* TPS22965DSG */
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compatible = "regulator-fixed";
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regulator-name = "evm_3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&vsys_3v3>;
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regulator-always-on;
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regulator-boot-on;
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};
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aic_dvdd: fixedregulator-aic_dvdd {
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/* TPS77018DBVT */
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compatible = "regulator-fixed";
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regulator-name = "aic_dvdd";
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vin-supply = <&evm_3v3_sw>;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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evm_3v3_sd: fixedregulator-sd {
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compatible = "regulator-fixed";
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regulator-name = "evm_3v3_sd";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&evm_3v3_sw>;
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enable-active-high;
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gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
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};
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extcon_usb1: extcon_usb1 {
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compatible = "linux,extcon-usb-gpio";
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id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
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};
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extcon_usb2: extcon_usb2 {
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compatible = "linux,extcon-usb-gpio";
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id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
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};
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hdmi0: connector {
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compatible = "hdmi-connector";
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label = "hdmi";
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type = "a";
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port {
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hdmi_connector_in: endpoint {
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remote-endpoint = <&tpd12s015_out>;
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};
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};
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};
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tpd12s015: encoder {
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compatible = "ti,tpd12s015";
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gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
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<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
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<&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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tpd12s015_in: endpoint {
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remote-endpoint = <&hdmi_out>;
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};
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};
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port@1 {
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reg = <1>;
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tpd12s015_out: endpoint {
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remote-endpoint = <&hdmi_connector_in>;
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};
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};
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};
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};
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sound0: sound0 {
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compatible = "simple-audio-card";
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simple-audio-card,name = "DRA7xx-EVM";
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simple-audio-card,widgets =
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"Headphone", "Headphone Jack",
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"Line", "Line Out",
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"Microphone", "Mic Jack",
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"Line", "Line In";
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simple-audio-card,routing =
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"Headphone Jack", "HPLOUT",
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"Headphone Jack", "HPROUT",
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"Line Out", "LLOUT",
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"Line Out", "RLOUT",
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"MIC3L", "Mic Jack",
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"MIC3R", "Mic Jack",
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"Mic Jack", "Mic Bias",
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"LINE1L", "Line In",
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"LINE1R", "Line In";
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simple-audio-card,format = "dsp_b";
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simple-audio-card,bitclock-master = <&sound0_master>;
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simple-audio-card,frame-master = <&sound0_master>;
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simple-audio-card,bitclock-inversion;
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sound0_master: simple-audio-card,cpu {
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sound-dai = <&mcasp3>;
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system-clock-frequency = <5644800>;
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};
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simple-audio-card,codec {
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sound-dai = <&tlv320aic3106>;
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clocks = <&atl_clkin2_ck>;
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};
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};
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};
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&dra7_pmx_core {
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mmc1_pins_default: mmc1_pins_default {
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pinctrl-single,pins = <
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DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
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DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
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DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
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DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
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DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
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DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
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DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
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>;
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};
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mmc2_pins_default: mmc2_pins_default {
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pinctrl-single,pins = <
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DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
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DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
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DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
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DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
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DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
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DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
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DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
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DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
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DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
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DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
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>;
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};
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dcan1_pins_default: dcan1_pins_default {
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pinctrl-single,pins = <
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DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
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DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
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>;
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};
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dcan1_pins_sleep: dcan1_pins_sleep {
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pinctrl-single,pins = <
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DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
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DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
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>;
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};
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};
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&i2c1 {
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status = "okay";
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clock-frequency = <400000>;
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pcf_lcd: gpio@20 {
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compatible = "nxp,pcf8575";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pcf_gpio_21: gpio@21 {
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compatible = "ti,pcf8575", "nxp,pcf8575";
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reg = <0x21>;
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lines-initial-states = <0x1408>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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tlv320aic3106: tlv320aic3106@19 {
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#sound-dai-cells = <0>;
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compatible = "ti,tlv320aic3106";
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reg = <0x19>;
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adc-settle-ms = <40>;
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ai3x-micbias-vg = <1>; /* 2.0V */
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status = "okay";
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/* Regulators */
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AVDD-supply = <&evm_3v3_sw>;
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IOVDD-supply = <&evm_3v3_sw>;
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DRVDD-supply = <&evm_3v3_sw>;
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DVDD-supply = <&aic_dvdd>;
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};
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};
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&i2c5 {
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status = "okay";
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clock-frequency = <400000>;
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pcf_hdmi: pcf8575@26 {
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compatible = "ti,pcf8575", "nxp,pcf8575";
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reg = <0x26>;
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gpio-controller;
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#gpio-cells = <2>;
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/*
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* initial state is used here to keep the mdio interface
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* selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
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* VIN2_S0 driven high otherwise Ethernet stops working
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* VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
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*/
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lines-initial-states = <0x0f2b>;
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p1 {
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/* vin6_sel_s0: high: VIN6, low: audio */
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gpio-hog;
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gpios = <1 GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "vin6_sel_s0";
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};
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};
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};
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&uart1 {
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status = "okay";
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interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
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<&dra7_pmx_core 0x3e0>;
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};
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&elm {
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status = "okay";
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};
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&gpmc {
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/*
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* For the existing IOdelay configuration via U-Boot we don't
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* support NAND on dra72-evm. Keep it disabled. Enabling it
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* requires a different configuration by U-Boot.
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*/
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status = "disabled";
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ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
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nand@0,0 {
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/* To use NAND, DIP switch SW5 must be set like so:
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* SW5.1 (NAND_SELn) = ON (LOW)
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* SW5.9 (GPMC_WPN) = OFF (HIGH)
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*/
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compatible = "ti,omap2-nand";
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reg = <0 0 4>; /* device IO registers */
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interrupt-parent = <&gpmc>;
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interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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<1 IRQ_TYPE_NONE>; /* termcount */
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rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
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ti,nand-xfer-type = "prefetch-dma";
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ti,nand-ecc-opt = "bch8";
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ti,elm-id = <&elm>;
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nand-bus-width = <16>;
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gpmc,device-width = <2>;
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gpmc,sync-clk-ps = <0>;
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gpmc,cs-on-ns = <0>;
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gpmc,cs-rd-off-ns = <80>;
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gpmc,cs-wr-off-ns = <80>;
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gpmc,adv-on-ns = <0>;
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gpmc,adv-rd-off-ns = <60>;
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gpmc,adv-wr-off-ns = <60>;
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gpmc,we-on-ns = <10>;
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gpmc,we-off-ns = <50>;
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gpmc,oe-on-ns = <4>;
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gpmc,oe-off-ns = <40>;
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gpmc,access-ns = <40>;
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gpmc,wr-access-ns = <80>;
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gpmc,rd-cycle-ns = <80>;
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gpmc,wr-cycle-ns = <80>;
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gpmc,bus-turnaround-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <0>;
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gpmc,clk-activation-ns = <0>;
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gpmc,wr-data-mux-bus-ns = <0>;
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/* MTD partition table */
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/* All SPL-* partitions are sized to minimal length
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* which can be independently programmable. For
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* NAND flash this is equal to size of erase-block */
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "NAND.SPL";
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reg = <0x00000000 0x000020000>;
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};
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partition@1 {
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label = "NAND.SPL.backup1";
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reg = <0x00020000 0x00020000>;
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};
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partition@2 {
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label = "NAND.SPL.backup2";
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reg = <0x00040000 0x00020000>;
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};
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partition@3 {
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label = "NAND.SPL.backup3";
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reg = <0x00060000 0x00020000>;
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};
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partition@4 {
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label = "NAND.u-boot-spl-os";
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reg = <0x00080000 0x00040000>;
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};
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partition@5 {
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label = "NAND.u-boot";
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reg = <0x000c0000 0x00100000>;
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};
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partition@6 {
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label = "NAND.u-boot-env";
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reg = <0x001c0000 0x00020000>;
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};
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partition@7 {
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label = "NAND.u-boot-env.backup1";
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reg = <0x001e0000 0x00020000>;
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};
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partition@8 {
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label = "NAND.kernel";
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reg = <0x00200000 0x00800000>;
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};
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partition@9 {
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label = "NAND.file-system";
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reg = <0x00a00000 0x0f600000>;
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};
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};
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};
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&omap_dwc3_1 {
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extcon = <&extcon_usb1>;
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};
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&omap_dwc3_2 {
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extcon = <&extcon_usb2>;
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};
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&usb1 {
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dr_mode = "otg";
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extcon = <&extcon_usb1>;
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};
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&usb2 {
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dr_mode = "host";
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};
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&mmc1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&mmc1_pins_default>;
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vmmc-supply = <&evm_3v3_sd>;
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bus-width = <4>;
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/*
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* SDCD signal is not being used here - using the fact that GPIO mode
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* is a viable alternative
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*/
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cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
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max-frequency = <192000000>;
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};
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&mmc2 {
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/* SW5-3 in ON position */
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&mmc2_pins_default>;
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bus-width = <8>;
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ti,non-removable;
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max-frequency = <192000000>;
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};
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&mac {
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status = "okay";
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};
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&dcan1 {
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status = "ok";
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pinctrl-names = "default", "sleep", "active";
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pinctrl-0 = <&dcan1_pins_sleep>;
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pinctrl-1 = <&dcan1_pins_sleep>;
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pinctrl-2 = <&dcan1_pins_default>;
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};
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&qspi {
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status = "okay";
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spi-max-frequency = <76800000>;
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m25p80@0 {
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compatible = "s25fl256s1";
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spi-max-frequency = <76800000>;
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reg = <0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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#address-cells = <1>;
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#size-cells = <1>;
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/* MTD partition table.
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* The ROM checks the first four physical blocks
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* for a valid file to boot and the flash here is
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* 64KiB block size.
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*/
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partition@0 {
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label = "QSPI.SPL";
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reg = <0x00000000 0x000010000>;
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};
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partition@1 {
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label = "QSPI.SPL.backup1";
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reg = <0x00010000 0x00010000>;
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};
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partition@2 {
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label = "QSPI.SPL.backup2";
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reg = <0x00020000 0x00010000>;
|
|
};
|
|
partition@3 {
|
|
label = "QSPI.SPL.backup3";
|
|
reg = <0x00030000 0x00010000>;
|
|
};
|
|
partition@4 {
|
|
label = "QSPI.u-boot";
|
|
reg = <0x00040000 0x00100000>;
|
|
};
|
|
partition@5 {
|
|
label = "QSPI.u-boot-spl-os";
|
|
reg = <0x00140000 0x00080000>;
|
|
};
|
|
partition@6 {
|
|
label = "QSPI.u-boot-env";
|
|
reg = <0x001c0000 0x00010000>;
|
|
};
|
|
partition@7 {
|
|
label = "QSPI.u-boot-env.backup1";
|
|
reg = <0x001d0000 0x0010000>;
|
|
};
|
|
partition@8 {
|
|
label = "QSPI.kernel";
|
|
reg = <0x001e0000 0x0800000>;
|
|
};
|
|
partition@9 {
|
|
label = "QSPI.file-system";
|
|
reg = <0x009e0000 0x01620000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&dss {
|
|
status = "ok";
|
|
};
|
|
|
|
&hdmi {
|
|
status = "ok";
|
|
|
|
port {
|
|
hdmi_out: endpoint {
|
|
remote-endpoint = <&tpd12s015_in>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&atl {
|
|
assigned-clocks = <&abe_dpll_sys_clk_mux>,
|
|
<&atl_gfclk_mux>,
|
|
<&dpll_abe_ck>,
|
|
<&dpll_abe_m2x2_ck>,
|
|
<&atl_clkin2_ck>;
|
|
assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
|
|
assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
|
|
|
|
status = "okay";
|
|
|
|
atl2 {
|
|
bws = <DRA7_ATL_WS_MCASP2_FSX>;
|
|
aws = <DRA7_ATL_WS_MCASP3_FSX>;
|
|
};
|
|
};
|
|
|
|
&mcasp3 {
|
|
#sound-dai-cells = <0>;
|
|
|
|
assigned-clocks = <&mcasp3_ahclkx_mux>;
|
|
assigned-clock-parents = <&atl_clkin2_ck>;
|
|
|
|
status = "okay";
|
|
|
|
op-mode = <0>; /* MCASP_IIS_MODE */
|
|
tdm-slots = <2>;
|
|
/* 4 serializer */
|
|
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
|
|
1 2 0 0
|
|
>;
|
|
tx-num-evt = <32>;
|
|
rx-num-evt = <32>;
|
|
};
|
|
|
|
&mailbox5 {
|
|
status = "okay";
|
|
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
|
|
status = "okay";
|
|
};
|
|
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
&mailbox6 {
|
|
status = "okay";
|
|
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
&pcie1_rc {
|
|
status = "okay";
|
|
};
|