3b93fc0f2a
On Exynos5422 and Exynos5800 we support 12 cpufreq steps (200-1300 MHz) for LITTLE and 18 steps for big core (200-1700 MHz). Add respective cooling cells. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
126 lines
3.5 KiB
Plaintext
126 lines
3.5 KiB
Plaintext
/*
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* SAMSUNG EXYNOS5422 SoC cpu device tree source
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*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* This file provides desired ordering for Exynos5422: CPU[0123] being the A7.
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*
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* The Exynos5420, 5422 and 5800 actually share the same CPU configuration
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* but particular boards choose different booting order.
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*
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* Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
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* booting cluster (big or LITTLE) is chosen by IROM code by reading
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* the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
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* from the LITTLE: Cortex-A7.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x100>;
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clocks = <&clock CLK_KFC_CLK>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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operating-points-v2 = <&cluster_a7_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <11>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu1: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x101>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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operating-points-v2 = <&cluster_a7_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <11>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu2: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x102>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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operating-points-v2 = <&cluster_a7_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <11>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu3: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x103>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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operating-points-v2 = <&cluster_a7_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <11>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu4: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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clocks = <&clock CLK_ARM_CLK>;
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reg = <0x0>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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operating-points-v2 = <&cluster_a15_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <15>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu5: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x1>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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operating-points-v2 = <&cluster_a15_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <15>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu6: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x2>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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operating-points-v2 = <&cluster_a15_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <15>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu7: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x3>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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operating-points-v2 = <&cluster_a15_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <15>;
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#cooling-cells = <2>; /* min followed by max */
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};
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};
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};
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