964971c8a3
This adds the cpus node to the Integrator/AP device tree so that we have a proper placeholder to put in the DT-defined operating points for the generic DT/OPP cpufreq driver, along with the proper operating points. The old Integrator cpufreq driver would resolve the max frequency to 71MHz, and the min frequency to 12 MHz, but the clock driver can actually handle any frequency inbetween so I picked a few select frequencies as OPPs. The cpufreq framework doesn't seem to deal with sliding frequency scales, only fixed points so 7 OPPs is better than 2 atleast. We define a CPU node since this is required for cpufreq-dt, however we do not define any compatible string for the CPU since this architecture has pluggable CPU modules and we do not know which one will be used. If necessary, the CPU compatible can be filled in by the boot loader, but for just cpufreq-dt it is not required. Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Russell King <linux@armlinux.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
238 lines
6.1 KiB
Plaintext
238 lines
6.1 KiB
Plaintext
/*
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* Device Tree for the ARM Integrator/AP platform
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*/
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/dts-v1/;
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/include/ "integrator.dtsi"
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/ {
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model = "ARM Integrator/AP";
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compatible = "arm,integrator-ap";
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dma-ranges = <0x80000000 0x0 0x80000000>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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/*
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* Since the board has pluggable CPU modules, we
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* cannot define a proper compatible here. Let the
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* boot loader fill in the apropriate compatible
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* string if necessary.
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*/
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/* compatible = "arm,arm926ej-s"; */
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reg = <0>;
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/*
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* The documentation in ARM DUI 0138E page 3-12 states
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* that the maximum frequency for this clock is 200 MHz
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* but painful trial-and-error has proved to me that it
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* is actually just hanging the system above 71 MHz.
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* Sad but true.
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*/
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/* kHz uV */
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operating-points = <71000 0
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66000 0
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60000 0
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48000 0
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36000 0
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24000 0
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12000 0>;
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clocks = <&cmosc>;
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clock-names = "cpu";
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clock-latency = <1000000>; /* 1 ms */
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};
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};
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aliases {
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arm,timer-primary = &timer2;
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arm,timer-secondary = &timer1;
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};
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chosen {
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bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
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};
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/* 24 MHz chrystal on the Integrator/AP development board */
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xtal24mhz: xtal24mhz@24M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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pclk: pclk@0 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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/* The UART clock is 14.74 MHz divided by an ICS525 */
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uartclk: uartclk@14.74M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <14745600>;
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clocks = <&xtal24mhz>;
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};
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core-module@10000000 {
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/* 24 MHz chrystal on the core module */
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cm24mhz: cm24mhz@24M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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/* Oscillator on the core module, clocks the CPU core */
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cmosc: cmosc@24M {
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compatible = "arm,syscon-icst525-integratorap-cm";
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#clock-cells = <0>;
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lock-offset = <0x14>;
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vco-offset = <0x08>;
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clocks = <&cm24mhz>;
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};
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/* Auxilary oscillator on the core module, 32.369MHz at boot */
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auxosc: auxosc@24M {
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compatible = "arm,syscon-icst525";
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#clock-cells = <0>;
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lock-offset = <0x14>;
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vco-offset = <0x1c>;
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clocks = <&cm24mhz>;
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};
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};
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syscon {
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compatible = "arm,integrator-ap-syscon", "syscon";
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reg = <0x11000000 0x100>;
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interrupt-parent = <&pic>;
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/* These are the logical module IRQs */
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interrupts = <9>, <10>, <11>, <12>;
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/*
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* SYSCLK clocks PCIv3 bridge, system controller and the
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* logic modules.
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*/
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sysclk: apsys@24M {
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compatible = "arm,syscon-icst525-integratorap-sys";
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#clock-cells = <0>;
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lock-offset = <0x1c>;
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vco-offset = <0x04>;
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clocks = <&xtal24mhz>;
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};
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/* One-bit control for the PCI bus clock (33 or 25 MHz) */
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pciclk: pciclk@24M {
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compatible = "arm,syscon-icst525-integratorap-pci";
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#clock-cells = <0>;
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lock-offset = <0x1c>;
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vco-offset = <0x04>;
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clocks = <&xtal24mhz>;
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};
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};
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timer0: timer@13000000 {
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compatible = "arm,integrator-timer";
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clocks = <&xtal24mhz>;
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};
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timer1: timer@13000100 {
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compatible = "arm,integrator-timer";
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clocks = <&xtal24mhz>;
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};
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timer2: timer@13000200 {
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compatible = "arm,integrator-timer";
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clocks = <&xtal24mhz>;
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};
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pic: pic@14000000 {
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valid-mask = <0x003fffff>;
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};
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pci: pciv3@62000000 {
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compatible = "v3,v360epc-pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0x62000000 0x10000>;
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interrupt-parent = <&pic>;
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interrupts = <17>; /* Bus error IRQ */
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ranges = <0x00000000 0 0x61000000 /* config space */
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0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */
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0x01000000 0 0x0 /* I/O space */
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0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */
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0x02000000 0 0x00000000 /* non-prefectable memory */
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0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */
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0x42000000 0 0x10000000 /* prefetchable memory */
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0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */
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interrupt-map-mask = <0xf800 0 0 0x7>;
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interrupt-map = <
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/* IDSEL 9 */
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0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
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0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
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0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
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0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
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/* IDSEL 10 */
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0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
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0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
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0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
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0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
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/* IDSEL 11 */
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0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
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0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
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0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
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0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
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/* IDSEL 12 */
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0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
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0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
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0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
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0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
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>;
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};
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fpga {
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/*
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* The Integator/AP predates the idea to have magic numbers
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* identifying the PrimeCell in hardware, thus we have to
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* supply these from the device tree.
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*/
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rtc: rtc@15000000 {
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compatible = "arm,pl030", "arm,primecell";
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arm,primecell-periphid = <0x00041030>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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uart0: uart@16000000 {
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compatible = "arm,pl010", "arm,primecell";
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arm,primecell-periphid = <0x00041010>;
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clocks = <&uartclk>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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uart1: uart@17000000 {
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compatible = "arm,pl010", "arm,primecell";
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arm,primecell-periphid = <0x00041010>;
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clocks = <&uartclk>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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kmi0: kmi@18000000 {
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compatible = "arm,pl050", "arm,primecell";
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arm,primecell-periphid = <0x00041050>;
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clocks = <&xtal24mhz>, <&pclk>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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kmi1: kmi@19000000 {
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compatible = "arm,pl050", "arm,primecell";
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arm,primecell-periphid = <0x00041050>;
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clocks = <&xtal24mhz>, <&pclk>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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};
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};
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