fef5c646db
The PHYs embedded in the switch direct there interrupts through the switch interrupt controllers. Now that devel C has its switch interrupts connected to the SoC, the PHY interrupts can be used by phylib. Explicitly include MDIO nodes in the switch device tree nodes, and link the PHY interrupts back to the switch interrupt controller. Also, link the ports to the PHYs on the MDIO bus. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
494 lines
9.9 KiB
Plaintext
494 lines
9.9 KiB
Plaintext
/*
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* Copyright (C) 2015, 2016 Zodiac Inflight Innovations
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*
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* Based on an original 'vf610-twr.dts' which is Copyright 2015,
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* Freescale Semiconductor, Inc.
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include "vf610-zii-dev.dtsi"
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/ {
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model = "ZII VF610 Development Board, Rev C";
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compatible = "zii,vf610dev-c", "zii,vf610dev", "fsl,vf610";
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mdio-mux {
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compatible = "mdio-mux-gpio";
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pinctrl-0 = <&pinctrl_mdio_mux>;
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pinctrl-names = "default";
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gpios = <&gpio0 8 GPIO_ACTIVE_HIGH
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&gpio0 9 GPIO_ACTIVE_HIGH
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&gpio0 25 GPIO_ACTIVE_HIGH>;
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mdio-parent-bus = <&mdio1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mdio_mux_1: mdio@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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switch0: switch@0 {
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compatible = "marvell,mv88e6190";
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pinctrl-0 = <&pinctrl_gpio_switch0>;
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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dsa,member = <0 0>;
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eeprom-length = <512>;
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interrupt-parent = <&gpio0>;
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interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "cpu";
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ethernet = <&fec1>;
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fixed-link {
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speed = <100>;
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full-duplex;
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};
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};
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port@1 {
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reg = <1>;
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label = "lan1";
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phy-handle = <&switch0phy1>;
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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phy-handle = <&switch0phy2>;
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};
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port@3 {
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reg = <3>;
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label = "lan3";
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phy-handle = <&switch0phy3>;
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};
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port@4 {
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reg = <4>;
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label = "lan4";
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phy-handle = <&switch0phy4>;
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};
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switch0port10: port@10 {
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reg = <10>;
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label = "dsa";
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phy-mode = "xgmii";
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link = <&switch1port10>;
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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switch0phy1: switch0phy@1 {
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reg = <1>;
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interrupt-parent = <&switch0>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
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};
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switch0phy2: switch0phy@2 {
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reg = <2>;
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interrupt-parent = <&switch0>;
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interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
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};
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switch0phy3: switch0phy@3 {
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reg = <3>;
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interrupt-parent = <&switch0>;
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interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
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};
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switch0phy4: switch0phy@4 {
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reg = <4>;
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interrupt-parent = <&switch0>;
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interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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};
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};
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mdio_mux_2: mdio@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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switch1: switch@0 {
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compatible = "marvell,mv88e6190";
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pinctrl-0 = <&pinctrl_gpio_switch1>;
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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dsa,member = <0 1>;
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eeprom-length = <512>;
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interrupt-parent = <&gpio0>;
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interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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label = "lan5";
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phy-handle = <&switch1phy1>;
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};
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port@2 {
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reg = <2>;
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label = "lan6";
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phy-handle = <&switch1phy2>;
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};
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port@3 {
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reg = <3>;
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label = "lan7";
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phy-handle = <&switch1phy3>;
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};
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port@4 {
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reg = <4>;
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label = "lan8";
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phy-handle = <&switch1phy4>;
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};
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switch1port10: port@10 {
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reg = <10>;
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label = "dsa";
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phy-mode = "xgmii";
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link = <&switch0port10>;
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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switch1phy1: switch1phy@1 {
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reg = <1>;
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interrupt-parent = <&switch1>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
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};
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switch1phy2: switch1phy@2 {
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reg = <2>;
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interrupt-parent = <&switch1>;
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interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
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};
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switch1phy3: switch1phy@3 {
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reg = <3>;
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interrupt-parent = <&switch1>;
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interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
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};
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switch1phy4: switch1phy@4 {
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reg = <4>;
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interrupt-parent = <&switch1>;
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interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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};
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};
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mdio_mux_4: mdio@4 {
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reg = <4>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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&dspi0 {
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bus-num = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_dspi0>;
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status = "okay";
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spi-num-chipselects = <2>;
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m25p128@0 {
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compatible = "m25p128", "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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spi-max-frequency = <1000000>;
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};
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atzb-rf-233@1 {
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compatible = "atmel,at86rf233";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctr_atzb_rf_233>;
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spi-max-frequency = <7500000>;
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reg = <1>;
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interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gpio3>;
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xtal-trim = /bits/ 8 <0x06>;
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sleep-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
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reset-gpio = <&gpio6 10 GPIO_ACTIVE_HIGH>;
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fsl,spi-cs-sck-delay = <180>;
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fsl,spi-sck-cs-delay = <250>;
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};
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};
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&i2c0 {
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/*
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* U712
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*
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* Exposed signals:
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* P1 - WE2_CMD
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* P2 - WE2_CLK
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*/
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gpio5: pca9557@18 {
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compatible = "nxp,pca9557";
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reg = <0x18>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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/*
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* U121
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*
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* Exposed signals:
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* I/O0 - ENET_SWR_EN
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* I/O1 - ESW1_RESETn
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* I/O2 - ARINC_RESET
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* I/O3 - DD1_IO_RESET
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* I/O4 - ESW2_RESETn
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* I/O5 - ESW3_RESETn
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* I/O6 - ESW4_RESETn
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* I/O8 - TP909
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* I/O9 - FEM_SEL
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* I/O10 - WIFI_RESETn
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* I/O11 - PHY_RSTn
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* I/O12 - OPT1_SD
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* I/O13 - OPT2_SD
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* I/O14 - OPT1_TX_DIS
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* I/O15 - OPT2_TX_DIS
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*/
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gpio6: sx1503@20 {
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compatible = "semtech,sx1503q";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sx1503_20>;
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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reg = <0x20>;
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interrupt-parent = <&gpio0>;
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interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
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gpio-controller;
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interrupt-controller;
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enet_swr_en {
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gpio-hog;
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gpios = <0 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "enet-swr-en";
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};
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};
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/*
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* U715
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*
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* Exposed signals:
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* IO0 - WE1_CLK
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* IO1 - WE1_CMD
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*/
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gpio7: pca9554@22 {
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compatible = "nxp,pca9554";
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reg = <0x22>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&i2c1 {
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at24mac602@00 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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read-only;
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};
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};
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&i2c2 {
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tca9548@70 {
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compatible = "nxp,pca9548";
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pinctrl-0 = <&pinctrl_i2c_mux_reset>;
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x70>;
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reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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sfp2: at24c04@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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};
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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sfp3: at24c04@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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};
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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};
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};
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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status = "okay";
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};
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&gpio0 {
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eth0_intrp {
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gpio-hog;
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gpios = <23 GPIO_ACTIVE_HIGH>;
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input;
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line-name = "sx1503-irq";
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};
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};
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&gpio3 {
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eth0_intrp {
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gpio-hog;
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gpios = <2 GPIO_ACTIVE_HIGH>;
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input;
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line-name = "eth0-intrp";
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};
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};
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&fec0 {
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec0_phy_int>;
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interrupt-parent = <&gpio3>;
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interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
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reg = <0>;
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};
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};
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};
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&iomuxc {
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pinctr_atzb_rf_233: pinctrl-atzb-rf-233 {
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fsl,pins = <
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VF610_PAD_PTB2__GPIO_24 0x31c2
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VF610_PAD_PTE27__GPIO_132 0x33e2
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>;
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};
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pinctrl_sx1503_20: pinctrl-sx1503-20 {
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fsl,pins = <
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VF610_PAD_PTB1__GPIO_23 0x219d
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>;
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};
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pinctrl_uart3: uart3grp {
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fsl,pins = <
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VF610_PAD_PTA20__UART3_TX 0x21a2
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VF610_PAD_PTA21__UART3_RX 0x21a1
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>;
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};
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pinctrl_mdio_mux: pinctrl-mdio-mux {
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fsl,pins = <
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VF610_PAD_PTA18__GPIO_8 0x31c2
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VF610_PAD_PTA19__GPIO_9 0x31c2
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VF610_PAD_PTB3__GPIO_25 0x31c2
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>;
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};
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pinctrl_fec0_phy_int: pinctrl-fec0-phy-int {
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fsl,pins = <
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VF610_PAD_PTB28__GPIO_98 0x219d
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>;
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};
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};
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