![Stephen Boyd](/assets/img/avatar_default.png)
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers in this driver, allowing us to move closer to a clear split of consumer and provider clk APIs. Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Tested-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
531 lines
13 KiB
C
531 lines
13 KiB
C
/*
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* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clk/at91_pmc.h>
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#include <linux/of.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include "pmc.h"
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#define PLL_STATUS_MASK(id) (1 << (1 + (id)))
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#define PLL_REG(id) (AT91_CKGR_PLLAR + ((id) * 4))
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#define PLL_DIV_MASK 0xff
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#define PLL_DIV_MAX PLL_DIV_MASK
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#define PLL_DIV(reg) ((reg) & PLL_DIV_MASK)
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#define PLL_MUL(reg, layout) (((reg) >> (layout)->mul_shift) & \
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(layout)->mul_mask)
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#define PLL_MUL_MIN 2
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#define PLL_MUL_MASK(layout) ((layout)->mul_mask)
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#define PLL_MUL_MAX(layout) (PLL_MUL_MASK(layout) + 1)
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#define PLL_ICPR_SHIFT(id) ((id) * 16)
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#define PLL_ICPR_MASK(id) (0xffff << PLL_ICPR_SHIFT(id))
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#define PLL_MAX_COUNT 0x3f
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#define PLL_COUNT_SHIFT 8
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#define PLL_OUT_SHIFT 14
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#define PLL_MAX_ID 1
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struct clk_pll_characteristics {
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struct clk_range input;
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int num_output;
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struct clk_range *output;
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u16 *icpll;
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u8 *out;
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};
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struct clk_pll_layout {
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u32 pllr_mask;
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u16 mul_mask;
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u8 mul_shift;
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};
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#define to_clk_pll(hw) container_of(hw, struct clk_pll, hw)
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struct clk_pll {
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struct clk_hw hw;
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struct regmap *regmap;
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u8 id;
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u8 div;
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u8 range;
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u16 mul;
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const struct clk_pll_layout *layout;
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const struct clk_pll_characteristics *characteristics;
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};
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static inline bool clk_pll_ready(struct regmap *regmap, int id)
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{
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unsigned int status;
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regmap_read(regmap, AT91_PMC_SR, &status);
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return status & PLL_STATUS_MASK(id) ? 1 : 0;
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}
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static int clk_pll_prepare(struct clk_hw *hw)
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{
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struct clk_pll *pll = to_clk_pll(hw);
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struct regmap *regmap = pll->regmap;
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const struct clk_pll_layout *layout = pll->layout;
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const struct clk_pll_characteristics *characteristics =
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pll->characteristics;
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u8 id = pll->id;
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u32 mask = PLL_STATUS_MASK(id);
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int offset = PLL_REG(id);
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u8 out = 0;
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unsigned int pllr;
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unsigned int status;
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u8 div;
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u16 mul;
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regmap_read(regmap, offset, &pllr);
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div = PLL_DIV(pllr);
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mul = PLL_MUL(pllr, layout);
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regmap_read(regmap, AT91_PMC_SR, &status);
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if ((status & mask) &&
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(div == pll->div && mul == pll->mul))
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return 0;
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if (characteristics->out)
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out = characteristics->out[pll->range];
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if (characteristics->icpll)
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regmap_update_bits(regmap, AT91_PMC_PLLICPR, PLL_ICPR_MASK(id),
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characteristics->icpll[pll->range] << PLL_ICPR_SHIFT(id));
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regmap_update_bits(regmap, offset, layout->pllr_mask,
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pll->div | (PLL_MAX_COUNT << PLL_COUNT_SHIFT) |
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(out << PLL_OUT_SHIFT) |
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((pll->mul & layout->mul_mask) << layout->mul_shift));
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while (!clk_pll_ready(regmap, pll->id))
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cpu_relax();
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return 0;
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}
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static int clk_pll_is_prepared(struct clk_hw *hw)
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{
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struct clk_pll *pll = to_clk_pll(hw);
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return clk_pll_ready(pll->regmap, pll->id);
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}
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static void clk_pll_unprepare(struct clk_hw *hw)
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{
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struct clk_pll *pll = to_clk_pll(hw);
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unsigned int mask = pll->layout->pllr_mask;
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regmap_update_bits(pll->regmap, PLL_REG(pll->id), mask, ~mask);
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}
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static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_pll *pll = to_clk_pll(hw);
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unsigned int pllr;
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u16 mul;
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u8 div;
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regmap_read(pll->regmap, PLL_REG(pll->id), &pllr);
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div = PLL_DIV(pllr);
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mul = PLL_MUL(pllr, pll->layout);
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if (!div || !mul)
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return 0;
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return (parent_rate / div) * (mul + 1);
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}
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static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
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unsigned long parent_rate,
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u32 *div, u32 *mul,
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u32 *index) {
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const struct clk_pll_layout *layout = pll->layout;
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const struct clk_pll_characteristics *characteristics =
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pll->characteristics;
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unsigned long bestremainder = ULONG_MAX;
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unsigned long maxdiv, mindiv, tmpdiv;
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long bestrate = -ERANGE;
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unsigned long bestdiv;
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unsigned long bestmul;
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int i = 0;
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/* Check if parent_rate is a valid input rate */
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if (parent_rate < characteristics->input.min)
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return -ERANGE;
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/*
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* Calculate minimum divider based on the minimum multiplier, the
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* parent_rate and the requested rate.
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* Should always be 2 according to the input and output characteristics
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* of the PLL blocks.
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*/
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mindiv = (parent_rate * PLL_MUL_MIN) / rate;
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if (!mindiv)
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mindiv = 1;
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if (parent_rate > characteristics->input.max) {
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tmpdiv = DIV_ROUND_UP(parent_rate, characteristics->input.max);
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if (tmpdiv > PLL_DIV_MAX)
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return -ERANGE;
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if (tmpdiv > mindiv)
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mindiv = tmpdiv;
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}
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/*
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* Calculate the maximum divider which is limited by PLL register
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* layout (limited by the MUL or DIV field size).
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*/
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maxdiv = DIV_ROUND_UP(parent_rate * PLL_MUL_MAX(layout), rate);
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if (maxdiv > PLL_DIV_MAX)
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maxdiv = PLL_DIV_MAX;
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/*
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* Iterate over the acceptable divider values to find the best
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* divider/multiplier pair (the one that generates the closest
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* rate to the requested one).
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*/
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for (tmpdiv = mindiv; tmpdiv <= maxdiv; tmpdiv++) {
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unsigned long remainder;
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unsigned long tmprate;
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unsigned long tmpmul;
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/*
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* Calculate the multiplier associated with the current
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* divider that provide the closest rate to the requested one.
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*/
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tmpmul = DIV_ROUND_CLOSEST(rate, parent_rate / tmpdiv);
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tmprate = (parent_rate / tmpdiv) * tmpmul;
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if (tmprate > rate)
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remainder = tmprate - rate;
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else
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remainder = rate - tmprate;
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/*
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* Compare the remainder with the best remainder found until
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* now and elect a new best multiplier/divider pair if the
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* current remainder is smaller than the best one.
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*/
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if (remainder < bestremainder) {
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bestremainder = remainder;
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bestdiv = tmpdiv;
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bestmul = tmpmul;
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bestrate = tmprate;
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}
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/*
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* We've found a perfect match!
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* Stop searching now and use this multiplier/divider pair.
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*/
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if (!remainder)
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break;
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}
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/* We haven't found any multiplier/divider pair => return -ERANGE */
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if (bestrate < 0)
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return bestrate;
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/* Check if bestrate is a valid output rate */
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for (i = 0; i < characteristics->num_output; i++) {
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if (bestrate >= characteristics->output[i].min &&
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bestrate <= characteristics->output[i].max)
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break;
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}
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if (i >= characteristics->num_output)
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return -ERANGE;
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if (div)
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*div = bestdiv;
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if (mul)
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*mul = bestmul - 1;
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if (index)
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*index = i;
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return bestrate;
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}
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static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct clk_pll *pll = to_clk_pll(hw);
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return clk_pll_get_best_div_mul(pll, rate, *parent_rate,
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NULL, NULL, NULL);
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}
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static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_pll *pll = to_clk_pll(hw);
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long ret;
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u32 div;
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u32 mul;
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u32 index;
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ret = clk_pll_get_best_div_mul(pll, rate, parent_rate,
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&div, &mul, &index);
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if (ret < 0)
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return ret;
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pll->range = index;
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pll->div = div;
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pll->mul = mul;
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return 0;
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}
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static const struct clk_ops pll_ops = {
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.prepare = clk_pll_prepare,
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.unprepare = clk_pll_unprepare,
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.is_prepared = clk_pll_is_prepared,
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.recalc_rate = clk_pll_recalc_rate,
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.round_rate = clk_pll_round_rate,
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.set_rate = clk_pll_set_rate,
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};
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static struct clk_hw * __init
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at91_clk_register_pll(struct regmap *regmap, const char *name,
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const char *parent_name, u8 id,
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const struct clk_pll_layout *layout,
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const struct clk_pll_characteristics *characteristics)
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{
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struct clk_pll *pll;
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struct clk_hw *hw;
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struct clk_init_data init;
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int offset = PLL_REG(id);
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unsigned int pllr;
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int ret;
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if (id > PLL_MAX_ID)
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return ERR_PTR(-EINVAL);
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &pll_ops;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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init.flags = CLK_SET_RATE_GATE;
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pll->id = id;
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pll->hw.init = &init;
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pll->layout = layout;
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pll->characteristics = characteristics;
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pll->regmap = regmap;
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regmap_read(regmap, offset, &pllr);
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pll->div = PLL_DIV(pllr);
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pll->mul = PLL_MUL(pllr, layout);
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hw = &pll->hw;
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ret = clk_hw_register(NULL, &pll->hw);
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if (ret) {
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kfree(pll);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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static const struct clk_pll_layout at91rm9200_pll_layout = {
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.pllr_mask = 0x7FFFFFF,
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.mul_shift = 16,
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.mul_mask = 0x7FF,
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};
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static const struct clk_pll_layout at91sam9g45_pll_layout = {
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.pllr_mask = 0xFFFFFF,
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.mul_shift = 16,
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.mul_mask = 0xFF,
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};
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static const struct clk_pll_layout at91sam9g20_pllb_layout = {
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.pllr_mask = 0x3FFFFF,
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.mul_shift = 16,
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.mul_mask = 0x3F,
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};
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static const struct clk_pll_layout sama5d3_pll_layout = {
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.pllr_mask = 0x1FFFFFF,
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.mul_shift = 18,
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.mul_mask = 0x7F,
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};
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static struct clk_pll_characteristics * __init
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of_at91_clk_pll_get_characteristics(struct device_node *np)
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{
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int i;
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int offset;
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u32 tmp;
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int num_output;
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u32 num_cells;
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struct clk_range input;
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struct clk_range *output;
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u8 *out = NULL;
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u16 *icpll = NULL;
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struct clk_pll_characteristics *characteristics;
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if (of_at91_get_clk_range(np, "atmel,clk-input-range", &input))
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return NULL;
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if (of_property_read_u32(np, "#atmel,pll-clk-output-range-cells",
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&num_cells))
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return NULL;
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if (num_cells < 2 || num_cells > 4)
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return NULL;
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if (!of_get_property(np, "atmel,pll-clk-output-ranges", &tmp))
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return NULL;
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num_output = tmp / (sizeof(u32) * num_cells);
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characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
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if (!characteristics)
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return NULL;
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output = kzalloc(sizeof(*output) * num_output, GFP_KERNEL);
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if (!output)
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goto out_free_characteristics;
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if (num_cells > 2) {
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out = kzalloc(sizeof(*out) * num_output, GFP_KERNEL);
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if (!out)
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goto out_free_output;
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}
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if (num_cells > 3) {
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icpll = kzalloc(sizeof(*icpll) * num_output, GFP_KERNEL);
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if (!icpll)
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goto out_free_output;
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}
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for (i = 0; i < num_output; i++) {
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offset = i * num_cells;
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if (of_property_read_u32_index(np,
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"atmel,pll-clk-output-ranges",
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offset, &tmp))
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goto out_free_output;
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output[i].min = tmp;
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if (of_property_read_u32_index(np,
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"atmel,pll-clk-output-ranges",
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offset + 1, &tmp))
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goto out_free_output;
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output[i].max = tmp;
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if (num_cells == 2)
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continue;
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if (of_property_read_u32_index(np,
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"atmel,pll-clk-output-ranges",
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offset + 2, &tmp))
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goto out_free_output;
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out[i] = tmp;
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if (num_cells == 3)
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continue;
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if (of_property_read_u32_index(np,
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"atmel,pll-clk-output-ranges",
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offset + 3, &tmp))
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goto out_free_output;
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icpll[i] = tmp;
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}
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characteristics->input = input;
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characteristics->num_output = num_output;
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characteristics->output = output;
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characteristics->out = out;
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characteristics->icpll = icpll;
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return characteristics;
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out_free_output:
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kfree(icpll);
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kfree(out);
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kfree(output);
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out_free_characteristics:
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kfree(characteristics);
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return NULL;
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}
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|
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static void __init
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of_at91_clk_pll_setup(struct device_node *np,
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const struct clk_pll_layout *layout)
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{
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u32 id;
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struct clk_hw *hw;
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struct regmap *regmap;
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const char *parent_name;
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const char *name = np->name;
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struct clk_pll_characteristics *characteristics;
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if (of_property_read_u32(np, "reg", &id))
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return;
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parent_name = of_clk_get_parent_name(np, 0);
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of_property_read_string(np, "clock-output-names", &name);
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regmap = syscon_node_to_regmap(of_get_parent(np));
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if (IS_ERR(regmap))
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return;
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characteristics = of_at91_clk_pll_get_characteristics(np);
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if (!characteristics)
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return;
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hw = at91_clk_register_pll(regmap, name, parent_name, id, layout,
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characteristics);
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if (IS_ERR(hw))
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goto out_free_characteristics;
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of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
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return;
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out_free_characteristics:
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kfree(characteristics);
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}
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static void __init of_at91rm9200_clk_pll_setup(struct device_node *np)
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{
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of_at91_clk_pll_setup(np, &at91rm9200_pll_layout);
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}
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CLK_OF_DECLARE(at91rm9200_clk_pll, "atmel,at91rm9200-clk-pll",
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of_at91rm9200_clk_pll_setup);
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static void __init of_at91sam9g45_clk_pll_setup(struct device_node *np)
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{
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of_at91_clk_pll_setup(np, &at91sam9g45_pll_layout);
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}
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CLK_OF_DECLARE(at91sam9g45_clk_pll, "atmel,at91sam9g45-clk-pll",
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of_at91sam9g45_clk_pll_setup);
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|
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static void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np)
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{
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of_at91_clk_pll_setup(np, &at91sam9g20_pllb_layout);
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}
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CLK_OF_DECLARE(at91sam9g20_clk_pllb, "atmel,at91sam9g20-clk-pllb",
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|
of_at91sam9g20_clk_pllb_setup);
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|
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static void __init of_sama5d3_clk_pll_setup(struct device_node *np)
|
|
{
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|
of_at91_clk_pll_setup(np, &sama5d3_pll_layout);
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|
}
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CLK_OF_DECLARE(sama5d3_clk_pll, "atmel,sama5d3-clk-pll",
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|
of_sama5d3_clk_pll_setup);
|