6c9da387c8
The CRG(Clock and Reset Generator) block provides clock and reset signals for other modules in hi3519 soc. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
14 lines
406 B
Makefile
14 lines
406 B
Makefile
#
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# Hisilicon Clock specific Makefile
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#
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obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
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obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
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obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
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obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
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obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
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obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o
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obj-$(CONFIG_RESET_HISI) += reset.o
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obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o
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