![Geert Uytterhoeven](/assets/img/avatar_default.png)
Initial support for R-Car M3-W (r8a7796), including basic core clocks, and SCIF2 (console) and INTC-AP (GIC) module clocks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Simon Horman <horms+renesas@verge.net.au>
609 lines
14 KiB
C
609 lines
14 KiB
C
/*
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* Renesas Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2015 Glider bvba
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*
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* Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
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*
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* Copyright (C) 2013 Ideas On Board SPRL
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* Copyright (C) 2015 Renesas Electronics Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/renesas.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_clock.h>
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#include <linux/pm_domain.h>
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#include <linux/slab.h>
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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#include "clk-div6.h"
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#ifdef DEBUG
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#define WARN_DEBUG(x) do { } while (0)
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#else
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#define WARN_DEBUG(x) WARN_ON(x)
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#endif
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/*
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* Module Standby and Software Reset register offets.
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*
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* If the registers exist, these are valid for SH-Mobile, R-Mobile,
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* R-Car Gen 2, and R-Car Gen 3.
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* These are NOT valid for R-Car Gen1 and RZ/A1!
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*/
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/*
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* Module Stop Status Register offsets
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*/
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static const u16 mstpsr[] = {
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0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
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0x9A0, 0x9A4, 0x9A8, 0x9AC,
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};
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#define MSTPSR(i) mstpsr[i]
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/*
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* System Module Stop Control Register offsets
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*/
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static const u16 smstpcr[] = {
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0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
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0x990, 0x994, 0x998, 0x99C,
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};
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#define SMSTPCR(i) smstpcr[i]
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/*
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* Software Reset Register offsets
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*/
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static const u16 srcr[] = {
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0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,
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0x920, 0x924, 0x928, 0x92C,
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};
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#define SRCR(i) srcr[i]
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/* Realtime Module Stop Control Register offsets */
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#define RMSTPCR(i) (smstpcr[i] - 0x20)
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/* Modem Module Stop Control Register offsets (r8a73a4) */
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#define MMSTPCR(i) (smstpcr[i] + 0x20)
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/* Software Reset Clearing Register offsets */
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#define SRSTCLR(i) (0x940 + (i) * 4)
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/**
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* Clock Pulse Generator / Module Standby and Software Reset Private Data
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*
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* @dev: CPG/MSSR device
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* @base: CPG/MSSR register block base address
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* @mstp_lock: protects writes to SMSTPCR
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* @clks: Array containing all Core and Module Clocks
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* @num_core_clks: Number of Core Clocks in clks[]
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* @num_mod_clks: Number of Module Clocks in clks[]
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* @last_dt_core_clk: ID of the last Core Clock exported to DT
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*/
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struct cpg_mssr_priv {
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struct device *dev;
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void __iomem *base;
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spinlock_t mstp_lock;
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struct clk **clks;
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unsigned int num_core_clks;
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unsigned int num_mod_clks;
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unsigned int last_dt_core_clk;
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};
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/**
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* struct mstp_clock - MSTP gating clock
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* @hw: handle between common and hardware-specific interfaces
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* @index: MSTP clock number
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* @priv: CPG/MSSR private data
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*/
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struct mstp_clock {
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struct clk_hw hw;
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u32 index;
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struct cpg_mssr_priv *priv;
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};
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#define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
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static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
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{
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struct mstp_clock *clock = to_mstp_clock(hw);
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struct cpg_mssr_priv *priv = clock->priv;
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unsigned int reg = clock->index / 32;
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unsigned int bit = clock->index % 32;
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struct device *dev = priv->dev;
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u32 bitmask = BIT(bit);
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unsigned long flags;
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unsigned int i;
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u32 value;
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dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk,
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enable ? "ON" : "OFF");
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spin_lock_irqsave(&priv->mstp_lock, flags);
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value = clk_readl(priv->base + SMSTPCR(reg));
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if (enable)
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value &= ~bitmask;
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else
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value |= bitmask;
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clk_writel(value, priv->base + SMSTPCR(reg));
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spin_unlock_irqrestore(&priv->mstp_lock, flags);
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if (!enable)
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return 0;
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for (i = 1000; i > 0; --i) {
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if (!(clk_readl(priv->base + MSTPSR(reg)) &
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bitmask))
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break;
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cpu_relax();
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}
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if (!i) {
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dev_err(dev, "Failed to enable SMSTP %p[%d]\n",
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priv->base + SMSTPCR(reg), bit);
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int cpg_mstp_clock_enable(struct clk_hw *hw)
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{
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return cpg_mstp_clock_endisable(hw, true);
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}
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static void cpg_mstp_clock_disable(struct clk_hw *hw)
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{
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cpg_mstp_clock_endisable(hw, false);
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}
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static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
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{
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struct mstp_clock *clock = to_mstp_clock(hw);
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struct cpg_mssr_priv *priv = clock->priv;
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u32 value;
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value = clk_readl(priv->base + MSTPSR(clock->index / 32));
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return !(value & BIT(clock->index % 32));
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}
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static const struct clk_ops cpg_mstp_clock_ops = {
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.enable = cpg_mstp_clock_enable,
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.disable = cpg_mstp_clock_disable,
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.is_enabled = cpg_mstp_clock_is_enabled,
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};
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static
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struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
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void *data)
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{
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unsigned int clkidx = clkspec->args[1];
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struct cpg_mssr_priv *priv = data;
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struct device *dev = priv->dev;
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unsigned int idx;
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const char *type;
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struct clk *clk;
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switch (clkspec->args[0]) {
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case CPG_CORE:
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type = "core";
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if (clkidx > priv->last_dt_core_clk) {
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dev_err(dev, "Invalid %s clock index %u\n", type,
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clkidx);
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return ERR_PTR(-EINVAL);
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}
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clk = priv->clks[clkidx];
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break;
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case CPG_MOD:
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type = "module";
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idx = MOD_CLK_PACK(clkidx);
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if (clkidx % 100 > 31 || idx >= priv->num_mod_clks) {
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dev_err(dev, "Invalid %s clock index %u\n", type,
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clkidx);
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return ERR_PTR(-EINVAL);
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}
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clk = priv->clks[priv->num_core_clks + idx];
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break;
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default:
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dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
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return ERR_PTR(-EINVAL);
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}
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if (IS_ERR(clk))
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dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
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PTR_ERR(clk));
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else
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dev_dbg(dev, "clock (%u, %u) is %pC at %pCr Hz\n",
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clkspec->args[0], clkspec->args[1], clk, clk);
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return clk;
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}
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static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
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const struct cpg_mssr_info *info,
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struct cpg_mssr_priv *priv)
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{
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struct clk *clk = NULL, *parent;
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struct device *dev = priv->dev;
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unsigned int id = core->id, div = core->div;
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const char *parent_name;
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WARN_DEBUG(id >= priv->num_core_clks);
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WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
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switch (core->type) {
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case CLK_TYPE_IN:
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clk = of_clk_get_by_name(priv->dev->of_node, core->name);
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break;
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case CLK_TYPE_FF:
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case CLK_TYPE_DIV6P1:
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case CLK_TYPE_DIV6_RO:
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WARN_DEBUG(core->parent >= priv->num_core_clks);
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parent = priv->clks[core->parent];
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if (IS_ERR(parent)) {
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clk = parent;
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goto fail;
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}
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parent_name = __clk_get_name(parent);
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if (core->type == CLK_TYPE_DIV6_RO)
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/* Multiply with the DIV6 register value */
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div *= (readl(priv->base + core->offset) & 0x3f) + 1;
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if (core->type == CLK_TYPE_DIV6P1) {
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clk = cpg_div6_register(core->name, 1, &parent_name,
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priv->base + core->offset);
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} else {
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clk = clk_register_fixed_factor(NULL, core->name,
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parent_name, 0,
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core->mult, div);
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}
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break;
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default:
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if (info->cpg_clk_register)
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clk = info->cpg_clk_register(dev, core, info,
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priv->clks, priv->base);
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else
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dev_err(dev, "%s has unsupported core clock type %u\n",
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core->name, core->type);
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break;
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}
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if (IS_ERR_OR_NULL(clk))
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goto fail;
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dev_dbg(dev, "Core clock %pC at %pCr Hz\n", clk, clk);
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priv->clks[id] = clk;
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return;
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fail:
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dev_err(dev, "Failed to register %s clock %s: %ld\n", "core,",
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core->name, PTR_ERR(clk));
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}
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static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
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const struct cpg_mssr_info *info,
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struct cpg_mssr_priv *priv)
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{
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struct mstp_clock *clock = NULL;
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struct device *dev = priv->dev;
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unsigned int id = mod->id;
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struct clk_init_data init;
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struct clk *parent, *clk;
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const char *parent_name;
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unsigned int i;
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WARN_DEBUG(id < priv->num_core_clks);
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WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
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WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
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WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
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parent = priv->clks[mod->parent];
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if (IS_ERR(parent)) {
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clk = parent;
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goto fail;
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}
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clock = kzalloc(sizeof(*clock), GFP_KERNEL);
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if (!clock) {
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clk = ERR_PTR(-ENOMEM);
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goto fail;
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}
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init.name = mod->name;
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init.ops = &cpg_mstp_clock_ops;
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init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
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for (i = 0; i < info->num_crit_mod_clks; i++)
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if (id == info->crit_mod_clks[i]) {
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#ifdef CLK_ENABLE_HAND_OFF
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dev_dbg(dev, "MSTP %s setting CLK_ENABLE_HAND_OFF\n",
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mod->name);
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init.flags |= CLK_ENABLE_HAND_OFF;
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break;
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#else
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dev_dbg(dev, "Ignoring MSTP %s to prevent disabling\n",
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mod->name);
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kfree(clock);
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return;
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#endif
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}
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parent_name = __clk_get_name(parent);
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init.parent_names = &parent_name;
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init.num_parents = 1;
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clock->index = id - priv->num_core_clks;
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clock->priv = priv;
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clock->hw.init = &init;
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clk = clk_register(NULL, &clock->hw);
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if (IS_ERR(clk))
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goto fail;
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dev_dbg(dev, "Module clock %pC at %pCr Hz\n", clk, clk);
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priv->clks[id] = clk;
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return;
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fail:
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dev_err(dev, "Failed to register %s clock %s: %ld\n", "module,",
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mod->name, PTR_ERR(clk));
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kfree(clock);
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}
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struct cpg_mssr_clk_domain {
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struct generic_pm_domain genpd;
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struct device_node *np;
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unsigned int num_core_pm_clks;
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unsigned int core_pm_clks[0];
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};
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static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain;
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static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec,
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struct cpg_mssr_clk_domain *pd)
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{
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unsigned int i;
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if (clkspec->np != pd->np || clkspec->args_count != 2)
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return false;
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switch (clkspec->args[0]) {
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case CPG_CORE:
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for (i = 0; i < pd->num_core_pm_clks; i++)
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if (clkspec->args[1] == pd->core_pm_clks[i])
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return true;
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return false;
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case CPG_MOD:
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return true;
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default:
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return false;
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}
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}
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int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev)
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{
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struct cpg_mssr_clk_domain *pd = cpg_mssr_clk_domain;
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struct device_node *np = dev->of_node;
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struct of_phandle_args clkspec;
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struct clk *clk;
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int i = 0;
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int error;
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if (!pd) {
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dev_dbg(dev, "CPG/MSSR clock domain not yet available\n");
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return -EPROBE_DEFER;
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}
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while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
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&clkspec)) {
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if (cpg_mssr_is_pm_clk(&clkspec, pd))
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goto found;
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of_node_put(clkspec.np);
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i++;
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}
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return 0;
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found:
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clk = of_clk_get_from_provider(&clkspec);
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of_node_put(clkspec.np);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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error = pm_clk_create(dev);
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if (error) {
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dev_err(dev, "pm_clk_create failed %d\n", error);
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goto fail_put;
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}
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error = pm_clk_add_clk(dev, clk);
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if (error) {
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dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error);
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goto fail_destroy;
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}
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return 0;
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fail_destroy:
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pm_clk_destroy(dev);
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fail_put:
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clk_put(clk);
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return error;
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}
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void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev)
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{
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if (!list_empty(&dev->power.subsys_data->clock_list))
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pm_clk_destroy(dev);
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}
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static int __init cpg_mssr_add_clk_domain(struct device *dev,
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const unsigned int *core_pm_clks,
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unsigned int num_core_pm_clks)
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{
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struct device_node *np = dev->of_node;
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struct generic_pm_domain *genpd;
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struct cpg_mssr_clk_domain *pd;
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size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]);
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pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL);
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if (!pd)
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return -ENOMEM;
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pd->np = np;
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pd->num_core_pm_clks = num_core_pm_clks;
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memcpy(pd->core_pm_clks, core_pm_clks, pm_size);
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genpd = &pd->genpd;
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genpd->name = np->name;
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genpd->flags = GENPD_FLAG_PM_CLK;
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genpd->attach_dev = cpg_mssr_attach_dev;
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genpd->detach_dev = cpg_mssr_detach_dev;
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pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
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cpg_mssr_clk_domain = pd;
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of_genpd_add_provider_simple(np, genpd);
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return 0;
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}
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static const struct of_device_id cpg_mssr_match[] = {
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#ifdef CONFIG_ARCH_R8A7795
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{
|
|
.compatible = "renesas,r8a7795-cpg-mssr",
|
|
.data = &r8a7795_cpg_mssr_info,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARCH_R8A7796
|
|
{
|
|
.compatible = "renesas,r8a7796-cpg-mssr",
|
|
.data = &r8a7796_cpg_mssr_info,
|
|
},
|
|
#endif
|
|
{ /* sentinel */ }
|
|
};
|
|
|
|
static void cpg_mssr_del_clk_provider(void *data)
|
|
{
|
|
of_clk_del_provider(data);
|
|
}
|
|
|
|
static int __init cpg_mssr_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct device_node *np = dev->of_node;
|
|
const struct cpg_mssr_info *info;
|
|
struct cpg_mssr_priv *priv;
|
|
unsigned int nclks, i;
|
|
struct resource *res;
|
|
struct clk **clks;
|
|
int error;
|
|
|
|
info = of_match_node(cpg_mssr_match, np)->data;
|
|
if (info->init) {
|
|
error = info->init(dev);
|
|
if (error)
|
|
return error;
|
|
}
|
|
|
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
priv->dev = dev;
|
|
spin_lock_init(&priv->mstp_lock);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
priv->base = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(priv->base))
|
|
return PTR_ERR(priv->base);
|
|
|
|
nclks = info->num_total_core_clks + info->num_hw_mod_clks;
|
|
clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL);
|
|
if (!clks)
|
|
return -ENOMEM;
|
|
|
|
priv->clks = clks;
|
|
priv->num_core_clks = info->num_total_core_clks;
|
|
priv->num_mod_clks = info->num_hw_mod_clks;
|
|
priv->last_dt_core_clk = info->last_dt_core_clk;
|
|
|
|
for (i = 0; i < nclks; i++)
|
|
clks[i] = ERR_PTR(-ENOENT);
|
|
|
|
for (i = 0; i < info->num_core_clks; i++)
|
|
cpg_mssr_register_core_clk(&info->core_clks[i], info, priv);
|
|
|
|
for (i = 0; i < info->num_mod_clks; i++)
|
|
cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv);
|
|
|
|
error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
|
|
if (error)
|
|
return error;
|
|
|
|
error = devm_add_action_or_reset(dev,
|
|
cpg_mssr_del_clk_provider,
|
|
np);
|
|
if (error)
|
|
return error;
|
|
|
|
error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks,
|
|
info->num_core_pm_clks);
|
|
if (error)
|
|
return error;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver cpg_mssr_driver = {
|
|
.driver = {
|
|
.name = "renesas-cpg-mssr",
|
|
.of_match_table = cpg_mssr_match,
|
|
},
|
|
};
|
|
|
|
static int __init cpg_mssr_init(void)
|
|
{
|
|
return platform_driver_probe(&cpg_mssr_driver, cpg_mssr_probe);
|
|
}
|
|
|
|
subsys_initcall(cpg_mssr_init);
|
|
|
|
MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");
|
|
MODULE_LICENSE("GPL v2");
|