a4f182bf81
Changing the rate of the DDR clock needs special care, as the DDR is of course in use and will react badly if the rate changes under it. Over time different approaches to handle that were used. Past SoCs like the rk3288 and before would store some code in SRAM while the rk3368 used a SCPI variant and let a coprocessor handle that. New rockchip platforms like the rk3399 have a dcf controller to do ddr frequency scaling, and support for this controller will be implemented in the arm-trusted-firmware. This new clock-type should over time handle all these methods for handling DDR rate changes, but right now it will concentrate on the SIP interface used to talk to ARM trusted firmware. The SIP interface counterpart was merged from pull-request #684 [0] into the upstream arm-trusted-firmware codebase. [0] https://github.com/ARM-software/arm-trusted-firmware/pull/684 Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
20 lines
362 B
Makefile
20 lines
362 B
Makefile
#
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# Rockchip Clock specific Makefile
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#
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obj-y += clk-rockchip.o
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obj-y += clk.o
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obj-y += clk-pll.o
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obj-y += clk-cpu.o
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obj-y += clk-inverter.o
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obj-y += clk-mmc-phase.o
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obj-y += clk-ddr.o
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obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
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obj-y += clk-rk3036.o
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obj-y += clk-rk3188.o
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obj-y += clk-rk3228.o
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obj-y += clk-rk3288.o
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obj-y += clk-rk3368.o
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obj-y += clk-rk3399.o
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