![Allan W. Nielsen](/assets/img/avatar_default.png)
Edge-Rate cleanup include the following: - Updated device tree bindings documentation for edge-rate - The edge-rate is now specified as a "slowdown", meaning that it is now being specified as positive values instead of negative (both documentation and implementation wise). - Only explicitly documented values for "vsc8531,vddmac" and "vsc8531,edge-slowdown" are accepted by the device driver. - Deleted include/dt-bindings/net/mscc-phy-vsc8531.h as it was not needed. - Read/validate devicetree settings in probe instead of init Signed-off-by: Allan W. Nielsen <allan.nielsen@microsemi.com> Signed-off-by: Raju Lakkaraju <raju.lakkaraju@microsemi.com> Signed-off-by: David S. Miller <davem@davemloft.net>
455 lines
12 KiB
C
455 lines
12 KiB
C
/*
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* Driver for Microsemi VSC85xx PHYs
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*
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* Author: Nagaraju Lakkaraju
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* License: Dual MIT/GPL
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* Copyright (c) 2016 Microsemi Corporation
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mdio.h>
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#include <linux/mii.h>
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#include <linux/phy.h>
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#include <linux/of.h>
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#include <linux/netdevice.h>
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enum rgmii_rx_clock_delay {
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RGMII_RX_CLK_DELAY_0_2_NS = 0,
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RGMII_RX_CLK_DELAY_0_8_NS = 1,
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RGMII_RX_CLK_DELAY_1_1_NS = 2,
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RGMII_RX_CLK_DELAY_1_7_NS = 3,
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RGMII_RX_CLK_DELAY_2_0_NS = 4,
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RGMII_RX_CLK_DELAY_2_3_NS = 5,
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RGMII_RX_CLK_DELAY_2_6_NS = 6,
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RGMII_RX_CLK_DELAY_3_4_NS = 7
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};
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/* Microsemi VSC85xx PHY registers */
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/* IEEE 802. Std Registers */
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#define MSCC_PHY_EXT_PHY_CNTL_1 23
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#define MAC_IF_SELECTION_MASK 0x1800
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#define MAC_IF_SELECTION_GMII 0
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#define MAC_IF_SELECTION_RMII 1
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#define MAC_IF_SELECTION_RGMII 2
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#define MAC_IF_SELECTION_POS 11
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#define FAR_END_LOOPBACK_MODE_MASK 0x0008
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#define MII_VSC85XX_INT_MASK 25
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#define MII_VSC85XX_INT_MASK_MASK 0xa000
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#define MII_VSC85XX_INT_MASK_WOL 0x0040
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#define MII_VSC85XX_INT_STATUS 26
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#define MSCC_PHY_WOL_MAC_CONTROL 27
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#define EDGE_RATE_CNTL_POS 5
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#define EDGE_RATE_CNTL_MASK 0x00E0
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#define MSCC_EXT_PAGE_ACCESS 31
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#define MSCC_PHY_PAGE_STANDARD 0x0000 /* Standard registers */
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#define MSCC_PHY_PAGE_EXTENDED_2 0x0002 /* Extended reg - page 2 */
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/* Extended Page 2 Registers */
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#define MSCC_PHY_RGMII_CNTL 20
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#define RGMII_RX_CLK_DELAY_MASK 0x0070
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#define RGMII_RX_CLK_DELAY_POS 4
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#define MSCC_PHY_WOL_LOWER_MAC_ADDR 21
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#define MSCC_PHY_WOL_MID_MAC_ADDR 22
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#define MSCC_PHY_WOL_UPPER_MAC_ADDR 23
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#define MSCC_PHY_WOL_LOWER_PASSWD 24
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#define MSCC_PHY_WOL_MID_PASSWD 25
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#define MSCC_PHY_WOL_UPPER_PASSWD 26
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#define MSCC_PHY_WOL_MAC_CONTROL 27
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#define SECURE_ON_ENABLE 0x8000
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#define SECURE_ON_PASSWD_LEN_4 0x4000
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/* Microsemi PHY ID's */
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#define PHY_ID_VSC8531 0x00070570
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#define PHY_ID_VSC8541 0x00070770
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#define MSCC_VDDMAC_1500 1500
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#define MSCC_VDDMAC_1800 1800
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#define MSCC_VDDMAC_2500 2500
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#define MSCC_VDDMAC_3300 3300
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struct vsc8531_private {
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int rate_magic;
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};
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#ifdef CONFIG_OF_MDIO
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struct vsc8531_edge_rate_table {
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u16 vddmac;
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u8 slowdown[8];
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};
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static const struct vsc8531_edge_rate_table edge_table[] = {
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{MSCC_VDDMAC_3300, { 0, 2, 4, 7, 10, 17, 29, 53} },
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{MSCC_VDDMAC_2500, { 0, 3, 6, 10, 14, 23, 37, 63} },
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{MSCC_VDDMAC_1800, { 0, 5, 9, 16, 23, 35, 52, 76} },
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{MSCC_VDDMAC_1500, { 0, 6, 14, 21, 29, 42, 58, 77} },
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};
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#endif /* CONFIG_OF_MDIO */
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static int vsc85xx_phy_page_set(struct phy_device *phydev, u8 page)
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{
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int rc;
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rc = phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page);
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return rc;
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}
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static int vsc85xx_wol_set(struct phy_device *phydev,
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struct ethtool_wolinfo *wol)
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{
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int rc;
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u16 reg_val;
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u8 i;
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u16 pwd[3] = {0, 0, 0};
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struct ethtool_wolinfo *wol_conf = wol;
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u8 *mac_addr = phydev->attached_dev->dev_addr;
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mutex_lock(&phydev->lock);
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rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
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if (rc != 0)
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goto out_unlock;
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if (wol->wolopts & WAKE_MAGIC) {
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/* Store the device address for the magic packet */
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for (i = 0; i < ARRAY_SIZE(pwd); i++)
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pwd[i] = mac_addr[5 - (i * 2 + 1)] << 8 |
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mac_addr[5 - i * 2];
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phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]);
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phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]);
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phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]);
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} else {
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phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0);
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phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0);
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phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0);
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}
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if (wol_conf->wolopts & WAKE_MAGICSECURE) {
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for (i = 0; i < ARRAY_SIZE(pwd); i++)
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pwd[i] = wol_conf->sopass[5 - (i * 2 + 1)] << 8 |
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wol_conf->sopass[5 - i * 2];
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phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]);
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phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]);
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phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]);
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} else {
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phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0);
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phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0);
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phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0);
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}
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reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
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if (wol_conf->wolopts & WAKE_MAGICSECURE)
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reg_val |= SECURE_ON_ENABLE;
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else
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reg_val &= ~SECURE_ON_ENABLE;
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phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
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rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
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if (rc != 0)
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goto out_unlock;
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if (wol->wolopts & WAKE_MAGIC) {
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/* Enable the WOL interrupt */
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reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
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reg_val |= MII_VSC85XX_INT_MASK_WOL;
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rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
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if (rc != 0)
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goto out_unlock;
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} else {
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/* Disable the WOL interrupt */
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reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
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reg_val &= (~MII_VSC85XX_INT_MASK_WOL);
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rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
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if (rc != 0)
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goto out_unlock;
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}
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/* Clear WOL iterrupt status */
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reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS);
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out_unlock:
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mutex_unlock(&phydev->lock);
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return rc;
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}
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static void vsc85xx_wol_get(struct phy_device *phydev,
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struct ethtool_wolinfo *wol)
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{
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int rc;
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u16 reg_val;
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u8 i;
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u16 pwd[3] = {0, 0, 0};
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struct ethtool_wolinfo *wol_conf = wol;
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mutex_lock(&phydev->lock);
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rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
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if (rc != 0)
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goto out_unlock;
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reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
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if (reg_val & SECURE_ON_ENABLE)
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wol_conf->wolopts |= WAKE_MAGICSECURE;
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if (wol_conf->wolopts & WAKE_MAGICSECURE) {
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pwd[0] = phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD);
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pwd[1] = phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD);
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pwd[2] = phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD);
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for (i = 0; i < ARRAY_SIZE(pwd); i++) {
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wol_conf->sopass[5 - i * 2] = pwd[i] & 0x00ff;
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wol_conf->sopass[5 - (i * 2 + 1)] = (pwd[i] & 0xff00)
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>> 8;
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}
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}
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rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
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out_unlock:
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mutex_unlock(&phydev->lock);
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}
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#ifdef CONFIG_OF_MDIO
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static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
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{
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u8 sd;
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u16 vdd;
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int rc, i, j;
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struct device *dev = &phydev->mdio.dev;
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struct device_node *of_node = dev->of_node;
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u8 sd_array_size = ARRAY_SIZE(edge_table[0].slowdown);
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if (!of_node)
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return -ENODEV;
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rc = of_property_read_u16(of_node, "vsc8531,vddmac", &vdd);
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if (rc != 0)
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vdd = MSCC_VDDMAC_3300;
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rc = of_property_read_u8(of_node, "vsc8531,edge-slowdown", &sd);
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if (rc != 0)
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sd = 0;
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for (i = 0; i < ARRAY_SIZE(edge_table); i++)
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if (edge_table[i].vddmac == vdd)
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for (j = 0; j < sd_array_size; j++)
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if (edge_table[i].slowdown[j] == sd)
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return (sd_array_size - j - 1);
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return -EINVAL;
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}
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#else
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static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
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{
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return 0;
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}
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#endif /* CONFIG_OF_MDIO */
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static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate)
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{
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int rc;
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u16 reg_val;
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mutex_lock(&phydev->lock);
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rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
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if (rc != 0)
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goto out_unlock;
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reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
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reg_val &= ~(EDGE_RATE_CNTL_MASK);
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reg_val |= (edge_rate << EDGE_RATE_CNTL_POS);
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rc = phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
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if (rc != 0)
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goto out_unlock;
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rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
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out_unlock:
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mutex_unlock(&phydev->lock);
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return rc;
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}
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static int vsc85xx_mac_if_set(struct phy_device *phydev,
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phy_interface_t interface)
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{
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int rc;
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u16 reg_val;
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mutex_lock(&phydev->lock);
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reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
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reg_val &= ~(MAC_IF_SELECTION_MASK);
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switch (interface) {
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case PHY_INTERFACE_MODE_RGMII:
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reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS);
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break;
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case PHY_INTERFACE_MODE_RMII:
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reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS);
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break;
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case PHY_INTERFACE_MODE_MII:
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case PHY_INTERFACE_MODE_GMII:
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reg_val |= (MAC_IF_SELECTION_GMII << MAC_IF_SELECTION_POS);
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break;
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default:
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rc = -EINVAL;
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goto out_unlock;
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}
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rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val);
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if (rc != 0)
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goto out_unlock;
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rc = genphy_soft_reset(phydev);
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out_unlock:
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mutex_unlock(&phydev->lock);
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return rc;
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}
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static int vsc85xx_default_config(struct phy_device *phydev)
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{
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int rc;
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u16 reg_val;
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mutex_lock(&phydev->lock);
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rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
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if (rc != 0)
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goto out_unlock;
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reg_val = phy_read(phydev, MSCC_PHY_RGMII_CNTL);
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reg_val &= ~(RGMII_RX_CLK_DELAY_MASK);
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reg_val |= (RGMII_RX_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS);
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phy_write(phydev, MSCC_PHY_RGMII_CNTL, reg_val);
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rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
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out_unlock:
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mutex_unlock(&phydev->lock);
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return rc;
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}
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static int vsc85xx_config_init(struct phy_device *phydev)
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{
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int rc;
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struct vsc8531_private *vsc8531 = phydev->priv;
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rc = vsc85xx_default_config(phydev);
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if (rc)
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return rc;
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rc = vsc85xx_mac_if_set(phydev, phydev->interface);
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if (rc)
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return rc;
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rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->rate_magic);
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if (rc)
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return rc;
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rc = genphy_config_init(phydev);
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return rc;
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}
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static int vsc85xx_ack_interrupt(struct phy_device *phydev)
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{
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int rc = 0;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
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rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
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return (rc < 0) ? rc : 0;
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}
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static int vsc85xx_config_intr(struct phy_device *phydev)
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{
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int rc;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
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rc = phy_write(phydev, MII_VSC85XX_INT_MASK,
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MII_VSC85XX_INT_MASK_MASK);
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} else {
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rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0);
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if (rc < 0)
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return rc;
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rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
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}
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return rc;
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}
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static int vsc85xx_probe(struct phy_device *phydev)
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{
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int rate_magic;
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struct vsc8531_private *vsc8531;
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rate_magic = vsc85xx_edge_rate_magic_get(phydev);
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if (rate_magic < 0)
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return rate_magic;
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vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
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if (!vsc8531)
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return -ENOMEM;
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phydev->priv = vsc8531;
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vsc8531->rate_magic = rate_magic;
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return 0;
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}
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/* Microsemi VSC85xx PHYs */
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static struct phy_driver vsc85xx_driver[] = {
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{
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.phy_id = PHY_ID_VSC8531,
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.name = "Microsemi VSC8531",
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.phy_id_mask = 0xfffffff0,
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.features = PHY_GBIT_FEATURES,
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.flags = PHY_HAS_INTERRUPT,
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.soft_reset = &genphy_soft_reset,
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.config_init = &vsc85xx_config_init,
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.config_aneg = &genphy_config_aneg,
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.aneg_done = &genphy_aneg_done,
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.read_status = &genphy_read_status,
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.ack_interrupt = &vsc85xx_ack_interrupt,
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.config_intr = &vsc85xx_config_intr,
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.suspend = &genphy_suspend,
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.resume = &genphy_resume,
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.probe = &vsc85xx_probe,
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.set_wol = &vsc85xx_wol_set,
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.get_wol = &vsc85xx_wol_get,
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},
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{
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.phy_id = PHY_ID_VSC8541,
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.name = "Microsemi VSC8541 SyncE",
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.phy_id_mask = 0xfffffff0,
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.features = PHY_GBIT_FEATURES,
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.flags = PHY_HAS_INTERRUPT,
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.soft_reset = &genphy_soft_reset,
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.config_init = &vsc85xx_config_init,
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.config_aneg = &genphy_config_aneg,
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.aneg_done = &genphy_aneg_done,
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.read_status = &genphy_read_status,
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.ack_interrupt = &vsc85xx_ack_interrupt,
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.config_intr = &vsc85xx_config_intr,
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.suspend = &genphy_suspend,
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.resume = &genphy_resume,
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.probe = &vsc85xx_probe,
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.set_wol = &vsc85xx_wol_set,
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.get_wol = &vsc85xx_wol_get,
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}
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};
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module_phy_driver(vsc85xx_driver);
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static struct mdio_device_id __maybe_unused vsc85xx_tbl[] = {
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{ PHY_ID_VSC8531, 0xfffffff0, },
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{ PHY_ID_VSC8541, 0xfffffff0, },
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, vsc85xx_tbl);
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MODULE_DESCRIPTION("Microsemi VSC85xx PHY driver");
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MODULE_AUTHOR("Nagaraju Lakkaraju");
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MODULE_LICENSE("Dual MIT/GPL");
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