![Arnd Bergmann](/assets/img/avatar_default.png)
While looking at a patch that introduced a compile-time warning
"‘pmc_core_dev_state_get’ defined but not used" (I sent a patch
for debugfs to fix it), I noticed that the same patch caused
it in intel_pmc_core also introduced a bogus run-time warning:
"PMC Core: debugfs register failed".
The problem is the IS_ERR_OR_NULL() check that as usual gets
things wrong: when CONFIG_DEBUGFS_FS is disabled,
debugfs_create_dir() fails with an error code, and we don't
need to warn about it, unlike the case in which it returns
NULL.
This reverts the driver to the previous state of not warning
about CONFIG_DEBUGFS_FS being disabled. I chose not to
restore the driver to making a runtime error in debugfs
fatal in pmc_core_probe().
Fixes: df2294fb64
("intel_pmc_core: Convert to DEFINE_DEBUGFS_ATTRIBUTE")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
177 lines
4.5 KiB
C
177 lines
4.5 KiB
C
/*
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* Intel Core SoC Power Management Controller Driver
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*
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* Copyright (c) 2016, Intel Corporation.
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* All Rights Reserved.
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*
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* Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
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* Vishwanath Somayaji <vishwanath.somayaji@intel.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#include <linux/debugfs.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/pci.h>
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#include <asm/cpu_device_id.h>
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#include <asm/intel-family.h>
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#include <asm/pmc_core.h>
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#include "intel_pmc_core.h"
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static struct pmc_dev pmc;
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static const struct pci_device_id pmc_pci_ids[] = {
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{ PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID), (kernel_ulong_t)NULL },
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{ 0, },
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};
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static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
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{
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return readl(pmcdev->regbase + reg_offset);
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}
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static inline u32 pmc_core_adjust_slp_s0_step(u32 value)
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{
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return value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
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}
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/**
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* intel_pmc_slp_s0_counter_read() - Read SLP_S0 residency.
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* @data: Out param that contains current SLP_S0 count.
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*
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* This API currently supports Intel Skylake SoC and Sunrise
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* Point Platform Controller Hub. Future platform support
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* should be added for platforms that support low power modes
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* beyond Package C10 state.
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*
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* SLP_S0_RESIDENCY counter counts in 100 us granularity per
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* step hence function populates the multiplied value in out
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* parameter @data.
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*
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* Return: an error code or 0 on success.
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*/
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int intel_pmc_slp_s0_counter_read(u32 *data)
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{
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struct pmc_dev *pmcdev = &pmc;
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u32 value;
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if (!pmcdev->has_slp_s0_res)
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return -EACCES;
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value = pmc_core_reg_read(pmcdev, SPT_PMC_SLP_S0_RES_COUNTER_OFFSET);
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*data = pmc_core_adjust_slp_s0_step(value);
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return 0;
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}
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EXPORT_SYMBOL_GPL(intel_pmc_slp_s0_counter_read);
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static int pmc_core_dev_state_get(void *data, u64 *val)
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{
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struct pmc_dev *pmcdev = data;
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u32 value;
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value = pmc_core_reg_read(pmcdev, SPT_PMC_SLP_S0_RES_COUNTER_OFFSET);
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*val = pmc_core_adjust_slp_s0_step(value);
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return 0;
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}
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DEFINE_DEBUGFS_ATTRIBUTE(pmc_core_dev_state, pmc_core_dev_state_get, NULL, "%llu\n");
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static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
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{
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debugfs_remove_recursive(pmcdev->dbgfs_dir);
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}
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static int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
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{
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struct dentry *dir, *file;
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dir = debugfs_create_dir("pmc_core", NULL);
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if (!dir)
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return -ENOMEM;
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pmcdev->dbgfs_dir = dir;
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file = debugfs_create_file("slp_s0_residency_usec", S_IFREG | S_IRUGO,
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dir, pmcdev, &pmc_core_dev_state);
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if (!file) {
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pmc_core_dbgfs_unregister(pmcdev);
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return -ENODEV;
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}
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return 0;
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}
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static const struct x86_cpu_id intel_pmc_core_ids[] = {
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_MOBILE, X86_FEATURE_MWAIT,
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(kernel_ulong_t)NULL},
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_DESKTOP, X86_FEATURE_MWAIT,
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(kernel_ulong_t)NULL},
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{}
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};
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static int pmc_core_probe(struct pci_dev *dev, const struct pci_device_id *id)
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{
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struct device *ptr_dev = &dev->dev;
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struct pmc_dev *pmcdev = &pmc;
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const struct x86_cpu_id *cpu_id;
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int err;
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cpu_id = x86_match_cpu(intel_pmc_core_ids);
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if (!cpu_id) {
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dev_dbg(&dev->dev, "PMC Core: cpuid mismatch.\n");
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return -EINVAL;
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}
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err = pcim_enable_device(dev);
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if (err < 0) {
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dev_dbg(&dev->dev, "PMC Core: failed to enable Power Management Controller.\n");
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return err;
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}
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err = pci_read_config_dword(dev,
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SPT_PMC_BASE_ADDR_OFFSET,
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&pmcdev->base_addr);
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if (err < 0) {
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dev_dbg(&dev->dev, "PMC Core: failed to read PCI config space.\n");
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return err;
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}
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dev_dbg(&dev->dev, "PMC Core: PWRMBASE is %#x\n", pmcdev->base_addr);
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pmcdev->regbase = devm_ioremap_nocache(ptr_dev,
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pmcdev->base_addr,
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SPT_PMC_MMIO_REG_LEN);
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if (!pmcdev->regbase) {
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dev_dbg(&dev->dev, "PMC Core: ioremap failed.\n");
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return -ENOMEM;
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}
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err = pmc_core_dbgfs_register(pmcdev);
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if (err < 0)
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dev_warn(&dev->dev, "PMC Core: debugfs register failed.\n");
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pmc.has_slp_s0_res = true;
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return 0;
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}
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static struct pci_driver intel_pmc_core_driver = {
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.name = "intel_pmc_core",
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.id_table = pmc_pci_ids,
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.probe = pmc_core_probe,
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};
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builtin_pci_driver(intel_pmc_core_driver);
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