![Paul Gortmaker](/assets/img/avatar_default.png)
The Kconfig entry controlling compilation of this code is: drivers/platform/x86/Kconfig:config GPIO_INTEL_PMIC drivers/platform/x86/Kconfig: bool "Intel PMIC GPIO support" ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. We delete the MODULE_LICENSE tag etc. since all that information was (or is now) contained at the top of the file in the comments. We don't replace module.h with init.h since the file already has that. Cc: Alek Du <alek.du@intel.com> Cc: platform-driver-x86@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Darren Hart <dvhart@linux.intel.com>
327 lines
8 KiB
C
327 lines
8 KiB
C
/* Moorestown PMIC GPIO (access through IPC) driver
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* Copyright (c) 2008 - 2009, Intel Corporation.
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*
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* Author: Alek Du <alek.du@intel.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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/* Supports:
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* Moorestown platform PMIC chip
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/stddef.h>
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#include <linux/slab.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/gpio/driver.h>
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#include <asm/intel_scu_ipc.h>
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#include <linux/device.h>
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#include <linux/intel_pmic_gpio.h>
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#include <linux/platform_device.h>
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#define DRIVER_NAME "pmic_gpio"
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/* register offset that IPC driver should use
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* 8 GPIO + 8 GPOSW (6 controllable) + 8GPO
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*/
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enum pmic_gpio_register {
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GPIO0 = 0xE0,
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GPIO7 = 0xE7,
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GPIOINT = 0xE8,
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GPOSWCTL0 = 0xEC,
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GPOSWCTL5 = 0xF1,
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GPO = 0xF4,
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};
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/* bits definition for GPIO & GPOSW */
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#define GPIO_DRV 0x01
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#define GPIO_DIR 0x02
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#define GPIO_DIN 0x04
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#define GPIO_DOU 0x08
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#define GPIO_INTCTL 0x30
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#define GPIO_DBC 0xc0
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#define GPOSW_DRV 0x01
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#define GPOSW_DOU 0x08
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#define GPOSW_RDRV 0x30
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#define GPIO_UPDATE_TYPE 0x80000000
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#define NUM_GPIO 24
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struct pmic_gpio {
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struct mutex buslock;
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struct gpio_chip chip;
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void *gpiointr;
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int irq;
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unsigned irq_base;
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unsigned int update_type;
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u32 trigger_type;
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};
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static void pmic_program_irqtype(int gpio, int type)
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{
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if (type & IRQ_TYPE_EDGE_RISING)
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intel_scu_ipc_update_register(GPIO0 + gpio, 0x20, 0x20);
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else
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intel_scu_ipc_update_register(GPIO0 + gpio, 0x00, 0x20);
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if (type & IRQ_TYPE_EDGE_FALLING)
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intel_scu_ipc_update_register(GPIO0 + gpio, 0x10, 0x10);
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else
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intel_scu_ipc_update_register(GPIO0 + gpio, 0x00, 0x10);
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};
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static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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if (offset >= 8) {
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pr_err("only pin 0-7 support input\n");
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return -1;/* we only have 8 GPIO can use as input */
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}
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return intel_scu_ipc_update_register(GPIO0 + offset,
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GPIO_DIR, GPIO_DIR);
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}
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static int pmic_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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int rc = 0;
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if (offset < 8)/* it is GPIO */
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rc = intel_scu_ipc_update_register(GPIO0 + offset,
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GPIO_DRV | (value ? GPIO_DOU : 0),
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GPIO_DRV | GPIO_DOU | GPIO_DIR);
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else if (offset < 16)/* it is GPOSW */
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rc = intel_scu_ipc_update_register(GPOSWCTL0 + offset - 8,
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GPOSW_DRV | (value ? GPOSW_DOU : 0),
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GPOSW_DRV | GPOSW_DOU | GPOSW_RDRV);
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else if (offset > 15 && offset < 24)/* it is GPO */
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rc = intel_scu_ipc_update_register(GPO,
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value ? 1 << (offset - 16) : 0,
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1 << (offset - 16));
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else {
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pr_err("invalid PMIC GPIO pin %d!\n", offset);
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WARN_ON(1);
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}
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return rc;
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}
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static int pmic_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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u8 r;
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int ret;
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/* we only have 8 GPIO pins we can use as input */
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if (offset >= 8)
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return -EOPNOTSUPP;
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ret = intel_scu_ipc_ioread8(GPIO0 + offset, &r);
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if (ret < 0)
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return ret;
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return r & GPIO_DIN;
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}
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static void pmic_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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if (offset < 8)/* it is GPIO */
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intel_scu_ipc_update_register(GPIO0 + offset,
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GPIO_DRV | (value ? GPIO_DOU : 0),
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GPIO_DRV | GPIO_DOU);
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else if (offset < 16)/* it is GPOSW */
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intel_scu_ipc_update_register(GPOSWCTL0 + offset - 8,
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GPOSW_DRV | (value ? GPOSW_DOU : 0),
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GPOSW_DRV | GPOSW_DOU | GPOSW_RDRV);
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else if (offset > 15 && offset < 24) /* it is GPO */
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intel_scu_ipc_update_register(GPO,
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value ? 1 << (offset - 16) : 0,
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1 << (offset - 16));
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}
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/*
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* This is called from genirq with pg->buslock locked and
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* irq_desc->lock held. We can not access the scu bus here, so we
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* store the change and update in the bus_sync_unlock() function below
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*/
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static int pmic_irq_type(struct irq_data *data, unsigned type)
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{
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struct pmic_gpio *pg = irq_data_get_irq_chip_data(data);
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u32 gpio = data->irq - pg->irq_base;
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if (gpio >= pg->chip.ngpio)
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return -EINVAL;
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pg->trigger_type = type;
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pg->update_type = gpio | GPIO_UPDATE_TYPE;
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return 0;
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}
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static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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struct pmic_gpio *pg = gpiochip_get_data(chip);
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return pg->irq_base + offset;
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}
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static void pmic_bus_lock(struct irq_data *data)
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{
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struct pmic_gpio *pg = irq_data_get_irq_chip_data(data);
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mutex_lock(&pg->buslock);
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}
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static void pmic_bus_sync_unlock(struct irq_data *data)
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{
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struct pmic_gpio *pg = irq_data_get_irq_chip_data(data);
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if (pg->update_type) {
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unsigned int gpio = pg->update_type & ~GPIO_UPDATE_TYPE;
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pmic_program_irqtype(gpio, pg->trigger_type);
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pg->update_type = 0;
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}
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mutex_unlock(&pg->buslock);
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}
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/* the gpiointr register is read-clear, so just do nothing. */
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static void pmic_irq_unmask(struct irq_data *data) { }
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static void pmic_irq_mask(struct irq_data *data) { }
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static struct irq_chip pmic_irqchip = {
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.name = "PMIC-GPIO",
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.irq_mask = pmic_irq_mask,
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.irq_unmask = pmic_irq_unmask,
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.irq_set_type = pmic_irq_type,
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.irq_bus_lock = pmic_bus_lock,
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.irq_bus_sync_unlock = pmic_bus_sync_unlock,
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};
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static irqreturn_t pmic_irq_handler(int irq, void *data)
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{
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struct pmic_gpio *pg = data;
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u8 intsts = *((u8 *)pg->gpiointr + 4);
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int gpio;
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irqreturn_t ret = IRQ_NONE;
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for (gpio = 0; gpio < 8; gpio++) {
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if (intsts & (1 << gpio)) {
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pr_debug("pmic pin %d triggered\n", gpio);
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generic_handle_irq(pg->irq_base + gpio);
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ret = IRQ_HANDLED;
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}
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}
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return ret;
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}
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static int platform_pmic_gpio_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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int irq = platform_get_irq(pdev, 0);
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struct intel_pmic_gpio_platform_data *pdata = dev->platform_data;
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struct pmic_gpio *pg;
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int retval;
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int i;
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if (irq < 0) {
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dev_dbg(dev, "no IRQ line\n");
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return -EINVAL;
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}
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if (!pdata || !pdata->gpio_base || !pdata->irq_base) {
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dev_dbg(dev, "incorrect or missing platform data\n");
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return -EINVAL;
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}
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pg = kzalloc(sizeof(*pg), GFP_KERNEL);
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if (!pg)
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return -ENOMEM;
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dev_set_drvdata(dev, pg);
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pg->irq = irq;
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/* setting up SRAM mapping for GPIOINT register */
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pg->gpiointr = ioremap_nocache(pdata->gpiointr, 8);
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if (!pg->gpiointr) {
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pr_err("Can not map GPIOINT\n");
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retval = -EINVAL;
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goto err2;
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}
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pg->irq_base = pdata->irq_base;
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pg->chip.label = "intel_pmic";
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pg->chip.direction_input = pmic_gpio_direction_input;
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pg->chip.direction_output = pmic_gpio_direction_output;
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pg->chip.get = pmic_gpio_get;
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pg->chip.set = pmic_gpio_set;
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pg->chip.to_irq = pmic_gpio_to_irq;
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pg->chip.base = pdata->gpio_base;
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pg->chip.ngpio = NUM_GPIO;
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pg->chip.can_sleep = 1;
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pg->chip.parent = dev;
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mutex_init(&pg->buslock);
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pg->chip.parent = dev;
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retval = gpiochip_add_data(&pg->chip, pg);
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if (retval) {
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pr_err("Can not add pmic gpio chip\n");
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goto err;
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}
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retval = request_irq(pg->irq, pmic_irq_handler, 0, "pmic", pg);
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if (retval) {
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pr_warn("Interrupt request failed\n");
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goto fail_request_irq;
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}
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for (i = 0; i < 8; i++) {
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irq_set_chip_and_handler_name(i + pg->irq_base,
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&pmic_irqchip,
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handle_simple_irq,
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"demux");
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irq_set_chip_data(i + pg->irq_base, pg);
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}
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return 0;
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fail_request_irq:
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gpiochip_remove(&pg->chip);
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err:
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iounmap(pg->gpiointr);
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err2:
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kfree(pg);
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return retval;
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}
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/* at the same time, register a platform driver
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* this supports the sfi 0.81 fw */
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static struct platform_driver platform_pmic_gpio_driver = {
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.driver = {
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.name = DRIVER_NAME,
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},
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.probe = platform_pmic_gpio_probe,
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};
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static int __init platform_pmic_gpio_init(void)
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{
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return platform_driver_register(&platform_pmic_gpio_driver);
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}
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subsys_initcall(platform_pmic_gpio_init);
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