![Johan Hovold](/assets/img/avatar_default.png)
Make sure to deregister and free any fixed-link phy registered during probe on probe errors and on driver unbind by adding a new glue helper function. Drop the of-node reference taken in the same path also on late probe errors (and not just on driver unbind) by moving the put from stmmac_dvr_remove() to the new helper. Fixes:277323814e
("stmmac: add fixed-link device-tree support") Fixes:4613b279be
("ethernet: stmicro: stmmac: add missing of_node_put after calling of_parse_phandle") Signed-off-by: Johan Hovold <johan@kernel.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: David S. Miller <davem@davemloft.net>
385 lines
11 KiB
C
385 lines
11 KiB
C
/*
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* Qualcomm Atheros IPQ806x GMAC glue layer
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*
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* Copyright (C) 2015 The Linux Foundation
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/phy.h>
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#include <linux/regmap.h>
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#include <linux/clk.h>
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#include <linux/reset.h>
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#include <linux/of_net.h>
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#include <linux/mfd/syscon.h>
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#include <linux/stmmac.h>
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#include <linux/of_mdio.h>
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#include <linux/module.h>
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#include "stmmac_platform.h"
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#define NSS_COMMON_CLK_GATE 0x8
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#define NSS_COMMON_CLK_GATE_PTP_EN(x) BIT(0x10 + x)
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#define NSS_COMMON_CLK_GATE_RGMII_RX_EN(x) BIT(0x9 + (x * 2))
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#define NSS_COMMON_CLK_GATE_RGMII_TX_EN(x) BIT(0x8 + (x * 2))
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#define NSS_COMMON_CLK_GATE_GMII_RX_EN(x) BIT(0x4 + x)
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#define NSS_COMMON_CLK_GATE_GMII_TX_EN(x) BIT(0x0 + x)
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#define NSS_COMMON_CLK_DIV0 0xC
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#define NSS_COMMON_CLK_DIV_OFFSET(x) (x * 8)
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#define NSS_COMMON_CLK_DIV_MASK 0x7f
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#define NSS_COMMON_CLK_SRC_CTRL 0x14
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#define NSS_COMMON_CLK_SRC_CTRL_OFFSET(x) (x)
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/* Mode is coded on 1 bit but is different depending on the MAC ID:
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* MAC0: QSGMII=0 RGMII=1
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* MAC1: QSGMII=0 SGMII=0 RGMII=1
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* MAC2 & MAC3: QSGMII=0 SGMII=1
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*/
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#define NSS_COMMON_CLK_SRC_CTRL_RGMII(x) 1
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#define NSS_COMMON_CLK_SRC_CTRL_SGMII(x) ((x >= 2) ? 1 : 0)
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#define NSS_COMMON_MACSEC_CTL 0x28
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#define NSS_COMMON_MACSEC_CTL_EXT_BYPASS_EN(x) (1 << x)
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#define NSS_COMMON_GMAC_CTL(x) (0x30 + (x * 4))
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#define NSS_COMMON_GMAC_CTL_CSYS_REQ BIT(19)
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#define NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL BIT(16)
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#define NSS_COMMON_GMAC_CTL_IFG_LIMIT_OFFSET 8
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#define NSS_COMMON_GMAC_CTL_IFG_OFFSET 0
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#define NSS_COMMON_GMAC_CTL_IFG_MASK 0x3f
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#define NSS_COMMON_CLK_DIV_RGMII_1000 1
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#define NSS_COMMON_CLK_DIV_RGMII_100 9
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#define NSS_COMMON_CLK_DIV_RGMII_10 99
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#define NSS_COMMON_CLK_DIV_SGMII_1000 0
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#define NSS_COMMON_CLK_DIV_SGMII_100 4
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#define NSS_COMMON_CLK_DIV_SGMII_10 49
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#define QSGMII_PCS_MODE_CTL 0x68
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#define QSGMII_PCS_MODE_CTL_AUTONEG_EN(x) BIT((x * 8) + 7)
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#define QSGMII_PCS_CAL_LCKDT_CTL 0x120
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#define QSGMII_PCS_CAL_LCKDT_CTL_RST BIT(19)
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/* Only GMAC1/2/3 support SGMII and their CTL register are not contiguous */
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#define QSGMII_PHY_SGMII_CTL(x) ((x == 1) ? 0x134 : \
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(0x13c + (4 * (x - 2))))
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#define QSGMII_PHY_CDR_EN BIT(0)
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#define QSGMII_PHY_RX_FRONT_EN BIT(1)
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#define QSGMII_PHY_RX_SIGNAL_DETECT_EN BIT(2)
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#define QSGMII_PHY_TX_DRIVER_EN BIT(3)
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#define QSGMII_PHY_QSGMII_EN BIT(7)
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#define QSGMII_PHY_PHASE_LOOP_GAIN_OFFSET 12
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#define QSGMII_PHY_PHASE_LOOP_GAIN_MASK 0x7
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#define QSGMII_PHY_RX_DC_BIAS_OFFSET 18
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#define QSGMII_PHY_RX_DC_BIAS_MASK 0x3
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#define QSGMII_PHY_RX_INPUT_EQU_OFFSET 20
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#define QSGMII_PHY_RX_INPUT_EQU_MASK 0x3
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#define QSGMII_PHY_CDR_PI_SLEW_OFFSET 22
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#define QSGMII_PHY_CDR_PI_SLEW_MASK 0x3
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#define QSGMII_PHY_TX_DRV_AMP_OFFSET 28
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#define QSGMII_PHY_TX_DRV_AMP_MASK 0xf
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struct ipq806x_gmac {
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struct platform_device *pdev;
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struct regmap *nss_common;
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struct regmap *qsgmii_csr;
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uint32_t id;
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struct clk *core_clk;
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phy_interface_t phy_mode;
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};
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static int get_clk_div_sgmii(struct ipq806x_gmac *gmac, unsigned int speed)
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{
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struct device *dev = &gmac->pdev->dev;
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int div;
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switch (speed) {
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case SPEED_1000:
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div = NSS_COMMON_CLK_DIV_SGMII_1000;
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break;
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case SPEED_100:
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div = NSS_COMMON_CLK_DIV_SGMII_100;
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break;
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case SPEED_10:
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div = NSS_COMMON_CLK_DIV_SGMII_10;
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break;
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default:
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dev_err(dev, "Speed %dMbps not supported in SGMII\n", speed);
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return -EINVAL;
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}
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return div;
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}
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static int get_clk_div_rgmii(struct ipq806x_gmac *gmac, unsigned int speed)
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{
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struct device *dev = &gmac->pdev->dev;
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int div;
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switch (speed) {
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case SPEED_1000:
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div = NSS_COMMON_CLK_DIV_RGMII_1000;
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break;
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case SPEED_100:
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div = NSS_COMMON_CLK_DIV_RGMII_100;
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break;
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case SPEED_10:
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div = NSS_COMMON_CLK_DIV_RGMII_10;
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break;
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default:
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dev_err(dev, "Speed %dMbps not supported in RGMII\n", speed);
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return -EINVAL;
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}
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return div;
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}
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static int ipq806x_gmac_set_speed(struct ipq806x_gmac *gmac, unsigned int speed)
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{
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uint32_t clk_bits, val;
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int div;
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switch (gmac->phy_mode) {
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case PHY_INTERFACE_MODE_RGMII:
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div = get_clk_div_rgmii(gmac, speed);
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clk_bits = NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) |
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NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id);
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break;
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case PHY_INTERFACE_MODE_SGMII:
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div = get_clk_div_sgmii(gmac, speed);
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clk_bits = NSS_COMMON_CLK_GATE_GMII_RX_EN(gmac->id) |
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NSS_COMMON_CLK_GATE_GMII_TX_EN(gmac->id);
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break;
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default:
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dev_err(&gmac->pdev->dev, "Unsupported PHY mode: \"%s\"\n",
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phy_modes(gmac->phy_mode));
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return -EINVAL;
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}
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/* Disable the clocks */
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regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val);
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val &= ~clk_bits;
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regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val);
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/* Set the divider */
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regmap_read(gmac->nss_common, NSS_COMMON_CLK_DIV0, &val);
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val &= ~(NSS_COMMON_CLK_DIV_MASK
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<< NSS_COMMON_CLK_DIV_OFFSET(gmac->id));
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val |= div << NSS_COMMON_CLK_DIV_OFFSET(gmac->id);
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regmap_write(gmac->nss_common, NSS_COMMON_CLK_DIV0, val);
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/* Enable the clock back */
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regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val);
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val |= clk_bits;
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regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val);
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return 0;
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}
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static int ipq806x_gmac_of_parse(struct ipq806x_gmac *gmac)
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{
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struct device *dev = &gmac->pdev->dev;
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gmac->phy_mode = of_get_phy_mode(dev->of_node);
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if (gmac->phy_mode < 0) {
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dev_err(dev, "missing phy mode property\n");
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return -EINVAL;
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}
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if (of_property_read_u32(dev->of_node, "qcom,id", &gmac->id) < 0) {
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dev_err(dev, "missing qcom id property\n");
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return -EINVAL;
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}
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/* The GMACs are called 1 to 4 in the documentation, but to simplify the
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* code and keep it consistent with the Linux convention, we'll number
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* them from 0 to 3 here.
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*/
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if (gmac->id < 0 || gmac->id > 3) {
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dev_err(dev, "invalid gmac id\n");
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return -EINVAL;
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}
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gmac->core_clk = devm_clk_get(dev, "stmmaceth");
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if (IS_ERR(gmac->core_clk)) {
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dev_err(dev, "missing stmmaceth clk property\n");
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return PTR_ERR(gmac->core_clk);
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}
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clk_set_rate(gmac->core_clk, 266000000);
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/* Setup the register map for the nss common registers */
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gmac->nss_common = syscon_regmap_lookup_by_phandle(dev->of_node,
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"qcom,nss-common");
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if (IS_ERR(gmac->nss_common)) {
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dev_err(dev, "missing nss-common node\n");
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return PTR_ERR(gmac->nss_common);
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}
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/* Setup the register map for the qsgmii csr registers */
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gmac->qsgmii_csr = syscon_regmap_lookup_by_phandle(dev->of_node,
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"qcom,qsgmii-csr");
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if (IS_ERR(gmac->qsgmii_csr))
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dev_err(dev, "missing qsgmii-csr node\n");
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return PTR_ERR_OR_ZERO(gmac->qsgmii_csr);
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}
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static void ipq806x_gmac_fix_mac_speed(void *priv, unsigned int speed)
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{
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struct ipq806x_gmac *gmac = priv;
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ipq806x_gmac_set_speed(gmac, speed);
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}
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static int ipq806x_gmac_probe(struct platform_device *pdev)
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{
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struct plat_stmmacenet_data *plat_dat;
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struct stmmac_resources stmmac_res;
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struct device *dev = &pdev->dev;
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struct ipq806x_gmac *gmac;
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int val;
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int err;
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val = stmmac_get_platform_resources(pdev, &stmmac_res);
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if (val)
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return val;
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plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
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if (IS_ERR(plat_dat))
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return PTR_ERR(plat_dat);
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gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL);
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if (!gmac) {
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err = -ENOMEM;
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goto err_remove_config_dt;
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}
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gmac->pdev = pdev;
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err = ipq806x_gmac_of_parse(gmac);
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if (err) {
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dev_err(dev, "device tree parsing error\n");
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goto err_remove_config_dt;
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}
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regmap_write(gmac->qsgmii_csr, QSGMII_PCS_CAL_LCKDT_CTL,
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QSGMII_PCS_CAL_LCKDT_CTL_RST);
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/* Inter frame gap is set to 12 */
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val = 12 << NSS_COMMON_GMAC_CTL_IFG_OFFSET |
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12 << NSS_COMMON_GMAC_CTL_IFG_LIMIT_OFFSET;
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/* We also initiate an AXI low power exit request */
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val |= NSS_COMMON_GMAC_CTL_CSYS_REQ;
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switch (gmac->phy_mode) {
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case PHY_INTERFACE_MODE_RGMII:
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val |= NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL;
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break;
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case PHY_INTERFACE_MODE_SGMII:
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val &= ~NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL;
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break;
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default:
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dev_err(&pdev->dev, "Unsupported PHY mode: \"%s\"\n",
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phy_modes(gmac->phy_mode));
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err = -EINVAL;
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goto err_remove_config_dt;
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}
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regmap_write(gmac->nss_common, NSS_COMMON_GMAC_CTL(gmac->id), val);
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/* Configure the clock src according to the mode */
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regmap_read(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, &val);
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val &= ~(1 << NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id));
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switch (gmac->phy_mode) {
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case PHY_INTERFACE_MODE_RGMII:
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val |= NSS_COMMON_CLK_SRC_CTRL_RGMII(gmac->id) <<
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NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id);
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break;
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case PHY_INTERFACE_MODE_SGMII:
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val |= NSS_COMMON_CLK_SRC_CTRL_SGMII(gmac->id) <<
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NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id);
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break;
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default:
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dev_err(&pdev->dev, "Unsupported PHY mode: \"%s\"\n",
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phy_modes(gmac->phy_mode));
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err = -EINVAL;
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goto err_remove_config_dt;
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}
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regmap_write(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, val);
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/* Enable PTP clock */
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regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val);
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val |= NSS_COMMON_CLK_GATE_PTP_EN(gmac->id);
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regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val);
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if (gmac->phy_mode == PHY_INTERFACE_MODE_SGMII) {
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regmap_write(gmac->qsgmii_csr, QSGMII_PHY_SGMII_CTL(gmac->id),
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QSGMII_PHY_CDR_EN |
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QSGMII_PHY_RX_FRONT_EN |
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QSGMII_PHY_RX_SIGNAL_DETECT_EN |
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QSGMII_PHY_TX_DRIVER_EN |
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QSGMII_PHY_QSGMII_EN |
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0x4ul << QSGMII_PHY_PHASE_LOOP_GAIN_OFFSET |
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0x3ul << QSGMII_PHY_RX_DC_BIAS_OFFSET |
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0x1ul << QSGMII_PHY_RX_INPUT_EQU_OFFSET |
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0x2ul << QSGMII_PHY_CDR_PI_SLEW_OFFSET |
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0xCul << QSGMII_PHY_TX_DRV_AMP_OFFSET);
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}
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plat_dat->has_gmac = true;
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plat_dat->bsp_priv = gmac;
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plat_dat->fix_mac_speed = ipq806x_gmac_fix_mac_speed;
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err = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
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if (err)
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goto err_remove_config_dt;
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return 0;
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err_remove_config_dt:
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stmmac_remove_config_dt(pdev, plat_dat);
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return err;
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}
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static const struct of_device_id ipq806x_gmac_dwmac_match[] = {
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{ .compatible = "qcom,ipq806x-gmac" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, ipq806x_gmac_dwmac_match);
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static struct platform_driver ipq806x_gmac_dwmac_driver = {
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.probe = ipq806x_gmac_probe,
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.remove = stmmac_pltfr_remove,
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.driver = {
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.name = "ipq806x-gmac-dwmac",
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.pm = &stmmac_pltfr_pm_ops,
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.of_match_table = ipq806x_gmac_dwmac_match,
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},
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};
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module_platform_driver(ipq806x_gmac_dwmac_driver);
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MODULE_AUTHOR("Mathieu Olivari <mathieu@codeaurora.org>");
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MODULE_DESCRIPTION("Qualcomm Atheros IPQ806x DWMAC specific glue layer");
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MODULE_LICENSE("Dual BSD/GPL");
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