529ed12752
Instead of having individual PHY drivers set the SUPPORTED_Pause and
SUPPORTED_Asym_Pause flags, phylib itself should set those flags,
unless there is a hardware erratum or other special case. During
autonegotiation, the PHYs will determine whether to enable pause
frame support.
Pause frames are a feature that is supported by the MAC. It is the MAC
that generates the frames and that processes them. The PHY can only be
configured to allow them to pass through.
This commit also effectively reverts the recently applied c7a61319
("net: phy: dp83848: Support ethernet pause frames").
So the new process is:
1) Unless the PHY driver overrides it, phylib sets the SUPPORTED_Pause
and SUPPORTED_AsymPause bits in phydev->supported. This indicates that
the PHY supports pause frames.
2) The MAC driver checks phydev->supported before it calls phy_start().
If (SUPPORTED_Pause | SUPPORTED_AsymPause) is set, then the MAC driver
sets those bits in phydev->advertising, if it wants to enable pause
frame support.
3) When the link state changes, the MAC driver checks phydev->pause and
phydev->asym_pause, If the bits are set, then it enables the corresponding
features in the MAC. The algorithm is:
if (phydev->pause)
The MAC should be programmed to receive and honor
pause frames it receives, i.e. enable receive flow control.
if (phydev->pause != phydev->asym_pause)
The MAC should be programmed to transmit pause
frames when needed, i.e. enable transmit flow control.
Signed-off-by: Timur Tabi <timur@codeaurora.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
158 lines
4 KiB
C
158 lines
4 KiB
C
/*
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* Copyright (C) 2015 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Broadcom Cygnus SoC internal transceivers support. */
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#include "bcm-phy-lib.h"
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#include <linux/brcmphy.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/phy.h>
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/* Broadcom Cygnus Phy specific registers */
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#define MII_BCM_CYGNUS_AFE_VDAC_ICTRL_0 0x91E5 /* VDAL Control register */
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static int bcm_cygnus_afe_config(struct phy_device *phydev)
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{
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int rc;
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/* ensure smdspclk is enabled */
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rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, 0x0c30);
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if (rc < 0)
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return rc;
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/* AFE_VDAC_ICTRL_0 bit 7:4 Iq=1100 for 1g 10bt, normal modes */
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rc = bcm_phy_write_misc(phydev, 0x39, 0x01, 0xA7C8);
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if (rc < 0)
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return rc;
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/* AFE_HPF_TRIM_OTHERS bit11=1, short cascode enable for all modes*/
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rc = bcm_phy_write_misc(phydev, 0x3A, 0x00, 0x0803);
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if (rc < 0)
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return rc;
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/* AFE_TX_CONFIG_1 bit 7:4 Iq=1100 for test modes */
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rc = bcm_phy_write_misc(phydev, 0x3A, 0x01, 0xA740);
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if (rc < 0)
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return rc;
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/* AFE TEMPSEN_OTHERS rcal_HT, rcal_LT 10000 */
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rc = bcm_phy_write_misc(phydev, 0x3A, 0x03, 0x8400);
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if (rc < 0)
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return rc;
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/* AFE_FUTURE_RSV bit 2:0 rccal <2:0>=100 */
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rc = bcm_phy_write_misc(phydev, 0x3B, 0x00, 0x0004);
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if (rc < 0)
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return rc;
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/* Adjust bias current trim to overcome digital offSet */
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rc = phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x02);
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if (rc < 0)
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return rc;
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/* make rcal=100, since rdb default is 000 */
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rc = bcm_phy_write_exp(phydev, MII_BRCM_CORE_EXPB1, 0x10);
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if (rc < 0)
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return rc;
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/* CORE_EXPB0, Reset R_CAL/RC_CAL Engine */
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rc = bcm_phy_write_exp(phydev, MII_BRCM_CORE_EXPB0, 0x10);
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if (rc < 0)
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return rc;
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/* CORE_EXPB0, Disable Reset R_CAL/RC_CAL Engine */
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rc = bcm_phy_write_exp(phydev, MII_BRCM_CORE_EXPB0, 0x00);
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return 0;
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}
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static int bcm_cygnus_config_init(struct phy_device *phydev)
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{
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int reg, rc;
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reg = phy_read(phydev, MII_BCM54XX_ECR);
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if (reg < 0)
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return reg;
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/* Mask interrupts globally. */
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reg |= MII_BCM54XX_ECR_IM;
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rc = phy_write(phydev, MII_BCM54XX_ECR, reg);
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if (rc)
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return rc;
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/* Unmask events of interest */
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reg = ~(MII_BCM54XX_INT_DUPLEX |
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MII_BCM54XX_INT_SPEED |
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MII_BCM54XX_INT_LINK);
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rc = phy_write(phydev, MII_BCM54XX_IMR, reg);
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if (rc)
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return rc;
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/* Apply AFE settings for the PHY */
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rc = bcm_cygnus_afe_config(phydev);
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if (rc)
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return rc;
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/* Advertise EEE */
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rc = bcm_phy_set_eee(phydev, true);
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if (rc)
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return rc;
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/* Enable APD */
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return bcm_phy_enable_apd(phydev, false);
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}
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static int bcm_cygnus_resume(struct phy_device *phydev)
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{
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int rc;
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genphy_resume(phydev);
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/* Re-initialize the PHY to apply AFE work-arounds and
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* configurations when coming out of suspend.
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*/
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rc = bcm_cygnus_config_init(phydev);
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if (rc)
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return rc;
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/* restart auto negotiation with the new settings */
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return genphy_config_aneg(phydev);
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}
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static struct phy_driver bcm_cygnus_phy_driver[] = {
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{
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.phy_id = PHY_ID_BCM_CYGNUS,
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.phy_id_mask = 0xfffffff0,
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.name = "Broadcom Cygnus PHY",
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.features = PHY_GBIT_FEATURES,
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.config_init = bcm_cygnus_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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.ack_interrupt = bcm_phy_ack_intr,
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.config_intr = bcm_phy_config_intr,
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.suspend = genphy_suspend,
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.resume = bcm_cygnus_resume,
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} };
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static struct mdio_device_id __maybe_unused bcm_cygnus_phy_tbl[] = {
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{ PHY_ID_BCM_CYGNUS, 0xfffffff0, },
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, bcm_cygnus_phy_tbl);
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module_phy_driver(bcm_cygnus_phy_driver);
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MODULE_DESCRIPTION("Broadcom Cygnus internal PHY driver");
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Broadcom Corporation");
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