529ed12752
Instead of having individual PHY drivers set the SUPPORTED_Pause and
SUPPORTED_Asym_Pause flags, phylib itself should set those flags,
unless there is a hardware erratum or other special case. During
autonegotiation, the PHYs will determine whether to enable pause
frame support.
Pause frames are a feature that is supported by the MAC. It is the MAC
that generates the frames and that processes them. The PHY can only be
configured to allow them to pass through.
This commit also effectively reverts the recently applied c7a61319
("net: phy: dp83848: Support ethernet pause frames").
So the new process is:
1) Unless the PHY driver overrides it, phylib sets the SUPPORTED_Pause
and SUPPORTED_AsymPause bits in phydev->supported. This indicates that
the PHY supports pause frames.
2) The MAC driver checks phydev->supported before it calls phy_start().
If (SUPPORTED_Pause | SUPPORTED_AsymPause) is set, then the MAC driver
sets those bits in phydev->advertising, if it wants to enable pause
frame support.
3) When the link state changes, the MAC driver checks phydev->pause and
phydev->asym_pause, If the bits are set, then it enables the corresponding
features in the MAC. The algorithm is:
if (phydev->pause)
The MAC should be programmed to receive and honor
pause frames it receives, i.e. enable receive flow control.
if (phydev->pause != phydev->asym_pause)
The MAC should be programmed to transmit pause
frames when needed, i.e. enable transmit flow control.
Signed-off-by: Timur Tabi <timur@codeaurora.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
157 lines
4.1 KiB
C
157 lines
4.1 KiB
C
/*
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* drivers/net/phy/national.c
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*
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* Driver for National Semiconductor PHYs
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*
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* Author: Stuart Menefy <stuart.menefy@st.com>
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* Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*
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* Copyright (c) 2008 STMicroelectronics Limited
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mii.h>
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#include <linux/ethtool.h>
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#include <linux/phy.h>
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#include <linux/netdevice.h>
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#define DEBUG
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/* DP83865 phy identifier values */
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#define DP83865_PHY_ID 0x20005c7a
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#define DP83865_INT_STATUS 0x14
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#define DP83865_INT_MASK 0x15
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#define DP83865_INT_CLEAR 0x17
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#define DP83865_INT_REMOTE_FAULT 0x0008
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#define DP83865_INT_ANE_COMPLETED 0x0010
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#define DP83865_INT_LINK_CHANGE 0xe000
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#define DP83865_INT_MASK_DEFAULT (DP83865_INT_REMOTE_FAULT | \
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DP83865_INT_ANE_COMPLETED | \
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DP83865_INT_LINK_CHANGE)
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/* Advanced proprietary configuration */
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#define NS_EXP_MEM_CTL 0x16
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#define NS_EXP_MEM_DATA 0x1d
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#define NS_EXP_MEM_ADD 0x1e
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#define LED_CTRL_REG 0x13
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#define AN_FALLBACK_AN 0x0001
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#define AN_FALLBACK_CRC 0x0002
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#define AN_FALLBACK_IE 0x0004
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#define ALL_FALLBACK_ON (AN_FALLBACK_AN | AN_FALLBACK_CRC | AN_FALLBACK_IE)
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enum hdx_loopback {
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hdx_loopback_on = 0,
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hdx_loopback_off = 1,
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};
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static u8 ns_exp_read(struct phy_device *phydev, u16 reg)
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{
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phy_write(phydev, NS_EXP_MEM_ADD, reg);
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return phy_read(phydev, NS_EXP_MEM_DATA);
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}
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static void ns_exp_write(struct phy_device *phydev, u16 reg, u8 data)
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{
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phy_write(phydev, NS_EXP_MEM_ADD, reg);
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phy_write(phydev, NS_EXP_MEM_DATA, data);
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}
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static int ns_config_intr(struct phy_device *phydev)
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{
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int err;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
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err = phy_write(phydev, DP83865_INT_MASK,
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DP83865_INT_MASK_DEFAULT);
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else
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err = phy_write(phydev, DP83865_INT_MASK, 0);
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return err;
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}
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static int ns_ack_interrupt(struct phy_device *phydev)
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{
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int ret = phy_read(phydev, DP83865_INT_STATUS);
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if (ret < 0)
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return ret;
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/* Clear the interrupt status bit by writing a “1”
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* to the corresponding bit in INT_CLEAR (2:0 are reserved) */
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ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7);
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return ret;
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}
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static void ns_giga_speed_fallback(struct phy_device *phydev, int mode)
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{
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int bmcr = phy_read(phydev, MII_BMCR);
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phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN));
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/* Enable 8 bit expended memory read/write (no auto increment) */
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phy_write(phydev, NS_EXP_MEM_CTL, 0);
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phy_write(phydev, NS_EXP_MEM_ADD, 0x1C0);
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phy_write(phydev, NS_EXP_MEM_DATA, 0x0008);
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phy_write(phydev, MII_BMCR, (bmcr & ~BMCR_PDOWN));
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phy_write(phydev, LED_CTRL_REG, mode);
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}
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static void ns_10_base_t_hdx_loopack(struct phy_device *phydev, int disable)
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{
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if (disable)
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ns_exp_write(phydev, 0x1c0, ns_exp_read(phydev, 0x1c0) | 1);
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else
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ns_exp_write(phydev, 0x1c0,
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ns_exp_read(phydev, 0x1c0) & 0xfffe);
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pr_debug("10BASE-T HDX loopback %s\n",
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(ns_exp_read(phydev, 0x1c0) & 0x0001) ? "off" : "on");
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}
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static int ns_config_init(struct phy_device *phydev)
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{
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ns_giga_speed_fallback(phydev, ALL_FALLBACK_ON);
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/* In the latest MAC or switches design, the 10 Mbps loopback
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is desired to be turned off. */
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ns_10_base_t_hdx_loopack(phydev, hdx_loopback_off);
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return ns_ack_interrupt(phydev);
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}
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static struct phy_driver dp83865_driver[] = { {
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.phy_id = DP83865_PHY_ID,
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.phy_id_mask = 0xfffffff0,
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.name = "NatSemi DP83865",
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.features = PHY_GBIT_FEATURES,
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.flags = PHY_HAS_INTERRUPT,
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.config_init = ns_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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.ack_interrupt = ns_ack_interrupt,
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.config_intr = ns_config_intr,
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} };
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module_phy_driver(dp83865_driver);
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MODULE_DESCRIPTION("NatSemi PHY driver");
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MODULE_AUTHOR("Stuart Menefy");
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MODULE_LICENSE("GPL");
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static struct mdio_device_id __maybe_unused ns_tbl[] = {
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{ DP83865_PHY_ID, 0xfffffff0 },
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, ns_tbl);
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