![Janusz Krzysztofik](/assets/img/avatar_default.png)
According to comments in omap1_select_table_rate(), reprogramming dpll1 is tricky, and should always be done from SRAM. While being at it, move OMAP730 special case handling inside omap_sram_reprogram_clock(). Created on top of version 2 of the series "ARM: OMAP1: Fix dpll1 reprogramming related issues", which it depends on. Tested on Amstrad Delta. Signed-off-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl> Signed-off-by: Tony Lindgren <tony@atomide.com>
612 lines
14 KiB
C
612 lines
14 KiB
C
/*
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* linux/arch/arm/mach-omap1/clock.c
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*
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* Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
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* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
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*
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* Modified to use omap shared clock framework by
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* Tony Lindgren <tony@atomide.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/clkdev.h>
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#include <asm/mach-types.h>
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#include <plat/cpu.h>
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#include <plat/usb.h>
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#include <plat/clock.h>
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#include <plat/sram.h>
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#include <plat/clkdev_omap.h>
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#include "clock.h"
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#include "opp.h"
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__u32 arm_idlect1_mask;
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struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
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/*
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* Omap1 specific clock functions
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*/
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unsigned long omap1_uart_recalc(struct clk *clk)
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{
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unsigned int val = __raw_readl(clk->enable_reg);
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return val & clk->enable_bit ? 48000000 : 12000000;
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}
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unsigned long omap1_sossi_recalc(struct clk *clk)
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{
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u32 div = omap_readl(MOD_CONF_CTRL_1);
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div = (div >> 17) & 0x7;
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div++;
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return clk->parent->rate / div;
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}
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static void omap1_clk_allow_idle(struct clk *clk)
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{
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struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
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if (!(clk->flags & CLOCK_IDLE_CONTROL))
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return;
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if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count))
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arm_idlect1_mask |= 1 << iclk->idlect_shift;
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}
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static void omap1_clk_deny_idle(struct clk *clk)
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{
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struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
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if (!(clk->flags & CLOCK_IDLE_CONTROL))
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return;
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if (iclk->no_idle_count++ == 0)
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arm_idlect1_mask &= ~(1 << iclk->idlect_shift);
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}
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static __u16 verify_ckctl_value(__u16 newval)
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{
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/* This function checks for following limitations set
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* by the hardware (all conditions must be true):
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* DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
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* ARM_CK >= TC_CK
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* DSP_CK >= TC_CK
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* DSPMMU_CK >= TC_CK
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*
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* In addition following rules are enforced:
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* LCD_CK <= TC_CK
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* ARMPER_CK <= TC_CK
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*
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* However, maximum frequencies are not checked for!
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*/
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__u8 per_exp;
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__u8 lcd_exp;
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__u8 arm_exp;
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__u8 dsp_exp;
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__u8 tc_exp;
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__u8 dspmmu_exp;
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per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
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lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
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arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
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dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
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tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
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dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
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if (dspmmu_exp < dsp_exp)
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dspmmu_exp = dsp_exp;
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if (dspmmu_exp > dsp_exp+1)
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dspmmu_exp = dsp_exp+1;
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if (tc_exp < arm_exp)
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tc_exp = arm_exp;
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if (tc_exp < dspmmu_exp)
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tc_exp = dspmmu_exp;
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if (tc_exp > lcd_exp)
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lcd_exp = tc_exp;
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if (tc_exp > per_exp)
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per_exp = tc_exp;
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newval &= 0xf000;
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newval |= per_exp << CKCTL_PERDIV_OFFSET;
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newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
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newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
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newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
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newval |= tc_exp << CKCTL_TCDIV_OFFSET;
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newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
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return newval;
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}
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static int calc_dsor_exp(struct clk *clk, unsigned long rate)
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{
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/* Note: If target frequency is too low, this function will return 4,
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* which is invalid value. Caller must check for this value and act
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* accordingly.
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*
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* Note: This function does not check for following limitations set
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* by the hardware (all conditions must be true):
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* DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
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* ARM_CK >= TC_CK
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* DSP_CK >= TC_CK
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* DSPMMU_CK >= TC_CK
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*/
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unsigned long realrate;
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struct clk * parent;
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unsigned dsor_exp;
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parent = clk->parent;
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if (unlikely(parent == NULL))
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return -EIO;
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realrate = parent->rate;
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for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
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if (realrate <= rate)
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break;
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realrate /= 2;
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}
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return dsor_exp;
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}
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unsigned long omap1_ckctl_recalc(struct clk *clk)
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{
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/* Calculate divisor encoded as 2-bit exponent */
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int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
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return clk->parent->rate / dsor;
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}
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unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk)
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{
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int dsor;
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/* Calculate divisor encoded as 2-bit exponent
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*
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* The clock control bits are in DSP domain,
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* so api_ck is needed for access.
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* Note that DSP_CKCTL virt addr = phys addr, so
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* we must use __raw_readw() instead of omap_readw().
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*/
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omap1_clk_enable(api_ck_p);
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dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
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omap1_clk_disable(api_ck_p);
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return clk->parent->rate / dsor;
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}
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/* MPU virtual clock functions */
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int omap1_select_table_rate(struct clk *clk, unsigned long rate)
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{
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/* Find the highest supported frequency <= rate and switch to it */
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struct mpu_rate * ptr;
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unsigned long dpll1_rate, ref_rate;
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dpll1_rate = ck_dpll1_p->rate;
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ref_rate = ck_ref_p->rate;
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for (ptr = omap1_rate_table; ptr->rate; ptr++) {
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if (!(ptr->flags & cpu_mask))
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continue;
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if (ptr->xtal != ref_rate)
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continue;
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/* DPLL1 cannot be reprogrammed without risking system crash */
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if (likely(dpll1_rate != 0) && ptr->pll_rate != dpll1_rate)
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continue;
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/* Can check only after xtal frequency check */
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if (ptr->rate <= rate)
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break;
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}
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if (!ptr->rate)
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return -EINVAL;
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/*
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* In most cases we should not need to reprogram DPLL.
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* Reprogramming the DPLL is tricky, it must be done from SRAM.
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*/
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omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
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/* XXX Do we need to recalculate the tree below DPLL1 at this point? */
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ck_dpll1_p->rate = ptr->pll_rate;
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return 0;
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}
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int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
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{
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int dsor_exp;
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u16 regval;
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dsor_exp = calc_dsor_exp(clk, rate);
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if (dsor_exp > 3)
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dsor_exp = -EINVAL;
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if (dsor_exp < 0)
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return dsor_exp;
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regval = __raw_readw(DSP_CKCTL);
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regval &= ~(3 << clk->rate_offset);
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regval |= dsor_exp << clk->rate_offset;
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__raw_writew(regval, DSP_CKCTL);
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clk->rate = clk->parent->rate / (1 << dsor_exp);
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return 0;
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}
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long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
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{
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int dsor_exp = calc_dsor_exp(clk, rate);
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if (dsor_exp < 0)
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return dsor_exp;
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if (dsor_exp > 3)
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dsor_exp = 3;
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return clk->parent->rate / (1 << dsor_exp);
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}
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int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
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{
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int dsor_exp;
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u16 regval;
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dsor_exp = calc_dsor_exp(clk, rate);
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if (dsor_exp > 3)
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dsor_exp = -EINVAL;
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if (dsor_exp < 0)
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return dsor_exp;
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regval = omap_readw(ARM_CKCTL);
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regval &= ~(3 << clk->rate_offset);
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regval |= dsor_exp << clk->rate_offset;
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regval = verify_ckctl_value(regval);
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omap_writew(regval, ARM_CKCTL);
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clk->rate = clk->parent->rate / (1 << dsor_exp);
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return 0;
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}
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long omap1_round_to_table_rate(struct clk *clk, unsigned long rate)
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{
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/* Find the highest supported frequency <= rate */
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struct mpu_rate * ptr;
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long highest_rate;
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unsigned long ref_rate;
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ref_rate = ck_ref_p->rate;
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highest_rate = -EINVAL;
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for (ptr = omap1_rate_table; ptr->rate; ptr++) {
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if (!(ptr->flags & cpu_mask))
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continue;
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if (ptr->xtal != ref_rate)
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continue;
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highest_rate = ptr->rate;
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/* Can check only after xtal frequency check */
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if (ptr->rate <= rate)
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break;
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}
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return highest_rate;
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}
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static unsigned calc_ext_dsor(unsigned long rate)
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{
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unsigned dsor;
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/* MCLK and BCLK divisor selection is not linear:
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* freq = 96MHz / dsor
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*
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* RATIO_SEL range: dsor <-> RATIO_SEL
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* 0..6: (RATIO_SEL+2) <-> (dsor-2)
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* 6..48: (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
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* Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
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* can not be used.
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*/
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for (dsor = 2; dsor < 96; ++dsor) {
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if ((dsor & 1) && dsor > 8)
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continue;
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if (rate >= 96000000 / dsor)
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break;
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}
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return dsor;
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}
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/* XXX Only needed on 1510 */
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int omap1_set_uart_rate(struct clk *clk, unsigned long rate)
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{
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unsigned int val;
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val = __raw_readl(clk->enable_reg);
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if (rate == 12000000)
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val &= ~(1 << clk->enable_bit);
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else if (rate == 48000000)
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val |= (1 << clk->enable_bit);
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else
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return -EINVAL;
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__raw_writel(val, clk->enable_reg);
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clk->rate = rate;
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return 0;
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}
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/* External clock (MCLK & BCLK) functions */
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int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate)
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{
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unsigned dsor;
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__u16 ratio_bits;
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dsor = calc_ext_dsor(rate);
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clk->rate = 96000000 / dsor;
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if (dsor > 8)
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ratio_bits = ((dsor - 8) / 2 + 6) << 2;
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else
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ratio_bits = (dsor - 2) << 2;
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ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd;
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__raw_writew(ratio_bits, clk->enable_reg);
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return 0;
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}
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int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
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{
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u32 l;
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int div;
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unsigned long p_rate;
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p_rate = clk->parent->rate;
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/* Round towards slower frequency */
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div = (p_rate + rate - 1) / rate;
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div--;
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if (div < 0 || div > 7)
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return -EINVAL;
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l = omap_readl(MOD_CONF_CTRL_1);
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l &= ~(7 << 17);
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l |= div << 17;
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omap_writel(l, MOD_CONF_CTRL_1);
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clk->rate = p_rate / (div + 1);
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return 0;
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}
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long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate)
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{
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return 96000000 / calc_ext_dsor(rate);
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}
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void omap1_init_ext_clk(struct clk *clk)
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{
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unsigned dsor;
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__u16 ratio_bits;
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/* Determine current rate and ensure clock is based on 96MHz APLL */
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ratio_bits = __raw_readw(clk->enable_reg) & ~1;
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__raw_writew(ratio_bits, clk->enable_reg);
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ratio_bits = (ratio_bits & 0xfc) >> 2;
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if (ratio_bits > 6)
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dsor = (ratio_bits - 6) * 2 + 8;
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else
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dsor = ratio_bits + 2;
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clk-> rate = 96000000 / dsor;
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}
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int omap1_clk_enable(struct clk *clk)
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{
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int ret = 0;
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if (clk->usecount++ == 0) {
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if (clk->parent) {
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ret = omap1_clk_enable(clk->parent);
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if (ret)
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goto err;
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if (clk->flags & CLOCK_NO_IDLE_PARENT)
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omap1_clk_deny_idle(clk->parent);
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}
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ret = clk->ops->enable(clk);
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if (ret) {
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if (clk->parent)
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omap1_clk_disable(clk->parent);
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goto err;
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}
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}
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return ret;
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err:
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clk->usecount--;
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return ret;
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}
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void omap1_clk_disable(struct clk *clk)
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{
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if (clk->usecount > 0 && !(--clk->usecount)) {
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clk->ops->disable(clk);
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if (likely(clk->parent)) {
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omap1_clk_disable(clk->parent);
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if (clk->flags & CLOCK_NO_IDLE_PARENT)
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omap1_clk_allow_idle(clk->parent);
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}
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}
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}
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static int omap1_clk_enable_generic(struct clk *clk)
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{
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__u16 regval16;
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__u32 regval32;
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if (unlikely(clk->enable_reg == NULL)) {
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printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
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clk->name);
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return -EINVAL;
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}
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if (clk->flags & ENABLE_REG_32BIT) {
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regval32 = __raw_readl(clk->enable_reg);
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regval32 |= (1 << clk->enable_bit);
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__raw_writel(regval32, clk->enable_reg);
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} else {
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regval16 = __raw_readw(clk->enable_reg);
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regval16 |= (1 << clk->enable_bit);
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__raw_writew(regval16, clk->enable_reg);
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}
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return 0;
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}
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static void omap1_clk_disable_generic(struct clk *clk)
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{
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__u16 regval16;
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__u32 regval32;
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if (clk->enable_reg == NULL)
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return;
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if (clk->flags & ENABLE_REG_32BIT) {
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regval32 = __raw_readl(clk->enable_reg);
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regval32 &= ~(1 << clk->enable_bit);
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__raw_writel(regval32, clk->enable_reg);
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} else {
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regval16 = __raw_readw(clk->enable_reg);
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regval16 &= ~(1 << clk->enable_bit);
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__raw_writew(regval16, clk->enable_reg);
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}
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}
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const struct clkops clkops_generic = {
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.enable = omap1_clk_enable_generic,
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.disable = omap1_clk_disable_generic,
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};
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static int omap1_clk_enable_dsp_domain(struct clk *clk)
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{
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int retval;
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retval = omap1_clk_enable(api_ck_p);
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if (!retval) {
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retval = omap1_clk_enable_generic(clk);
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omap1_clk_disable(api_ck_p);
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}
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return retval;
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}
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static void omap1_clk_disable_dsp_domain(struct clk *clk)
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{
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if (omap1_clk_enable(api_ck_p) == 0) {
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omap1_clk_disable_generic(clk);
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omap1_clk_disable(api_ck_p);
|
|
}
|
|
}
|
|
|
|
const struct clkops clkops_dspck = {
|
|
.enable = omap1_clk_enable_dsp_domain,
|
|
.disable = omap1_clk_disable_dsp_domain,
|
|
};
|
|
|
|
/* XXX SYSC register handling does not belong in the clock framework */
|
|
static int omap1_clk_enable_uart_functional_16xx(struct clk *clk)
|
|
{
|
|
int ret;
|
|
struct uart_clk *uclk;
|
|
|
|
ret = omap1_clk_enable_generic(clk);
|
|
if (ret == 0) {
|
|
/* Set smart idle acknowledgement mode */
|
|
uclk = (struct uart_clk *)clk;
|
|
omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
|
|
uclk->sysc_addr);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* XXX SYSC register handling does not belong in the clock framework */
|
|
static void omap1_clk_disable_uart_functional_16xx(struct clk *clk)
|
|
{
|
|
struct uart_clk *uclk;
|
|
|
|
/* Set force idle acknowledgement mode */
|
|
uclk = (struct uart_clk *)clk;
|
|
omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
|
|
|
|
omap1_clk_disable_generic(clk);
|
|
}
|
|
|
|
/* XXX SYSC register handling does not belong in the clock framework */
|
|
const struct clkops clkops_uart_16xx = {
|
|
.enable = omap1_clk_enable_uart_functional_16xx,
|
|
.disable = omap1_clk_disable_uart_functional_16xx,
|
|
};
|
|
|
|
long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
if (clk->round_rate != NULL)
|
|
return clk->round_rate(clk, rate);
|
|
|
|
return clk->rate;
|
|
}
|
|
|
|
int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
int ret = -EINVAL;
|
|
|
|
if (clk->set_rate)
|
|
ret = clk->set_rate(clk, rate);
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Omap1 clock reset and init functions
|
|
*/
|
|
|
|
#ifdef CONFIG_OMAP_RESET_CLOCKS
|
|
|
|
void omap1_clk_disable_unused(struct clk *clk)
|
|
{
|
|
__u32 regval32;
|
|
|
|
/* Clocks in the DSP domain need api_ck. Just assume bootloader
|
|
* has not enabled any DSP clocks */
|
|
if (clk->enable_reg == DSP_IDLECT2) {
|
|
printk(KERN_INFO "Skipping reset check for DSP domain "
|
|
"clock \"%s\"\n", clk->name);
|
|
return;
|
|
}
|
|
|
|
/* Is the clock already disabled? */
|
|
if (clk->flags & ENABLE_REG_32BIT)
|
|
regval32 = __raw_readl(clk->enable_reg);
|
|
else
|
|
regval32 = __raw_readw(clk->enable_reg);
|
|
|
|
if ((regval32 & (1 << clk->enable_bit)) == 0)
|
|
return;
|
|
|
|
printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
|
|
clk->ops->disable(clk);
|
|
printk(" done\n");
|
|
}
|
|
|
|
#endif
|