d457ef358f
This supports power-gated idle on secondary CPUs for Tegra30. The secondary CPUs can go into powered-down state independently. When CPU goes into this state, it saves it's contexts and puts itself to flow controlled WFI state. After that, it will been power gated. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
41 lines
1.5 KiB
Makefile
41 lines
1.5 KiB
Makefile
obj-y += common.o
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obj-y += io.o
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obj-y += irq.o
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obj-y += clock.o
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obj-y += timer.o
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obj-y += fuse.o
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obj-y += pmc.o
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obj-y += flowctrl.o
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obj-y += powergate.o
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obj-y += apbio.o
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obj-y += pm.o
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obj-$(CONFIG_CPU_IDLE) += cpuidle.o
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obj-$(CONFIG_CPU_IDLE) += sleep.o
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks.o
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks_data.o
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_speedo.o
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-tegra20.o
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ifeq ($(CONFIG_CPU_IDLE),y)
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += cpuidle-tegra20.o
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endif
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obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
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obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks_data.o
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obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_speedo.o
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obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-tegra30.o
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ifeq ($(CONFIG_CPU_IDLE),y)
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obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o
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endif
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obj-$(CONFIG_SMP) += platsmp.o headsmp.o
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obj-$(CONFIG_SMP) += reset.o
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obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
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obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o
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obj-$(CONFIG_TEGRA_PCI) += pcie.o
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-dt-tegra20.o
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obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-harmony-pcie.o
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o
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