![Thomas Abraham](/assets/img/avatar_default.png)
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
197 lines
4.3 KiB
C
197 lines
4.3 KiB
C
/* linux/arch/arm/plat-s3c24xx/clock-dclk.c
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*
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* Copyright (c) 2004-2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* S3C24XX - definitions for DCLK and CLKOUT registers
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <mach/regs-clock.h>
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#include <mach/regs-gpio.h>
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#include <plat/clock.h>
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#include <plat/cpu.h>
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/* clocks that could be registered by external code */
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static int s3c24xx_dclk_enable(struct clk *clk, int enable)
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{
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unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON);
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if (enable)
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dclkcon |= clk->ctrlbit;
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else
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dclkcon &= ~clk->ctrlbit;
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__raw_writel(dclkcon, S3C24XX_DCLKCON);
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return 0;
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}
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static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
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{
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unsigned long dclkcon;
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unsigned int uclk;
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if (parent == &clk_upll)
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uclk = 1;
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else if (parent == &clk_p)
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uclk = 0;
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else
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return -EINVAL;
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clk->parent = parent;
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dclkcon = __raw_readl(S3C24XX_DCLKCON);
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if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
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if (uclk)
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dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;
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else
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dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK;
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} else {
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if (uclk)
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dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;
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else
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dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK;
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}
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__raw_writel(dclkcon, S3C24XX_DCLKCON);
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return 0;
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}
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static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate)
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{
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unsigned long div;
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if ((rate == 0) || !clk->parent)
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return 0;
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div = clk_get_rate(clk->parent) / rate;
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if (div < 2)
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div = 2;
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else if (div > 16)
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div = 16;
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return div;
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}
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static unsigned long s3c24xx_round_dclk_rate(struct clk *clk,
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unsigned long rate)
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{
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unsigned long div = s3c24xx_calc_div(clk, rate);
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if (div == 0)
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return 0;
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return clk_get_rate(clk->parent) / div;
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}
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static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long mask, data, div = s3c24xx_calc_div(clk, rate);
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if (div == 0)
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return -EINVAL;
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if (clk == &s3c24xx_dclk0) {
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mask = S3C2410_DCLKCON_DCLK0_DIV_MASK |
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S3C2410_DCLKCON_DCLK0_CMP_MASK;
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data = S3C2410_DCLKCON_DCLK0_DIV(div) |
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S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2);
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} else if (clk == &s3c24xx_dclk1) {
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mask = S3C2410_DCLKCON_DCLK1_DIV_MASK |
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S3C2410_DCLKCON_DCLK1_CMP_MASK;
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data = S3C2410_DCLKCON_DCLK1_DIV(div) |
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S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2);
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} else
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return -EINVAL;
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clk->rate = clk_get_rate(clk->parent) / div;
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__raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data),
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S3C24XX_DCLKCON);
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return clk->rate;
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}
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static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
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{
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unsigned long mask;
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unsigned long source;
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/* calculate the MISCCR setting for the clock */
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if (parent == &clk_mpll)
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source = S3C2410_MISCCR_CLK0_MPLL;
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else if (parent == &clk_upll)
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source = S3C2410_MISCCR_CLK0_UPLL;
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else if (parent == &clk_f)
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source = S3C2410_MISCCR_CLK0_FCLK;
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else if (parent == &clk_h)
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source = S3C2410_MISCCR_CLK0_HCLK;
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else if (parent == &clk_p)
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source = S3C2410_MISCCR_CLK0_PCLK;
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else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0)
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source = S3C2410_MISCCR_CLK0_DCLK0;
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else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1)
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source = S3C2410_MISCCR_CLK0_DCLK0;
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else
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return -EINVAL;
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clk->parent = parent;
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if (clk == &s3c24xx_clkout0)
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mask = S3C2410_MISCCR_CLK0_MASK;
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else {
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source <<= 4;
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mask = S3C2410_MISCCR_CLK1_MASK;
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}
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s3c2410_modify_misccr(mask, source);
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return 0;
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}
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/* external clock definitions */
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static struct clk_ops dclk_ops = {
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.set_parent = s3c24xx_dclk_setparent,
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.set_rate = s3c24xx_set_dclk_rate,
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.round_rate = s3c24xx_round_dclk_rate,
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};
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struct clk s3c24xx_dclk0 = {
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.name = "dclk0",
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.ctrlbit = S3C2410_DCLKCON_DCLK0EN,
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.enable = s3c24xx_dclk_enable,
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.ops = &dclk_ops,
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};
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struct clk s3c24xx_dclk1 = {
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.name = "dclk1",
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.ctrlbit = S3C2410_DCLKCON_DCLK1EN,
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.enable = s3c24xx_dclk_enable,
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.ops = &dclk_ops,
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};
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static struct clk_ops clkout_ops = {
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.set_parent = s3c24xx_clkout_setparent,
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};
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struct clk s3c24xx_clkout0 = {
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.name = "clkout0",
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.ops = &clkout_ops,
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};
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struct clk s3c24xx_clkout1 = {
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.name = "clkout1",
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.ops = &clkout_ops,
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};
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