e1f34e4f27
PCIE and NSS has MISC reset register in which single register has multiple reset bit. The patch adds the DT bindings for these MISC resets. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
375 lines
12 KiB
C
375 lines
12 KiB
C
/*
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* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H
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#define _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H
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#define GPLL0 0
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#define GPLL0_MAIN 1
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#define GCC_SLEEP_CLK_SRC 2
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#define BLSP1_QUP1_I2C_APPS_CLK_SRC 3
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#define BLSP1_QUP1_SPI_APPS_CLK_SRC 4
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#define BLSP1_QUP2_I2C_APPS_CLK_SRC 5
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#define BLSP1_QUP2_SPI_APPS_CLK_SRC 6
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#define BLSP1_QUP3_I2C_APPS_CLK_SRC 7
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#define BLSP1_QUP3_SPI_APPS_CLK_SRC 8
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#define BLSP1_QUP4_I2C_APPS_CLK_SRC 9
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#define BLSP1_QUP4_SPI_APPS_CLK_SRC 10
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#define BLSP1_QUP5_I2C_APPS_CLK_SRC 11
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#define BLSP1_QUP5_SPI_APPS_CLK_SRC 12
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#define BLSP1_QUP6_I2C_APPS_CLK_SRC 13
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#define BLSP1_QUP6_SPI_APPS_CLK_SRC 14
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#define BLSP1_UART1_APPS_CLK_SRC 15
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#define BLSP1_UART2_APPS_CLK_SRC 16
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#define BLSP1_UART3_APPS_CLK_SRC 17
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#define BLSP1_UART4_APPS_CLK_SRC 18
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#define BLSP1_UART5_APPS_CLK_SRC 19
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#define BLSP1_UART6_APPS_CLK_SRC 20
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#define GCC_BLSP1_AHB_CLK 21
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#define GCC_BLSP1_QUP1_I2C_APPS_CLK 22
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#define GCC_BLSP1_QUP1_SPI_APPS_CLK 23
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#define GCC_BLSP1_QUP2_I2C_APPS_CLK 24
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#define GCC_BLSP1_QUP2_SPI_APPS_CLK 25
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#define GCC_BLSP1_QUP3_I2C_APPS_CLK 26
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#define GCC_BLSP1_QUP3_SPI_APPS_CLK 27
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#define GCC_BLSP1_QUP4_I2C_APPS_CLK 28
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#define GCC_BLSP1_QUP4_SPI_APPS_CLK 29
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#define GCC_BLSP1_QUP5_I2C_APPS_CLK 30
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#define GCC_BLSP1_QUP5_SPI_APPS_CLK 31
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#define GCC_BLSP1_QUP6_I2C_APPS_CLK 32
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#define GCC_BLSP1_QUP6_SPI_APPS_CLK 33
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#define GCC_BLSP1_UART1_APPS_CLK 34
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#define GCC_BLSP1_UART2_APPS_CLK 35
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#define GCC_BLSP1_UART3_APPS_CLK 36
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#define GCC_BLSP1_UART4_APPS_CLK 37
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#define GCC_BLSP1_UART5_APPS_CLK 38
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#define GCC_BLSP1_UART6_APPS_CLK 39
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#define GCC_PRNG_AHB_CLK 40
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#define GCC_QPIC_AHB_CLK 41
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#define GCC_QPIC_CLK 42
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#define PCNOC_BFDCD_CLK_SRC 43
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#define GPLL2_MAIN 44
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#define GPLL2 45
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#define GPLL4_MAIN 46
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#define GPLL4 47
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#define GPLL6_MAIN 48
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#define GPLL6 49
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#define UBI32_PLL_MAIN 50
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#define UBI32_PLL 51
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#define NSS_CRYPTO_PLL_MAIN 52
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#define NSS_CRYPTO_PLL 53
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#define PCIE0_AXI_CLK_SRC 54
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#define PCIE0_AUX_CLK_SRC 55
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#define PCIE0_PIPE_CLK_SRC 56
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#define PCIE1_AXI_CLK_SRC 57
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#define PCIE1_AUX_CLK_SRC 58
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#define PCIE1_PIPE_CLK_SRC 59
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#define SDCC1_APPS_CLK_SRC 60
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#define SDCC1_ICE_CORE_CLK_SRC 61
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#define SDCC2_APPS_CLK_SRC 62
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#define USB0_MASTER_CLK_SRC 63
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#define USB0_AUX_CLK_SRC 64
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#define USB0_MOCK_UTMI_CLK_SRC 65
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#define USB0_PIPE_CLK_SRC 66
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#define USB1_MASTER_CLK_SRC 67
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#define USB1_AUX_CLK_SRC 68
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#define USB1_MOCK_UTMI_CLK_SRC 69
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#define USB1_PIPE_CLK_SRC 70
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#define GCC_XO_CLK_SRC 71
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#define SYSTEM_NOC_BFDCD_CLK_SRC 72
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#define NSS_CE_CLK_SRC 73
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#define NSS_NOC_BFDCD_CLK_SRC 74
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#define NSS_CRYPTO_CLK_SRC 75
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#define NSS_UBI0_CLK_SRC 76
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#define NSS_UBI0_DIV_CLK_SRC 77
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#define NSS_UBI1_CLK_SRC 78
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#define NSS_UBI1_DIV_CLK_SRC 79
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#define UBI_MPT_CLK_SRC 80
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#define NSS_IMEM_CLK_SRC 81
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#define NSS_PPE_CLK_SRC 82
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#define NSS_PORT1_RX_CLK_SRC 83
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#define NSS_PORT1_RX_DIV_CLK_SRC 84
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#define NSS_PORT1_TX_CLK_SRC 85
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#define NSS_PORT1_TX_DIV_CLK_SRC 86
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#define NSS_PORT2_RX_CLK_SRC 87
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#define NSS_PORT2_RX_DIV_CLK_SRC 88
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#define NSS_PORT2_TX_CLK_SRC 89
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#define NSS_PORT2_TX_DIV_CLK_SRC 90
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#define NSS_PORT3_RX_CLK_SRC 91
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#define NSS_PORT3_RX_DIV_CLK_SRC 92
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#define NSS_PORT3_TX_CLK_SRC 93
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#define NSS_PORT3_TX_DIV_CLK_SRC 94
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#define NSS_PORT4_RX_CLK_SRC 95
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#define NSS_PORT4_RX_DIV_CLK_SRC 96
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#define NSS_PORT4_TX_CLK_SRC 97
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#define NSS_PORT4_TX_DIV_CLK_SRC 98
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#define NSS_PORT5_RX_CLK_SRC 99
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#define NSS_PORT5_RX_DIV_CLK_SRC 100
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#define NSS_PORT5_TX_CLK_SRC 101
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#define NSS_PORT5_TX_DIV_CLK_SRC 102
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#define NSS_PORT6_RX_CLK_SRC 103
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#define NSS_PORT6_RX_DIV_CLK_SRC 104
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#define NSS_PORT6_TX_CLK_SRC 105
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#define NSS_PORT6_TX_DIV_CLK_SRC 106
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#define CRYPTO_CLK_SRC 107
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#define GP1_CLK_SRC 108
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#define GP2_CLK_SRC 109
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#define GP3_CLK_SRC 110
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#define GCC_PCIE0_AHB_CLK 111
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#define GCC_PCIE0_AUX_CLK 112
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#define GCC_PCIE0_AXI_M_CLK 113
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#define GCC_PCIE0_AXI_S_CLK 114
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#define GCC_PCIE0_PIPE_CLK 115
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#define GCC_SYS_NOC_PCIE0_AXI_CLK 116
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#define GCC_PCIE1_AHB_CLK 117
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#define GCC_PCIE1_AUX_CLK 118
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#define GCC_PCIE1_AXI_M_CLK 119
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#define GCC_PCIE1_AXI_S_CLK 120
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#define GCC_PCIE1_PIPE_CLK 121
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#define GCC_SYS_NOC_PCIE1_AXI_CLK 122
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#define GCC_USB0_AUX_CLK 123
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#define GCC_SYS_NOC_USB0_AXI_CLK 124
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#define GCC_USB0_MASTER_CLK 125
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#define GCC_USB0_MOCK_UTMI_CLK 126
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#define GCC_USB0_PHY_CFG_AHB_CLK 127
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#define GCC_USB0_PIPE_CLK 128
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#define GCC_USB0_SLEEP_CLK 129
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#define GCC_USB1_AUX_CLK 130
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#define GCC_SYS_NOC_USB1_AXI_CLK 131
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#define GCC_USB1_MASTER_CLK 132
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#define GCC_USB1_MOCK_UTMI_CLK 133
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#define GCC_USB1_PHY_CFG_AHB_CLK 134
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#define GCC_USB1_PIPE_CLK 135
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#define GCC_USB1_SLEEP_CLK 136
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#define GCC_SDCC1_AHB_CLK 137
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#define GCC_SDCC1_APPS_CLK 138
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#define GCC_SDCC1_ICE_CORE_CLK 139
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#define GCC_SDCC2_AHB_CLK 140
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#define GCC_SDCC2_APPS_CLK 141
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#define GCC_MEM_NOC_NSS_AXI_CLK 142
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#define GCC_NSS_CE_APB_CLK 143
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#define GCC_NSS_CE_AXI_CLK 144
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#define GCC_NSS_CFG_CLK 145
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#define GCC_NSS_CRYPTO_CLK 146
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#define GCC_NSS_CSR_CLK 147
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#define GCC_NSS_EDMA_CFG_CLK 148
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#define GCC_NSS_EDMA_CLK 149
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#define GCC_NSS_IMEM_CLK 150
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#define GCC_NSS_NOC_CLK 151
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#define GCC_NSS_PPE_BTQ_CLK 152
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#define GCC_NSS_PPE_CFG_CLK 153
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#define GCC_NSS_PPE_CLK 154
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#define GCC_NSS_PPE_IPE_CLK 155
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#define GCC_NSS_PTP_REF_CLK 156
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#define GCC_NSSNOC_CE_APB_CLK 157
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#define GCC_NSSNOC_CE_AXI_CLK 158
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#define GCC_NSSNOC_CRYPTO_CLK 159
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#define GCC_NSSNOC_PPE_CFG_CLK 160
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#define GCC_NSSNOC_PPE_CLK 161
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#define GCC_NSSNOC_QOSGEN_REF_CLK 162
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#define GCC_NSSNOC_SNOC_CLK 163
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#define GCC_NSSNOC_TIMEOUT_REF_CLK 164
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#define GCC_NSSNOC_UBI0_AHB_CLK 165
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#define GCC_NSSNOC_UBI1_AHB_CLK 166
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#define GCC_UBI0_AHB_CLK 167
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#define GCC_UBI0_AXI_CLK 168
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#define GCC_UBI0_NC_AXI_CLK 169
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#define GCC_UBI0_CORE_CLK 170
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#define GCC_UBI0_MPT_CLK 171
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#define GCC_UBI1_AHB_CLK 172
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#define GCC_UBI1_AXI_CLK 173
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#define GCC_UBI1_NC_AXI_CLK 174
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#define GCC_UBI1_CORE_CLK 175
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#define GCC_UBI1_MPT_CLK 176
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#define GCC_CMN_12GPLL_AHB_CLK 177
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#define GCC_CMN_12GPLL_SYS_CLK 178
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#define GCC_MDIO_AHB_CLK 179
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#define GCC_UNIPHY0_AHB_CLK 180
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#define GCC_UNIPHY0_SYS_CLK 181
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#define GCC_UNIPHY1_AHB_CLK 182
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#define GCC_UNIPHY1_SYS_CLK 183
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#define GCC_UNIPHY2_AHB_CLK 184
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#define GCC_UNIPHY2_SYS_CLK 185
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#define GCC_NSS_PORT1_RX_CLK 186
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#define GCC_NSS_PORT1_TX_CLK 187
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#define GCC_NSS_PORT2_RX_CLK 188
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#define GCC_NSS_PORT2_TX_CLK 189
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#define GCC_NSS_PORT3_RX_CLK 190
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#define GCC_NSS_PORT3_TX_CLK 191
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#define GCC_NSS_PORT4_RX_CLK 192
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#define GCC_NSS_PORT4_TX_CLK 193
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#define GCC_NSS_PORT5_RX_CLK 194
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#define GCC_NSS_PORT5_TX_CLK 195
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#define GCC_NSS_PORT6_RX_CLK 196
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#define GCC_NSS_PORT6_TX_CLK 197
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#define GCC_PORT1_MAC_CLK 198
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#define GCC_PORT2_MAC_CLK 199
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#define GCC_PORT3_MAC_CLK 200
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#define GCC_PORT4_MAC_CLK 201
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#define GCC_PORT5_MAC_CLK 202
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#define GCC_PORT6_MAC_CLK 203
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#define GCC_UNIPHY0_PORT1_RX_CLK 204
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#define GCC_UNIPHY0_PORT1_TX_CLK 205
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#define GCC_UNIPHY0_PORT2_RX_CLK 206
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#define GCC_UNIPHY0_PORT2_TX_CLK 207
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#define GCC_UNIPHY0_PORT3_RX_CLK 208
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#define GCC_UNIPHY0_PORT3_TX_CLK 209
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#define GCC_UNIPHY0_PORT4_RX_CLK 210
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#define GCC_UNIPHY0_PORT4_TX_CLK 211
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#define GCC_UNIPHY0_PORT5_RX_CLK 212
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#define GCC_UNIPHY0_PORT5_TX_CLK 213
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#define GCC_UNIPHY1_PORT5_RX_CLK 214
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#define GCC_UNIPHY1_PORT5_TX_CLK 215
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#define GCC_UNIPHY2_PORT6_RX_CLK 216
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#define GCC_UNIPHY2_PORT6_TX_CLK 217
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#define GCC_CRYPTO_AHB_CLK 218
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#define GCC_CRYPTO_AXI_CLK 219
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#define GCC_CRYPTO_CLK 220
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#define GCC_GP1_CLK 221
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#define GCC_GP2_CLK 222
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#define GCC_GP3_CLK 223
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#define GCC_BLSP1_BCR 0
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#define GCC_BLSP1_QUP1_BCR 1
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#define GCC_BLSP1_UART1_BCR 2
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#define GCC_BLSP1_QUP2_BCR 3
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#define GCC_BLSP1_UART2_BCR 4
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#define GCC_BLSP1_QUP3_BCR 5
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#define GCC_BLSP1_UART3_BCR 6
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#define GCC_BLSP1_QUP4_BCR 7
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#define GCC_BLSP1_UART4_BCR 8
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#define GCC_BLSP1_QUP5_BCR 9
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#define GCC_BLSP1_UART5_BCR 10
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#define GCC_BLSP1_QUP6_BCR 11
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#define GCC_BLSP1_UART6_BCR 12
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#define GCC_IMEM_BCR 13
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#define GCC_SMMU_BCR 14
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#define GCC_APSS_TCU_BCR 15
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#define GCC_SMMU_XPU_BCR 16
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#define GCC_PCNOC_TBU_BCR 17
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#define GCC_SMMU_CFG_BCR 18
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#define GCC_PRNG_BCR 19
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#define GCC_BOOT_ROM_BCR 20
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#define GCC_CRYPTO_BCR 21
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#define GCC_WCSS_BCR 22
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#define GCC_WCSS_Q6_BCR 23
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#define GCC_NSS_BCR 24
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#define GCC_SEC_CTRL_BCR 25
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#define GCC_ADSS_BCR 26
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#define GCC_DDRSS_BCR 27
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#define GCC_SYSTEM_NOC_BCR 28
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#define GCC_PCNOC_BCR 29
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#define GCC_TCSR_BCR 30
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#define GCC_QDSS_BCR 31
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#define GCC_DCD_BCR 32
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#define GCC_MSG_RAM_BCR 33
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#define GCC_MPM_BCR 34
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#define GCC_SPMI_BCR 35
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#define GCC_SPDM_BCR 36
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#define GCC_RBCPR_BCR 37
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#define GCC_RBCPR_MX_BCR 38
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#define GCC_TLMM_BCR 39
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#define GCC_RBCPR_WCSS_BCR 40
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#define GCC_USB0_PHY_BCR 41
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#define GCC_USB3PHY_0_PHY_BCR 42
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#define GCC_USB0_BCR 43
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#define GCC_USB1_PHY_BCR 44
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#define GCC_USB3PHY_1_PHY_BCR 45
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#define GCC_USB1_BCR 46
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#define GCC_QUSB2_0_PHY_BCR 47
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#define GCC_QUSB2_1_PHY_BCR 48
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#define GCC_SDCC1_BCR 49
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#define GCC_SDCC2_BCR 50
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#define GCC_SNOC_BUS_TIMEOUT0_BCR 51
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#define GCC_SNOC_BUS_TIMEOUT2_BCR 52
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#define GCC_SNOC_BUS_TIMEOUT3_BCR 53
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#define GCC_PCNOC_BUS_TIMEOUT0_BCR 54
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#define GCC_PCNOC_BUS_TIMEOUT1_BCR 55
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#define GCC_PCNOC_BUS_TIMEOUT2_BCR 56
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#define GCC_PCNOC_BUS_TIMEOUT3_BCR 57
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#define GCC_PCNOC_BUS_TIMEOUT4_BCR 58
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#define GCC_PCNOC_BUS_TIMEOUT5_BCR 59
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#define GCC_PCNOC_BUS_TIMEOUT6_BCR 60
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#define GCC_PCNOC_BUS_TIMEOUT7_BCR 61
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#define GCC_PCNOC_BUS_TIMEOUT8_BCR 62
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#define GCC_PCNOC_BUS_TIMEOUT9_BCR 63
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#define GCC_UNIPHY0_BCR 64
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#define GCC_UNIPHY1_BCR 65
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#define GCC_UNIPHY2_BCR 66
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#define GCC_CMN_12GPLL_BCR 67
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#define GCC_QPIC_BCR 68
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#define GCC_MDIO_BCR 69
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#define GCC_PCIE1_TBU_BCR 70
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#define GCC_WCSS_CORE_TBU_BCR 71
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#define GCC_WCSS_Q6_TBU_BCR 72
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#define GCC_USB0_TBU_BCR 73
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#define GCC_USB1_TBU_BCR 74
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#define GCC_PCIE0_TBU_BCR 75
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#define GCC_NSS_NOC_TBU_BCR 76
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#define GCC_PCIE0_BCR 77
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#define GCC_PCIE0_PHY_BCR 78
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#define GCC_PCIE0PHY_PHY_BCR 79
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#define GCC_PCIE0_LINK_DOWN_BCR 80
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#define GCC_PCIE1_BCR 81
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#define GCC_PCIE1_PHY_BCR 82
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#define GCC_PCIE1PHY_PHY_BCR 83
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#define GCC_PCIE1_LINK_DOWN_BCR 84
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#define GCC_DCC_BCR 85
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#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 86
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#define GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR 87
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#define GCC_SMMU_CATS_BCR 88
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#define GCC_UBI0_AXI_ARES 89
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#define GCC_UBI0_AHB_ARES 90
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#define GCC_UBI0_NC_AXI_ARES 91
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#define GCC_UBI0_DBG_ARES 92
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#define GCC_UBI0_CORE_CLAMP_ENABLE 93
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#define GCC_UBI0_CLKRST_CLAMP_ENABLE 94
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#define GCC_UBI1_AXI_ARES 95
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#define GCC_UBI1_AHB_ARES 96
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#define GCC_UBI1_NC_AXI_ARES 97
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#define GCC_UBI1_DBG_ARES 98
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#define GCC_UBI1_CORE_CLAMP_ENABLE 99
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#define GCC_UBI1_CLKRST_CLAMP_ENABLE 100
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#define GCC_NSS_CFG_ARES 101
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#define GCC_NSS_IMEM_ARES 102
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#define GCC_NSS_NOC_ARES 103
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#define GCC_NSS_CRYPTO_ARES 104
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#define GCC_NSS_CSR_ARES 105
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#define GCC_NSS_CE_APB_ARES 106
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#define GCC_NSS_CE_AXI_ARES 107
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#define GCC_NSSNOC_CE_APB_ARES 108
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#define GCC_NSSNOC_CE_AXI_ARES 109
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#define GCC_NSSNOC_UBI0_AHB_ARES 110
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#define GCC_NSSNOC_UBI1_AHB_ARES 111
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#define GCC_NSSNOC_SNOC_ARES 112
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#define GCC_NSSNOC_CRYPTO_ARES 113
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#define GCC_NSSNOC_ATB_ARES 114
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#define GCC_NSSNOC_QOSGEN_REF_ARES 115
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#define GCC_NSSNOC_TIMEOUT_REF_ARES 116
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#define GCC_PCIE0_PIPE_ARES 117
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#define GCC_PCIE0_SLEEP_ARES 118
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#define GCC_PCIE0_CORE_STICKY_ARES 119
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#define GCC_PCIE0_AXI_MASTER_ARES 120
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#define GCC_PCIE0_AXI_SLAVE_ARES 121
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#define GCC_PCIE0_AHB_ARES 122
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#define GCC_PCIE0_AXI_MASTER_STICKY_ARES 123
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#define GCC_PCIE1_PIPE_ARES 124
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#define GCC_PCIE1_SLEEP_ARES 125
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#define GCC_PCIE1_CORE_STICKY_ARES 126
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#define GCC_PCIE1_AXI_MASTER_ARES 127
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#define GCC_PCIE1_AXI_SLAVE_ARES 128
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#define GCC_PCIE1_AHB_ARES 129
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#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
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#endif
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