6f1ed07a14
Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Only include clk.h in files that are using it. The clkdev.h header isn't always used either, so remove it and add in slab.h where files were relying on it to include slab for them. Cc: Chanwoo Choi <cw00.choi@samsung.com> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
304 lines
9.3 KiB
C
304 lines
9.3 KiB
C
/*
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* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Common Clock Framework support for S3C2412 and S3C2413.
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*/
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/syscore_ops.h>
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#include <linux/reboot.h>
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#include <dt-bindings/clock/s3c2412.h>
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#include "clk.h"
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#include "clk-pll.h"
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#define LOCKTIME 0x00
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#define MPLLCON 0x04
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#define UPLLCON 0x08
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#define CLKCON 0x0c
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#define CLKDIVN 0x14
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#define CLKSRC 0x1c
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#define SWRST 0x30
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/* list of PLLs to be registered */
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enum s3c2412_plls {
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mpll, upll,
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};
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static void __iomem *reg_base;
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#ifdef CONFIG_PM_SLEEP
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static struct samsung_clk_reg_dump *s3c2412_save;
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/*
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* list of controller registers to be saved and restored during a
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* suspend/resume cycle.
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*/
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static unsigned long s3c2412_clk_regs[] __initdata = {
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LOCKTIME,
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MPLLCON,
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UPLLCON,
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CLKCON,
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CLKDIVN,
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CLKSRC,
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};
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static int s3c2412_clk_suspend(void)
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{
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samsung_clk_save(reg_base, s3c2412_save,
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ARRAY_SIZE(s3c2412_clk_regs));
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return 0;
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}
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static void s3c2412_clk_resume(void)
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{
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samsung_clk_restore(reg_base, s3c2412_save,
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ARRAY_SIZE(s3c2412_clk_regs));
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}
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static struct syscore_ops s3c2412_clk_syscore_ops = {
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.suspend = s3c2412_clk_suspend,
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.resume = s3c2412_clk_resume,
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};
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static void s3c2412_clk_sleep_init(void)
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{
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s3c2412_save = samsung_clk_alloc_reg_dump(s3c2412_clk_regs,
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ARRAY_SIZE(s3c2412_clk_regs));
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if (!s3c2412_save) {
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pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
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__func__);
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return;
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}
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register_syscore_ops(&s3c2412_clk_syscore_ops);
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return;
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}
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#else
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static void s3c2412_clk_sleep_init(void) {}
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#endif
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static struct clk_div_table divxti_d[] = {
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{ .val = 0, .div = 1 },
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{ .val = 1, .div = 2 },
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{ .val = 2, .div = 4 },
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{ .val = 3, .div = 6 },
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{ .val = 4, .div = 8 },
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{ .val = 5, .div = 10 },
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{ .val = 6, .div = 12 },
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{ .val = 7, .div = 14 },
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{ /* sentinel */ },
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};
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struct samsung_div_clock s3c2412_dividers[] __initdata = {
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DIV_T(0, "div_xti", "xti", CLKSRC, 0, 3, divxti_d),
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DIV(0, "div_cam", "mux_cam", CLKDIVN, 16, 4),
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DIV(0, "div_i2s", "mux_i2s", CLKDIVN, 12, 4),
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DIV(0, "div_uart", "mux_uart", CLKDIVN, 8, 4),
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DIV(0, "div_usb", "mux_usb", CLKDIVN, 6, 1),
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DIV(0, "div_hclk_half", "hclk", CLKDIVN, 5, 1),
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DIV(ARMDIV, "armdiv", "msysclk", CLKDIVN, 3, 1),
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DIV(PCLK, "pclk", "hclk", CLKDIVN, 2, 1),
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DIV(HCLK, "hclk", "armdiv", CLKDIVN, 0, 2),
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};
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struct samsung_fixed_factor_clock s3c2412_ffactor[] __initdata = {
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FFACTOR(0, "ff_hclk", "hclk", 2, 1, CLK_SET_RATE_PARENT),
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};
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/*
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* The first two use the OM[4] setting, which is not readable from
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* software, so assume it is set to xti.
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*/
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PNAME(erefclk_p) = { "xti", "xti", "xti", "ext" };
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PNAME(urefclk_p) = { "xti", "xti", "xti", "ext" };
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PNAME(camclk_p) = { "usysclk", "hclk" };
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PNAME(usbclk_p) = { "usysclk", "hclk" };
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PNAME(i2sclk_p) = { "erefclk", "mpll" };
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PNAME(uartclk_p) = { "erefclk", "mpll" };
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PNAME(usysclk_p) = { "urefclk", "upll" };
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PNAME(msysclk_p) = { "mdivclk", "mpll" };
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PNAME(mdivclk_p) = { "xti", "div_xti" };
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PNAME(armclk_p) = { "armdiv", "hclk" };
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struct samsung_mux_clock s3c2412_muxes[] __initdata = {
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MUX(0, "erefclk", erefclk_p, CLKSRC, 14, 2),
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MUX(0, "urefclk", urefclk_p, CLKSRC, 12, 2),
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MUX(0, "mux_cam", camclk_p, CLKSRC, 11, 1),
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MUX(0, "mux_usb", usbclk_p, CLKSRC, 10, 1),
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MUX(0, "mux_i2s", i2sclk_p, CLKSRC, 9, 1),
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MUX(0, "mux_uart", uartclk_p, CLKSRC, 8, 1),
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MUX(USYSCLK, "usysclk", usysclk_p, CLKSRC, 5, 1),
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MUX(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1),
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MUX(MDIVCLK, "mdivclk", mdivclk_p, CLKSRC, 3, 1),
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MUX(ARMCLK, "armclk", armclk_p, CLKDIVN, 4, 1),
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};
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static struct samsung_pll_clock s3c2412_plls[] __initdata = {
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[mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
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LOCKTIME, MPLLCON, NULL),
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[upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "urefclk",
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LOCKTIME, UPLLCON, NULL),
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};
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struct samsung_gate_clock s3c2412_gates[] __initdata = {
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GATE(PCLK_WDT, "wdt", "pclk", CLKCON, 28, 0, 0),
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GATE(PCLK_SPI, "spi", "pclk", CLKCON, 27, 0, 0),
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GATE(PCLK_I2S, "i2s", "pclk", CLKCON, 26, 0, 0),
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GATE(PCLK_I2C, "i2c", "pclk", CLKCON, 25, 0, 0),
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GATE(PCLK_ADC, "adc", "pclk", CLKCON, 24, 0, 0),
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GATE(PCLK_RTC, "rtc", "pclk", CLKCON, 23, 0, 0),
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GATE(PCLK_GPIO, "gpio", "pclk", CLKCON, 22, CLK_IGNORE_UNUSED, 0),
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GATE(PCLK_UART2, "uart2", "pclk", CLKCON, 21, 0, 0),
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GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 20, 0, 0),
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GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 19, 0, 0),
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GATE(PCLK_SDI, "sdi", "pclk", CLKCON, 18, 0, 0),
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GATE(PCLK_PWM, "pwm", "pclk", CLKCON, 17, 0, 0),
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GATE(PCLK_USBD, "usb-device", "pclk", CLKCON, 16, 0, 0),
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GATE(SCLK_CAM, "sclk_cam", "div_cam", CLKCON, 15, 0, 0),
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GATE(SCLK_UART, "sclk_uart", "div_uart", CLKCON, 14, 0, 0),
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GATE(SCLK_I2S, "sclk_i2s", "div_i2s", CLKCON, 13, 0, 0),
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GATE(SCLK_USBH, "sclk_usbh", "div_usb", CLKCON, 12, 0, 0),
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GATE(SCLK_USBD, "sclk_usbd", "div_usb", CLKCON, 11, 0, 0),
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GATE(HCLK_HALF, "hclk_half", "div_hclk_half", CLKCON, 10, CLK_IGNORE_UNUSED, 0),
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GATE(HCLK_X2, "hclkx2", "ff_hclk", CLKCON, 9, CLK_IGNORE_UNUSED, 0),
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GATE(HCLK_SDRAM, "sdram", "hclk", CLKCON, 8, CLK_IGNORE_UNUSED, 0),
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GATE(HCLK_USBH, "usb-host", "hclk", CLKCON, 6, 0, 0),
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GATE(HCLK_LCD, "lcd", "hclk", CLKCON, 5, 0, 0),
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GATE(HCLK_NAND, "nand", "hclk", CLKCON, 4, 0, 0),
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GATE(HCLK_DMA3, "dma3", "hclk", CLKCON, 3, CLK_IGNORE_UNUSED, 0),
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GATE(HCLK_DMA2, "dma2", "hclk", CLKCON, 2, CLK_IGNORE_UNUSED, 0),
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GATE(HCLK_DMA1, "dma1", "hclk", CLKCON, 1, CLK_IGNORE_UNUSED, 0),
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GATE(HCLK_DMA0, "dma0", "hclk", CLKCON, 0, CLK_IGNORE_UNUSED, 0),
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};
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struct samsung_clock_alias s3c2412_aliases[] __initdata = {
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ALIAS(PCLK_UART0, "s3c2412-uart.0", "uart"),
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ALIAS(PCLK_UART1, "s3c2412-uart.1", "uart"),
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ALIAS(PCLK_UART2, "s3c2412-uart.2", "uart"),
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ALIAS(PCLK_UART0, "s3c2412-uart.0", "clk_uart_baud2"),
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ALIAS(PCLK_UART1, "s3c2412-uart.1", "clk_uart_baud2"),
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ALIAS(PCLK_UART2, "s3c2412-uart.2", "clk_uart_baud2"),
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ALIAS(SCLK_UART, NULL, "clk_uart_baud3"),
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ALIAS(PCLK_I2C, "s3c2410-i2c.0", "i2c"),
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ALIAS(PCLK_ADC, NULL, "adc"),
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ALIAS(PCLK_RTC, NULL, "rtc"),
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ALIAS(PCLK_PWM, NULL, "timers"),
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ALIAS(HCLK_LCD, NULL, "lcd"),
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ALIAS(PCLK_USBD, NULL, "usb-device"),
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ALIAS(SCLK_USBD, NULL, "usb-bus-gadget"),
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ALIAS(HCLK_USBH, NULL, "usb-host"),
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ALIAS(SCLK_USBH, NULL, "usb-bus-host"),
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ALIAS(ARMCLK, NULL, "armclk"),
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ALIAS(HCLK, NULL, "hclk"),
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ALIAS(MPLL, NULL, "mpll"),
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ALIAS(MSYSCLK, NULL, "fclk"),
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};
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static int s3c2412_restart(struct notifier_block *this,
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unsigned long mode, void *cmd)
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{
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/* errata "Watch-dog/Software Reset Problem" specifies that
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* this reset must be done with the SYSCLK sourced from
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* EXTCLK instead of FOUT to avoid a glitch in the reset
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* mechanism.
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*
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* See the watchdog section of the S3C2412 manual for more
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* information on this fix.
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*/
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__raw_writel(0x00, reg_base + CLKSRC);
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__raw_writel(0x533C2412, reg_base + SWRST);
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return NOTIFY_DONE;
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}
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static struct notifier_block s3c2412_restart_handler = {
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.notifier_call = s3c2412_restart,
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.priority = 129,
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};
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/*
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* fixed rate clocks generated outside the soc
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* Only necessary until the devicetree-move is complete
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*/
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#define XTI 1
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struct samsung_fixed_rate_clock s3c2412_common_frate_clks[] __initdata = {
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FRATE(XTI, "xti", NULL, CLK_IS_ROOT, 0),
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FRATE(0, "ext", NULL, CLK_IS_ROOT, 0),
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};
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static void __init s3c2412_common_clk_register_fixed_ext(
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struct samsung_clk_provider *ctx,
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unsigned long xti_f, unsigned long ext_f)
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{
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/* xtal alias is necessary for the current cpufreq driver */
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struct samsung_clock_alias xti_alias = ALIAS(XTI, NULL, "xtal");
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s3c2412_common_frate_clks[0].fixed_rate = xti_f;
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s3c2412_common_frate_clks[1].fixed_rate = ext_f;
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samsung_clk_register_fixed_rate(ctx, s3c2412_common_frate_clks,
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ARRAY_SIZE(s3c2412_common_frate_clks));
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samsung_clk_register_alias(ctx, &xti_alias, 1);
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}
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void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f,
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unsigned long ext_f, void __iomem *base)
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{
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struct samsung_clk_provider *ctx;
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int ret;
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reg_base = base;
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if (np) {
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reg_base = of_iomap(np, 0);
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if (!reg_base)
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panic("%s: failed to map registers\n", __func__);
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}
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ctx = samsung_clk_init(np, reg_base, NR_CLKS);
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if (!ctx)
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panic("%s: unable to allocate context.\n", __func__);
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/* Register external clocks only in non-dt cases */
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if (!np)
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s3c2412_common_clk_register_fixed_ext(ctx, xti_f, ext_f);
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/* Register PLLs. */
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samsung_clk_register_pll(ctx, s3c2412_plls, ARRAY_SIZE(s3c2412_plls),
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reg_base);
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/* Register common internal clocks. */
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samsung_clk_register_mux(ctx, s3c2412_muxes, ARRAY_SIZE(s3c2412_muxes));
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samsung_clk_register_div(ctx, s3c2412_dividers,
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ARRAY_SIZE(s3c2412_dividers));
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samsung_clk_register_gate(ctx, s3c2412_gates,
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ARRAY_SIZE(s3c2412_gates));
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samsung_clk_register_fixed_factor(ctx, s3c2412_ffactor,
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ARRAY_SIZE(s3c2412_ffactor));
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samsung_clk_register_alias(ctx, s3c2412_aliases,
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ARRAY_SIZE(s3c2412_aliases));
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s3c2412_clk_sleep_init();
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samsung_clk_of_add_provider(np, ctx);
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ret = register_restart_handler(&s3c2412_restart_handler);
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if (ret)
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pr_warn("cannot register restart handler, %d\n", ret);
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}
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static void __init s3c2412_clk_init(struct device_node *np)
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{
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s3c2412_common_clk_init(np, 0, 0, 0);
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}
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CLK_OF_DECLARE(s3c2412_clk, "samsung,s3c2412-clock", s3c2412_clk_init);
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