00482a4078
This patch groups the self-refresh on/cpu_do_idle/self-refresh off into a single 'standby' function. The standby routine for rm9200 has been turned into an asm routine to have a better control of the self refresh and to prevent a memory access when running this code. Draining the write buffer is done automatically when switching for the self refresh on sam9, so the instruction is added to the rm9200 only. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
111 lines
2.8 KiB
C
111 lines
2.8 KiB
C
/*
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* AT91 Power Management
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*
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* Copyright (C) 2005 David Brownell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __ARCH_ARM_MACH_AT91_PM
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#define __ARCH_ARM_MACH_AT91_PM
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#ifdef CONFIG_ARCH_AT91RM9200
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#include <mach/at91rm9200_mc.h>
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/*
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* The AT91RM9200 goes into self-refresh mode with this command, and will
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* terminate self-refresh automatically on the next SDRAM access.
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*
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* Self-refresh mode is exited as soon as a memory access is made, but we don't
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* know for sure when that happens. However, we need to restore the low-power
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* mode if it was enabled before going idle. Restoring low-power mode while
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* still in self-refresh is "not recommended", but seems to work.
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*/
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static inline void at91rm9200_standby(void)
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{
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u32 lpr = at91_sys_read(AT91_SDRAMC_LPR);
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asm volatile(
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"b 1f\n\t"
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".align 5\n\t"
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"1: mcr p15, 0, %0, c7, c10, 4\n\t"
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" str %0, [%1, %2]\n\t"
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" str %3, [%1, %4]\n\t"
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" mcr p15, 0, %0, c7, c0, 4\n\t"
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" str %5, [%1, %2]"
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:
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: "r" (0), "r" (AT91_BASE_SYS), "r" (AT91_SDRAMC_LPR),
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"r" (1), "r" (AT91_SDRAMC_SRR),
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"r" (lpr));
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}
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#define at91_standby at91rm9200_standby
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#elif defined(CONFIG_ARCH_AT91SAM9G45)
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#include <mach/at91sam9_ddrsdr.h>
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/* We manage both DDRAM/SDRAM controllers, we need more than one value to
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* remember.
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*/
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static inline void at91sam9g45_standby(void)
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{
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/* Those two values allow us to delay self-refresh activation
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* to the maximum. */
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u32 lpr0, lpr1;
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u32 saved_lpr0, saved_lpr1;
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saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
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lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
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lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
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saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
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lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
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lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
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/* self-refresh mode now */
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at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
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at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
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cpu_do_idle();
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at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
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at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
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}
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#define at91_standby at91sam9g45_standby
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#else
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#include <mach/at91sam9_sdramc.h>
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#ifdef CONFIG_ARCH_AT91SAM9263
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/*
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* FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
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* handle those cases both here and in the Suspend-To-RAM support.
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*/
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#warning Assuming EB1 SDRAM controller is *NOT* used
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#endif
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static inline void at91sam9_standby(void)
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{
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u32 saved_lpr, lpr;
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saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
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lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
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at91_ramc_write(0, AT91_SDRAMC_LPR, lpr |
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AT91_SDRAMC_LPCB_SELF_REFRESH);
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cpu_do_idle();
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at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr);
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}
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#define at91_standby at91sam9_standby
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#endif
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#endif
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