![Yevgeny Petrilin](/assets/img/avatar_default.png)
MT26468 (PCI ID 0x6764) devices can expose multiple physical functions. The current driver only handles the primary physical function. For other functions, the QUERY_FW firmware command will fail with the CMD_STAT_MULTI_FUNC_REQ error code. Don't try to drive such devices, but print a message saying the driver is skipping those devices rather than just "QUERY_FW command failed." Signed-off-by: Yevgeny Petrilin <yevgenyp@mellanox.co.il> [ Rather than keeping unsupported devices bound to the driver, simply print a more informative error message and exit - Roland ] Signed-off-by: Roland Dreier <rolandd@cisco.com>
443 lines
12 KiB
C
443 lines
12 KiB
C
/*
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* Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
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* Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
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* Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/errno.h>
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#include <linux/mlx4/cmd.h>
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#include <asm/io.h>
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#include "mlx4.h"
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#define CMD_POLL_TOKEN 0xffff
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enum {
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/* command completed successfully: */
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CMD_STAT_OK = 0x00,
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/* Internal error (such as a bus error) occurred while processing command: */
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CMD_STAT_INTERNAL_ERR = 0x01,
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/* Operation/command not supported or opcode modifier not supported: */
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CMD_STAT_BAD_OP = 0x02,
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/* Parameter not supported or parameter out of range: */
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CMD_STAT_BAD_PARAM = 0x03,
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/* System not enabled or bad system state: */
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CMD_STAT_BAD_SYS_STATE = 0x04,
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/* Attempt to access reserved or unallocaterd resource: */
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CMD_STAT_BAD_RESOURCE = 0x05,
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/* Requested resource is currently executing a command, or is otherwise busy: */
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CMD_STAT_RESOURCE_BUSY = 0x06,
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/* Required capability exceeds device limits: */
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CMD_STAT_EXCEED_LIM = 0x08,
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/* Resource is not in the appropriate state or ownership: */
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CMD_STAT_BAD_RES_STATE = 0x09,
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/* Index out of range: */
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CMD_STAT_BAD_INDEX = 0x0a,
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/* FW image corrupted: */
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CMD_STAT_BAD_NVMEM = 0x0b,
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/* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
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CMD_STAT_ICM_ERROR = 0x0c,
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/* Attempt to modify a QP/EE which is not in the presumed state: */
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CMD_STAT_BAD_QP_STATE = 0x10,
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/* Bad segment parameters (Address/Size): */
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CMD_STAT_BAD_SEG_PARAM = 0x20,
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/* Memory Region has Memory Windows bound to: */
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CMD_STAT_REG_BOUND = 0x21,
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/* HCA local attached memory not present: */
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CMD_STAT_LAM_NOT_PRE = 0x22,
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/* Bad management packet (silently discarded): */
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CMD_STAT_BAD_PKT = 0x30,
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/* More outstanding CQEs in CQ than new CQ size: */
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CMD_STAT_BAD_SIZE = 0x40,
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/* Multi Function device support required: */
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CMD_STAT_MULTI_FUNC_REQ = 0x50,
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};
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enum {
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HCR_IN_PARAM_OFFSET = 0x00,
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HCR_IN_MODIFIER_OFFSET = 0x08,
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HCR_OUT_PARAM_OFFSET = 0x0c,
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HCR_TOKEN_OFFSET = 0x14,
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HCR_STATUS_OFFSET = 0x18,
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HCR_OPMOD_SHIFT = 12,
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HCR_T_BIT = 21,
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HCR_E_BIT = 22,
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HCR_GO_BIT = 23
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};
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enum {
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GO_BIT_TIMEOUT_MSECS = 10000
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};
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struct mlx4_cmd_context {
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struct completion done;
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int result;
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int next;
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u64 out_param;
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u16 token;
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};
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static int mlx4_status_to_errno(u8 status)
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{
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static const int trans_table[] = {
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[CMD_STAT_INTERNAL_ERR] = -EIO,
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[CMD_STAT_BAD_OP] = -EPERM,
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[CMD_STAT_BAD_PARAM] = -EINVAL,
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[CMD_STAT_BAD_SYS_STATE] = -ENXIO,
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[CMD_STAT_BAD_RESOURCE] = -EBADF,
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[CMD_STAT_RESOURCE_BUSY] = -EBUSY,
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[CMD_STAT_EXCEED_LIM] = -ENOMEM,
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[CMD_STAT_BAD_RES_STATE] = -EBADF,
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[CMD_STAT_BAD_INDEX] = -EBADF,
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[CMD_STAT_BAD_NVMEM] = -EFAULT,
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[CMD_STAT_ICM_ERROR] = -ENFILE,
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[CMD_STAT_BAD_QP_STATE] = -EINVAL,
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[CMD_STAT_BAD_SEG_PARAM] = -EFAULT,
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[CMD_STAT_REG_BOUND] = -EBUSY,
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[CMD_STAT_LAM_NOT_PRE] = -EAGAIN,
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[CMD_STAT_BAD_PKT] = -EINVAL,
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[CMD_STAT_BAD_SIZE] = -ENOMEM,
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[CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
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};
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if (status >= ARRAY_SIZE(trans_table) ||
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(status != CMD_STAT_OK && trans_table[status] == 0))
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return -EIO;
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return trans_table[status];
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}
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static int cmd_pending(struct mlx4_dev *dev)
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{
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u32 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
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return (status & swab32(1 << HCR_GO_BIT)) ||
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(mlx4_priv(dev)->cmd.toggle ==
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!!(status & swab32(1 << HCR_T_BIT)));
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}
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static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
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u32 in_modifier, u8 op_modifier, u16 op, u16 token,
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int event)
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{
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struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
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u32 __iomem *hcr = cmd->hcr;
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int ret = -EAGAIN;
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unsigned long end;
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mutex_lock(&cmd->hcr_mutex);
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end = jiffies;
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if (event)
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end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
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while (cmd_pending(dev)) {
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if (time_after_eq(jiffies, end))
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goto out;
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cond_resched();
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}
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/*
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* We use writel (instead of something like memcpy_toio)
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* because writes of less than 32 bits to the HCR don't work
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* (and some architectures such as ia64 implement memcpy_toio
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* in terms of writeb).
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*/
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__raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0);
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__raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1);
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__raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2);
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__raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3);
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__raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
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__raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5);
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/* __raw_writel may not order writes. */
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wmb();
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__raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
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(cmd->toggle << HCR_T_BIT) |
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(event ? (1 << HCR_E_BIT) : 0) |
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(op_modifier << HCR_OPMOD_SHIFT) |
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op), hcr + 6);
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/*
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* Make sure that our HCR writes don't get mixed in with
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* writes from another CPU starting a FW command.
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*/
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mmiowb();
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cmd->toggle = cmd->toggle ^ 1;
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ret = 0;
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out:
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mutex_unlock(&cmd->hcr_mutex);
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return ret;
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}
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static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
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int out_is_imm, u32 in_modifier, u8 op_modifier,
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u16 op, unsigned long timeout)
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{
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struct mlx4_priv *priv = mlx4_priv(dev);
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void __iomem *hcr = priv->cmd.hcr;
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int err = 0;
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unsigned long end;
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down(&priv->cmd.poll_sem);
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err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
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in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
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if (err)
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goto out;
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end = msecs_to_jiffies(timeout) + jiffies;
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while (cmd_pending(dev) && time_before(jiffies, end))
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cond_resched();
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if (cmd_pending(dev)) {
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err = -ETIMEDOUT;
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goto out;
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}
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if (out_is_imm)
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*out_param =
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(u64) be32_to_cpu((__force __be32)
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__raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
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(u64) be32_to_cpu((__force __be32)
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__raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
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err = mlx4_status_to_errno(be32_to_cpu((__force __be32)
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__raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24);
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out:
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up(&priv->cmd.poll_sem);
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return err;
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}
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void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
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{
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struct mlx4_priv *priv = mlx4_priv(dev);
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struct mlx4_cmd_context *context =
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&priv->cmd.context[token & priv->cmd.token_mask];
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/* previously timed out command completing at long last */
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if (token != context->token)
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return;
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context->result = mlx4_status_to_errno(status);
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context->out_param = out_param;
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complete(&context->done);
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}
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static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
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int out_is_imm, u32 in_modifier, u8 op_modifier,
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u16 op, unsigned long timeout)
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{
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struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
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struct mlx4_cmd_context *context;
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int err = 0;
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down(&cmd->event_sem);
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spin_lock(&cmd->context_lock);
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BUG_ON(cmd->free_head < 0);
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context = &cmd->context[cmd->free_head];
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context->token += cmd->token_mask + 1;
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cmd->free_head = context->next;
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spin_unlock(&cmd->context_lock);
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init_completion(&context->done);
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mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
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in_modifier, op_modifier, op, context->token, 1);
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if (!wait_for_completion_timeout(&context->done, msecs_to_jiffies(timeout))) {
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err = -EBUSY;
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goto out;
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}
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err = context->result;
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if (err)
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goto out;
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if (out_is_imm)
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*out_param = context->out_param;
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out:
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spin_lock(&cmd->context_lock);
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context->next = cmd->free_head;
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cmd->free_head = context - cmd->context;
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spin_unlock(&cmd->context_lock);
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up(&cmd->event_sem);
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return err;
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}
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int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
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int out_is_imm, u32 in_modifier, u8 op_modifier,
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u16 op, unsigned long timeout)
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{
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if (mlx4_priv(dev)->cmd.use_events)
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return mlx4_cmd_wait(dev, in_param, out_param, out_is_imm,
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in_modifier, op_modifier, op, timeout);
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else
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return mlx4_cmd_poll(dev, in_param, out_param, out_is_imm,
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in_modifier, op_modifier, op, timeout);
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}
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EXPORT_SYMBOL_GPL(__mlx4_cmd);
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int mlx4_cmd_init(struct mlx4_dev *dev)
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{
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struct mlx4_priv *priv = mlx4_priv(dev);
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mutex_init(&priv->cmd.hcr_mutex);
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sema_init(&priv->cmd.poll_sem, 1);
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priv->cmd.use_events = 0;
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priv->cmd.toggle = 1;
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priv->cmd.hcr = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_HCR_BASE,
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MLX4_HCR_SIZE);
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if (!priv->cmd.hcr) {
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mlx4_err(dev, "Couldn't map command register.");
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return -ENOMEM;
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}
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priv->cmd.pool = pci_pool_create("mlx4_cmd", dev->pdev,
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MLX4_MAILBOX_SIZE,
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MLX4_MAILBOX_SIZE, 0);
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if (!priv->cmd.pool) {
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iounmap(priv->cmd.hcr);
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return -ENOMEM;
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}
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return 0;
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}
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void mlx4_cmd_cleanup(struct mlx4_dev *dev)
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{
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struct mlx4_priv *priv = mlx4_priv(dev);
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pci_pool_destroy(priv->cmd.pool);
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iounmap(priv->cmd.hcr);
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}
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/*
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* Switch to using events to issue FW commands (can only be called
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* after event queue for command events has been initialized).
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*/
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int mlx4_cmd_use_events(struct mlx4_dev *dev)
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{
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struct mlx4_priv *priv = mlx4_priv(dev);
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int i;
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priv->cmd.context = kmalloc(priv->cmd.max_cmds *
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sizeof (struct mlx4_cmd_context),
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GFP_KERNEL);
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if (!priv->cmd.context)
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return -ENOMEM;
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for (i = 0; i < priv->cmd.max_cmds; ++i) {
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priv->cmd.context[i].token = i;
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priv->cmd.context[i].next = i + 1;
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}
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priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
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priv->cmd.free_head = 0;
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sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
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spin_lock_init(&priv->cmd.context_lock);
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for (priv->cmd.token_mask = 1;
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priv->cmd.token_mask < priv->cmd.max_cmds;
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priv->cmd.token_mask <<= 1)
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; /* nothing */
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--priv->cmd.token_mask;
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priv->cmd.use_events = 1;
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down(&priv->cmd.poll_sem);
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return 0;
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}
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/*
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* Switch back to polling (used when shutting down the device)
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*/
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void mlx4_cmd_use_polling(struct mlx4_dev *dev)
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{
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struct mlx4_priv *priv = mlx4_priv(dev);
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int i;
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priv->cmd.use_events = 0;
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for (i = 0; i < priv->cmd.max_cmds; ++i)
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down(&priv->cmd.event_sem);
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kfree(priv->cmd.context);
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up(&priv->cmd.poll_sem);
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}
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struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
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{
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struct mlx4_cmd_mailbox *mailbox;
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mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
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if (!mailbox)
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return ERR_PTR(-ENOMEM);
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mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
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&mailbox->dma);
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if (!mailbox->buf) {
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kfree(mailbox);
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return ERR_PTR(-ENOMEM);
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}
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return mailbox;
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}
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EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
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void mlx4_free_cmd_mailbox(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox)
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{
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if (!mailbox)
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return;
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pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
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kfree(mailbox);
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}
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EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
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