![Mian Yousaf Kaukab](/assets/img/avatar_default.png)
As descriptor dma mode does not support split transfers, it can't be enabled for high speed devices. Add a core parameter to enable it for full speed devices. Ensure frame list and descriptor list are correctly freed during disconnect. Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@intel.com> Signed-off-by: Gregory Herrero <gregory.herrero@intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
810 lines
22 KiB
C
810 lines
22 KiB
C
/*
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* hcd_queue.c - DesignWare HS OTG Controller host queuing routines
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*
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* Copyright (C) 2004-2013 Synopsys, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The names of the above-listed copyright holders may not be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* This file contains the functions to manage Queue Heads and Queue
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* Transfer Descriptors for Host mode
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/usb.h>
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#include <linux/usb/hcd.h>
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#include <linux/usb/ch11.h>
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#include "core.h"
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#include "hcd.h"
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/**
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* dwc2_qh_init() - Initializes a QH structure
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*
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* @hsotg: The HCD state structure for the DWC OTG controller
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* @qh: The QH to init
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* @urb: Holds the information about the device/endpoint needed to initialize
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* the QH
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*/
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#define SCHEDULE_SLOP 10
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static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
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struct dwc2_hcd_urb *urb)
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{
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int dev_speed, hub_addr, hub_port;
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char *speed, *type;
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dev_vdbg(hsotg->dev, "%s()\n", __func__);
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/* Initialize QH */
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qh->ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
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qh->ep_is_in = dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0;
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qh->data_toggle = DWC2_HC_PID_DATA0;
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qh->maxp = dwc2_hcd_get_mps(&urb->pipe_info);
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INIT_LIST_HEAD(&qh->qtd_list);
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INIT_LIST_HEAD(&qh->qh_list_entry);
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/* FS/LS Endpoint on HS Hub, NOT virtual root hub */
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dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
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dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
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if ((dev_speed == USB_SPEED_LOW || dev_speed == USB_SPEED_FULL) &&
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hub_addr != 0 && hub_addr != 1) {
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dev_vdbg(hsotg->dev,
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"QH init: EP %d: TT found at hub addr %d, for port %d\n",
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dwc2_hcd_get_ep_num(&urb->pipe_info), hub_addr,
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hub_port);
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qh->do_split = 1;
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}
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if (qh->ep_type == USB_ENDPOINT_XFER_INT ||
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qh->ep_type == USB_ENDPOINT_XFER_ISOC) {
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/* Compute scheduling parameters once and save them */
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u32 hprt, prtspd;
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/* Todo: Account for split transfers in the bus time */
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int bytecount =
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dwc2_hb_mult(qh->maxp) * dwc2_max_packet(qh->maxp);
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qh->usecs = NS_TO_US(usb_calc_bus_time(qh->do_split ?
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USB_SPEED_HIGH : dev_speed, qh->ep_is_in,
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qh->ep_type == USB_ENDPOINT_XFER_ISOC,
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bytecount));
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/* Ensure frame_number corresponds to the reality */
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hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
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/* Start in a slightly future (micro)frame */
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qh->sched_frame = dwc2_frame_num_inc(hsotg->frame_number,
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SCHEDULE_SLOP);
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qh->interval = urb->interval;
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#if 0
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/* Increase interrupt polling rate for debugging */
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if (qh->ep_type == USB_ENDPOINT_XFER_INT)
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qh->interval = 8;
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#endif
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hprt = dwc2_readl(hsotg->regs + HPRT0);
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prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
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if (prtspd == HPRT0_SPD_HIGH_SPEED &&
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(dev_speed == USB_SPEED_LOW ||
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dev_speed == USB_SPEED_FULL)) {
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qh->interval *= 8;
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qh->sched_frame |= 0x7;
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qh->start_split_frame = qh->sched_frame;
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}
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dev_dbg(hsotg->dev, "interval=%d\n", qh->interval);
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}
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dev_vdbg(hsotg->dev, "DWC OTG HCD QH Initialized\n");
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dev_vdbg(hsotg->dev, "DWC OTG HCD QH - qh = %p\n", qh);
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dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Device Address = %d\n",
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dwc2_hcd_get_dev_addr(&urb->pipe_info));
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dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Endpoint %d, %s\n",
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dwc2_hcd_get_ep_num(&urb->pipe_info),
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dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
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qh->dev_speed = dev_speed;
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switch (dev_speed) {
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case USB_SPEED_LOW:
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speed = "low";
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break;
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case USB_SPEED_FULL:
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speed = "full";
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break;
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case USB_SPEED_HIGH:
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speed = "high";
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break;
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default:
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speed = "?";
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break;
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}
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dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Speed = %s\n", speed);
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switch (qh->ep_type) {
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case USB_ENDPOINT_XFER_ISOC:
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type = "isochronous";
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break;
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case USB_ENDPOINT_XFER_INT:
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type = "interrupt";
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break;
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case USB_ENDPOINT_XFER_CONTROL:
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type = "control";
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break;
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case USB_ENDPOINT_XFER_BULK:
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type = "bulk";
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break;
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default:
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type = "?";
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break;
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}
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dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Type = %s\n", type);
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if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
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dev_vdbg(hsotg->dev, "DWC OTG HCD QH - usecs = %d\n",
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qh->usecs);
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dev_vdbg(hsotg->dev, "DWC OTG HCD QH - interval = %d\n",
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qh->interval);
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}
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}
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/**
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* dwc2_hcd_qh_create() - Allocates and initializes a QH
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*
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* @hsotg: The HCD state structure for the DWC OTG controller
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* @urb: Holds the information about the device/endpoint needed
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* to initialize the QH
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* @atomic_alloc: Flag to do atomic allocation if needed
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*
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* Return: Pointer to the newly allocated QH, or NULL on error
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*/
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struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
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struct dwc2_hcd_urb *urb,
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gfp_t mem_flags)
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{
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struct dwc2_qh *qh;
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if (!urb->priv)
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return NULL;
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/* Allocate memory */
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qh = kzalloc(sizeof(*qh), mem_flags);
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if (!qh)
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return NULL;
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dwc2_qh_init(hsotg, qh, urb);
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if (hsotg->core_params->dma_desc_enable > 0 &&
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dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) {
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dwc2_hcd_qh_free(hsotg, qh);
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return NULL;
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}
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return qh;
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}
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/**
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* dwc2_hcd_qh_free() - Frees the QH
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*
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* @hsotg: HCD instance
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* @qh: The QH to free
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*
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* QH should already be removed from the list. QTD list should already be empty
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* if called from URB Dequeue.
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*
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* Must NOT be called with interrupt disabled or spinlock held
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*/
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void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
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{
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if (qh->desc_list) {
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dwc2_hcd_qh_free_ddma(hsotg, qh);
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} else {
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/* kfree(NULL) is safe */
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kfree(qh->dw_align_buf);
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qh->dw_align_buf_dma = (dma_addr_t)0;
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}
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kfree(qh);
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}
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/**
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* dwc2_periodic_channel_available() - Checks that a channel is available for a
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* periodic transfer
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*
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* @hsotg: The HCD state structure for the DWC OTG controller
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*
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* Return: 0 if successful, negative error code otherwise
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*/
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static int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg)
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{
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/*
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* Currently assuming that there is a dedicated host channel for
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* each periodic transaction plus at least one host channel for
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* non-periodic transactions
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*/
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int status;
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int num_channels;
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num_channels = hsotg->core_params->host_channels;
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if (hsotg->periodic_channels + hsotg->non_periodic_channels <
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num_channels
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&& hsotg->periodic_channels < num_channels - 1) {
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status = 0;
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} else {
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dev_dbg(hsotg->dev,
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"%s: Total channels: %d, Periodic: %d, "
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"Non-periodic: %d\n", __func__, num_channels,
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hsotg->periodic_channels, hsotg->non_periodic_channels);
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status = -ENOSPC;
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}
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return status;
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}
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/**
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* dwc2_check_periodic_bandwidth() - Checks that there is sufficient bandwidth
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* for the specified QH in the periodic schedule
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*
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* @hsotg: The HCD state structure for the DWC OTG controller
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* @qh: QH containing periodic bandwidth required
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*
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* Return: 0 if successful, negative error code otherwise
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*
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* For simplicity, this calculation assumes that all the transfers in the
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* periodic schedule may occur in the same (micro)frame
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*/
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static int dwc2_check_periodic_bandwidth(struct dwc2_hsotg *hsotg,
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struct dwc2_qh *qh)
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{
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int status;
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s16 max_claimed_usecs;
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status = 0;
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if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) {
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/*
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* High speed mode
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* Max periodic usecs is 80% x 125 usec = 100 usec
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*/
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max_claimed_usecs = 100 - qh->usecs;
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} else {
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/*
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* Full speed mode
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* Max periodic usecs is 90% x 1000 usec = 900 usec
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*/
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max_claimed_usecs = 900 - qh->usecs;
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}
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if (hsotg->periodic_usecs > max_claimed_usecs) {
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dev_err(hsotg->dev,
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"%s: already claimed usecs %d, required usecs %d\n",
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__func__, hsotg->periodic_usecs, qh->usecs);
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status = -ENOSPC;
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}
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return status;
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}
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/**
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* Microframe scheduler
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* track the total use in hsotg->frame_usecs
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* keep each qh use in qh->frame_usecs
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* when surrendering the qh then donate the time back
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*/
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static const unsigned short max_uframe_usecs[] = {
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100, 100, 100, 100, 100, 100, 30, 0
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};
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void dwc2_hcd_init_usecs(struct dwc2_hsotg *hsotg)
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{
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int i;
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for (i = 0; i < 8; i++)
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hsotg->frame_usecs[i] = max_uframe_usecs[i];
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}
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static int dwc2_find_single_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
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{
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unsigned short utime = qh->usecs;
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int i;
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for (i = 0; i < 8; i++) {
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/* At the start hsotg->frame_usecs[i] = max_uframe_usecs[i] */
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if (utime <= hsotg->frame_usecs[i]) {
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hsotg->frame_usecs[i] -= utime;
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qh->frame_usecs[i] += utime;
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return i;
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}
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}
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return -ENOSPC;
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}
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/*
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* use this for FS apps that can span multiple uframes
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*/
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static int dwc2_find_multi_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
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{
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unsigned short utime = qh->usecs;
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unsigned short xtime;
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int t_left;
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int i;
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int j;
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int k;
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for (i = 0; i < 8; i++) {
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if (hsotg->frame_usecs[i] <= 0)
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continue;
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/*
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* we need n consecutive slots so use j as a start slot
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* j plus j+1 must be enough time (for now)
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*/
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xtime = hsotg->frame_usecs[i];
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for (j = i + 1; j < 8; j++) {
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/*
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* if we add this frame remaining time to xtime we may
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* be OK, if not we need to test j for a complete frame
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*/
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if (xtime + hsotg->frame_usecs[j] < utime) {
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if (hsotg->frame_usecs[j] <
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max_uframe_usecs[j])
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continue;
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}
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if (xtime >= utime) {
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t_left = utime;
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for (k = i; k < 8; k++) {
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t_left -= hsotg->frame_usecs[k];
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if (t_left <= 0) {
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qh->frame_usecs[k] +=
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hsotg->frame_usecs[k]
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+ t_left;
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hsotg->frame_usecs[k] = -t_left;
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return i;
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} else {
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qh->frame_usecs[k] +=
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hsotg->frame_usecs[k];
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hsotg->frame_usecs[k] = 0;
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}
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}
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}
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/* add the frame time to x time */
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xtime += hsotg->frame_usecs[j];
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/* we must have a fully available next frame or break */
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if (xtime < utime &&
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hsotg->frame_usecs[j] == max_uframe_usecs[j])
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continue;
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}
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}
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return -ENOSPC;
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}
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static int dwc2_find_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
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{
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int ret;
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if (qh->dev_speed == USB_SPEED_HIGH) {
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/* if this is a hs transaction we need a full frame */
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ret = dwc2_find_single_uframe(hsotg, qh);
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} else {
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/*
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* if this is a fs transaction we may need a sequence
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* of frames
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*/
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ret = dwc2_find_multi_uframe(hsotg, qh);
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}
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return ret;
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}
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/**
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* dwc2_check_max_xfer_size() - Checks that the max transfer size allowed in a
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* host channel is large enough to handle the maximum data transfer in a single
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* (micro)frame for a periodic transfer
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*
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* @hsotg: The HCD state structure for the DWC OTG controller
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* @qh: QH for a periodic endpoint
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*
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* Return: 0 if successful, negative error code otherwise
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*/
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static int dwc2_check_max_xfer_size(struct dwc2_hsotg *hsotg,
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struct dwc2_qh *qh)
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{
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u32 max_xfer_size;
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u32 max_channel_xfer_size;
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int status = 0;
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max_xfer_size = dwc2_max_packet(qh->maxp) * dwc2_hb_mult(qh->maxp);
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max_channel_xfer_size = hsotg->core_params->max_transfer_size;
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if (max_xfer_size > max_channel_xfer_size) {
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dev_err(hsotg->dev,
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"%s: Periodic xfer length %d > max xfer length for channel %d\n",
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__func__, max_xfer_size, max_channel_xfer_size);
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status = -ENOSPC;
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}
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return status;
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}
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/**
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* dwc2_schedule_periodic() - Schedules an interrupt or isochronous transfer in
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* the periodic schedule
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*
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* @hsotg: The HCD state structure for the DWC OTG controller
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* @qh: QH for the periodic transfer. The QH should already contain the
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* scheduling information.
|
|
*
|
|
* Return: 0 if successful, negative error code otherwise
|
|
*/
|
|
static int dwc2_schedule_periodic(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
|
|
{
|
|
int status;
|
|
|
|
if (hsotg->core_params->uframe_sched > 0) {
|
|
int frame = -1;
|
|
|
|
status = dwc2_find_uframe(hsotg, qh);
|
|
if (status == 0)
|
|
frame = 7;
|
|
else if (status > 0)
|
|
frame = status - 1;
|
|
|
|
/* Set the new frame up */
|
|
if (frame >= 0) {
|
|
qh->sched_frame &= ~0x7;
|
|
qh->sched_frame |= (frame & 7);
|
|
}
|
|
|
|
if (status > 0)
|
|
status = 0;
|
|
} else {
|
|
status = dwc2_periodic_channel_available(hsotg);
|
|
if (status) {
|
|
dev_info(hsotg->dev,
|
|
"%s: No host channel available for periodic transfer\n",
|
|
__func__);
|
|
return status;
|
|
}
|
|
|
|
status = dwc2_check_periodic_bandwidth(hsotg, qh);
|
|
}
|
|
|
|
if (status) {
|
|
dev_dbg(hsotg->dev,
|
|
"%s: Insufficient periodic bandwidth for periodic transfer\n",
|
|
__func__);
|
|
return status;
|
|
}
|
|
|
|
status = dwc2_check_max_xfer_size(hsotg, qh);
|
|
if (status) {
|
|
dev_dbg(hsotg->dev,
|
|
"%s: Channel max transfer size too small for periodic transfer\n",
|
|
__func__);
|
|
return status;
|
|
}
|
|
|
|
if (hsotg->core_params->dma_desc_enable > 0)
|
|
/* Don't rely on SOF and start in ready schedule */
|
|
list_add_tail(&qh->qh_list_entry, &hsotg->periodic_sched_ready);
|
|
else
|
|
/* Always start in inactive schedule */
|
|
list_add_tail(&qh->qh_list_entry,
|
|
&hsotg->periodic_sched_inactive);
|
|
|
|
if (hsotg->core_params->uframe_sched <= 0)
|
|
/* Reserve periodic channel */
|
|
hsotg->periodic_channels++;
|
|
|
|
/* Update claimed usecs per (micro)frame */
|
|
hsotg->periodic_usecs += qh->usecs;
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* dwc2_deschedule_periodic() - Removes an interrupt or isochronous transfer
|
|
* from the periodic schedule
|
|
*
|
|
* @hsotg: The HCD state structure for the DWC OTG controller
|
|
* @qh: QH for the periodic transfer
|
|
*/
|
|
static void dwc2_deschedule_periodic(struct dwc2_hsotg *hsotg,
|
|
struct dwc2_qh *qh)
|
|
{
|
|
int i;
|
|
|
|
list_del_init(&qh->qh_list_entry);
|
|
|
|
/* Update claimed usecs per (micro)frame */
|
|
hsotg->periodic_usecs -= qh->usecs;
|
|
|
|
if (hsotg->core_params->uframe_sched > 0) {
|
|
for (i = 0; i < 8; i++) {
|
|
hsotg->frame_usecs[i] += qh->frame_usecs[i];
|
|
qh->frame_usecs[i] = 0;
|
|
}
|
|
} else {
|
|
/* Release periodic channel reservation */
|
|
hsotg->periodic_channels--;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* dwc2_hcd_qh_add() - Adds a QH to either the non periodic or periodic
|
|
* schedule if it is not already in the schedule. If the QH is already in
|
|
* the schedule, no action is taken.
|
|
*
|
|
* @hsotg: The HCD state structure for the DWC OTG controller
|
|
* @qh: The QH to add
|
|
*
|
|
* Return: 0 if successful, negative error code otherwise
|
|
*/
|
|
int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
|
|
{
|
|
int status;
|
|
u32 intr_mask;
|
|
|
|
if (dbg_qh(qh))
|
|
dev_vdbg(hsotg->dev, "%s()\n", __func__);
|
|
|
|
if (!list_empty(&qh->qh_list_entry))
|
|
/* QH already in a schedule */
|
|
return 0;
|
|
|
|
if (!dwc2_frame_num_le(qh->sched_frame, hsotg->frame_number) &&
|
|
!hsotg->frame_number) {
|
|
dev_dbg(hsotg->dev,
|
|
"reset frame number counter\n");
|
|
qh->sched_frame = dwc2_frame_num_inc(hsotg->frame_number,
|
|
SCHEDULE_SLOP);
|
|
}
|
|
|
|
/* Add the new QH to the appropriate schedule */
|
|
if (dwc2_qh_is_non_per(qh)) {
|
|
/* Always start in inactive schedule */
|
|
list_add_tail(&qh->qh_list_entry,
|
|
&hsotg->non_periodic_sched_inactive);
|
|
return 0;
|
|
}
|
|
|
|
status = dwc2_schedule_periodic(hsotg, qh);
|
|
if (status)
|
|
return status;
|
|
if (!hsotg->periodic_qh_count) {
|
|
intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
|
|
intr_mask |= GINTSTS_SOF;
|
|
dwc2_writel(intr_mask, hsotg->regs + GINTMSK);
|
|
}
|
|
hsotg->periodic_qh_count++;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* dwc2_hcd_qh_unlink() - Removes a QH from either the non-periodic or periodic
|
|
* schedule. Memory is not freed.
|
|
*
|
|
* @hsotg: The HCD state structure
|
|
* @qh: QH to remove from schedule
|
|
*/
|
|
void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
|
|
{
|
|
u32 intr_mask;
|
|
|
|
dev_vdbg(hsotg->dev, "%s()\n", __func__);
|
|
|
|
if (list_empty(&qh->qh_list_entry))
|
|
/* QH is not in a schedule */
|
|
return;
|
|
|
|
if (dwc2_qh_is_non_per(qh)) {
|
|
if (hsotg->non_periodic_qh_ptr == &qh->qh_list_entry)
|
|
hsotg->non_periodic_qh_ptr =
|
|
hsotg->non_periodic_qh_ptr->next;
|
|
list_del_init(&qh->qh_list_entry);
|
|
return;
|
|
}
|
|
|
|
dwc2_deschedule_periodic(hsotg, qh);
|
|
hsotg->periodic_qh_count--;
|
|
if (!hsotg->periodic_qh_count) {
|
|
intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
|
|
intr_mask &= ~GINTSTS_SOF;
|
|
dwc2_writel(intr_mask, hsotg->regs + GINTMSK);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Schedule the next continuing periodic split transfer
|
|
*/
|
|
static void dwc2_sched_periodic_split(struct dwc2_hsotg *hsotg,
|
|
struct dwc2_qh *qh, u16 frame_number,
|
|
int sched_next_periodic_split)
|
|
{
|
|
u16 incr;
|
|
|
|
if (sched_next_periodic_split) {
|
|
qh->sched_frame = frame_number;
|
|
incr = dwc2_frame_num_inc(qh->start_split_frame, 1);
|
|
if (dwc2_frame_num_le(frame_number, incr)) {
|
|
/*
|
|
* Allow one frame to elapse after start split
|
|
* microframe before scheduling complete split, but
|
|
* DON'T if we are doing the next start split in the
|
|
* same frame for an ISOC out
|
|
*/
|
|
if (qh->ep_type != USB_ENDPOINT_XFER_ISOC ||
|
|
qh->ep_is_in != 0) {
|
|
qh->sched_frame =
|
|
dwc2_frame_num_inc(qh->sched_frame, 1);
|
|
}
|
|
}
|
|
} else {
|
|
qh->sched_frame = dwc2_frame_num_inc(qh->start_split_frame,
|
|
qh->interval);
|
|
if (dwc2_frame_num_le(qh->sched_frame, frame_number))
|
|
qh->sched_frame = frame_number;
|
|
qh->sched_frame |= 0x7;
|
|
qh->start_split_frame = qh->sched_frame;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Deactivates a QH. For non-periodic QHs, removes the QH from the active
|
|
* non-periodic schedule. The QH is added to the inactive non-periodic
|
|
* schedule if any QTDs are still attached to the QH.
|
|
*
|
|
* For periodic QHs, the QH is removed from the periodic queued schedule. If
|
|
* there are any QTDs still attached to the QH, the QH is added to either the
|
|
* periodic inactive schedule or the periodic ready schedule and its next
|
|
* scheduled frame is calculated. The QH is placed in the ready schedule if
|
|
* the scheduled frame has been reached already. Otherwise it's placed in the
|
|
* inactive schedule. If there are no QTDs attached to the QH, the QH is
|
|
* completely removed from the periodic schedule.
|
|
*/
|
|
void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
|
|
int sched_next_periodic_split)
|
|
{
|
|
u16 frame_number;
|
|
|
|
if (dbg_qh(qh))
|
|
dev_vdbg(hsotg->dev, "%s()\n", __func__);
|
|
|
|
if (dwc2_qh_is_non_per(qh)) {
|
|
dwc2_hcd_qh_unlink(hsotg, qh);
|
|
if (!list_empty(&qh->qtd_list))
|
|
/* Add back to inactive non-periodic schedule */
|
|
dwc2_hcd_qh_add(hsotg, qh);
|
|
return;
|
|
}
|
|
|
|
frame_number = dwc2_hcd_get_frame_number(hsotg);
|
|
|
|
if (qh->do_split) {
|
|
dwc2_sched_periodic_split(hsotg, qh, frame_number,
|
|
sched_next_periodic_split);
|
|
} else {
|
|
qh->sched_frame = dwc2_frame_num_inc(qh->sched_frame,
|
|
qh->interval);
|
|
if (dwc2_frame_num_le(qh->sched_frame, frame_number))
|
|
qh->sched_frame = frame_number;
|
|
}
|
|
|
|
if (list_empty(&qh->qtd_list)) {
|
|
dwc2_hcd_qh_unlink(hsotg, qh);
|
|
return;
|
|
}
|
|
/*
|
|
* Remove from periodic_sched_queued and move to
|
|
* appropriate queue
|
|
*/
|
|
if ((hsotg->core_params->uframe_sched > 0 &&
|
|
dwc2_frame_num_le(qh->sched_frame, frame_number)) ||
|
|
(hsotg->core_params->uframe_sched <= 0 &&
|
|
qh->sched_frame == frame_number))
|
|
list_move(&qh->qh_list_entry, &hsotg->periodic_sched_ready);
|
|
else
|
|
list_move(&qh->qh_list_entry, &hsotg->periodic_sched_inactive);
|
|
}
|
|
|
|
/**
|
|
* dwc2_hcd_qtd_init() - Initializes a QTD structure
|
|
*
|
|
* @qtd: The QTD to initialize
|
|
* @urb: The associated URB
|
|
*/
|
|
void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
|
|
{
|
|
qtd->urb = urb;
|
|
if (dwc2_hcd_get_pipe_type(&urb->pipe_info) ==
|
|
USB_ENDPOINT_XFER_CONTROL) {
|
|
/*
|
|
* The only time the QTD data toggle is used is on the data
|
|
* phase of control transfers. This phase always starts with
|
|
* DATA1.
|
|
*/
|
|
qtd->data_toggle = DWC2_HC_PID_DATA1;
|
|
qtd->control_phase = DWC2_CONTROL_SETUP;
|
|
}
|
|
|
|
/* Start split */
|
|
qtd->complete_split = 0;
|
|
qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
|
|
qtd->isoc_split_offset = 0;
|
|
qtd->in_process = 0;
|
|
|
|
/* Store the qtd ptr in the urb to reference the QTD */
|
|
urb->qtd = qtd;
|
|
}
|
|
|
|
/**
|
|
* dwc2_hcd_qtd_add() - Adds a QTD to the QTD-list of a QH
|
|
* Caller must hold driver lock.
|
|
*
|
|
* @hsotg: The DWC HCD structure
|
|
* @qtd: The QTD to add
|
|
* @qh: Queue head to add qtd to
|
|
*
|
|
* Return: 0 if successful, negative error code otherwise
|
|
*
|
|
* If the QH to which the QTD is added is not currently scheduled, it is placed
|
|
* into the proper schedule based on its EP type.
|
|
*/
|
|
int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
|
|
struct dwc2_qh *qh)
|
|
{
|
|
int retval;
|
|
|
|
if (unlikely(!qh)) {
|
|
dev_err(hsotg->dev, "%s: Invalid QH\n", __func__);
|
|
retval = -EINVAL;
|
|
goto fail;
|
|
}
|
|
|
|
retval = dwc2_hcd_qh_add(hsotg, qh);
|
|
if (retval)
|
|
goto fail;
|
|
|
|
qtd->qh = qh;
|
|
list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list);
|
|
|
|
return 0;
|
|
fail:
|
|
return retval;
|
|
}
|