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-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJad5lgAAoJEFmIoMA60/r8s2kQAI3PztawDpaCP9Z12pkbBHSt Ho0xTyk9rCZi9kQJbNjc+a+QrlA3QmTHXIXerB3LSWoh7M+XhsECjem92eHpgLNS JvYPhTfOrCr0vdiAmOz6hD0AqN/psrbfzgiJhSwomsGEFS77k7kERSJckRv81sxb Aj5F/WjucAgLorwm4auveAJEQ7atE7/6pkXzoqYm4G6NLOb46jUcRGndrnvXZBlz fws8fBM4BHyi7i25CYQl24tFq1CGax1rIPgLg+4KnH76bQk/N6Ju0sGVSzfh+hG8 SIerK9bJbzGRAuNKoxB3aO1dyzsK3x9WztE2mG98w5trOISPIR1FqnvC/225FWAU d6eIXiC7wKnEx+DElNTzCjzfHc7SAJoupO32H7CoiTe5zPUlWlxJ1zLYkK1gt50q m8PRBiYTglxyznzrO0drtcdjEzvbdZNRrsYnul4wi1vSHzjk6F6XLtzT10XWM1M1 1pXLB8384FTj0Hu4bq6Y3Aivkmz0Sf+eQM2NaOwe+Zj7/1VV0d3lvi4LUXkqzLCA FoXPJSMxG2Qu+iflCeYRQBJjExaZH3eNLZ3dT6QpcJrjaFVedd9u5DeeFqNL27zV bhr8TdqrR4p4rc8EBAGoCapw96IxLZROKB3gxbrZVOpfIZpzthwHbElHX6aqUgF4 w/EV1JWs36WXWaxFk8wd =ttq9 -----END PGP SIGNATURE----- Merge tag 'pci-v4.16-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: - skip AER driver error recovery callbacks for correctable errors reported via ACPI APEI, as we already do for errors reported via the native path (Tyler Baicar) - fix DPC shared interrupt handling (Alex Williamson) - print full DPC interrupt number (Keith Busch) - enable DPC only if AER is available (Keith Busch) - simplify DPC code (Bjorn Helgaas) - calculate ASPM L1 substate parameter instead of hardcoding it (Bjorn Helgaas) - enable Latency Tolerance Reporting for ASPM L1 substates (Bjorn Helgaas) - move ASPM internal interfaces out of public header (Bjorn Helgaas) - allow hot-removal of VGA devices (Mika Westerberg) - speed up unplug and shutdown by assuming Thunderbolt controllers don't support Command Completed events (Lukas Wunner) - add AtomicOps support for GPU and Infiniband drivers (Felix Kuehling, Jay Cornwall) - expose "ari_enabled" in sysfs to help NIC naming (Stuart Hayes) - clean up PCI DMA interface usage (Christoph Hellwig) - remove PCI pool API (replaced with DMA pool) (Romain Perier) - deprecate pci_get_bus_and_slot(), which assumed PCI domain 0 (Sinan Kaya) - move DT PCI code from drivers/of/ to drivers/pci/ (Rob Herring) - add PCI-specific wrappers for dev_info(), etc (Frederick Lawler) - remove warnings on sysfs mmap failure (Bjorn Helgaas) - quiet ROM validation messages (Alex Deucher) - remove redundant memory alloc failure messages (Markus Elfring) - fill in types for compile-time VGA and other I/O port resources (Bjorn Helgaas) - make "pci=pcie_scan_all" work for Root Ports as well as Downstream Ports to help AmigaOne X1000 (Bjorn Helgaas) - add SPDX tags to all PCI files (Bjorn Helgaas) - quirk Marvell 9128 DMA aliases (Alex Williamson) - quirk broken INTx disable on Ceton InfiniTV4 (Bjorn Helgaas) - fix CONFIG_PCI=n build by adding dummy pci_irqd_intx_xlate() (Niklas Cassel) - use DMA API to get MSI address for DesignWare IP (Niklas Cassel) - fix endpoint-mode DMA mask configuration (Kishon Vijay Abraham I) - fix ARTPEC-6 incorrect IS_ERR() usage (Wei Yongjun) - add support for ARTPEC-7 SoC (Niklas Cassel) - add endpoint-mode support for ARTPEC (Niklas Cassel) - add Cadence PCIe host and endpoint controller driver (Cyrille Pitchen) - handle multiple INTx status bits being set in dra7xx (Vignesh R) - translate dra7xx hwirq range to fix INTD handling (Vignesh R) - remove deprecated Exynos PHY initialization code (Jaehoon Chung) - fix MSI erratum workaround for HiSilicon Hip06/Hip07 (Dongdong Liu) - fix NULL pointer dereference in iProc BCMA driver (Ray Jui) - fix Keystone interrupt-controller-node lookup (Johan Hovold) - constify qcom driver structures (Julia Lawall) - rework Tegra config space mapping to increase space available for endpoints (Vidya Sagar) - simplify Tegra driver by using bus->sysdata (Manikanta Maddireddy) - remove PCI_REASSIGN_ALL_BUS usage on Tegra (Manikanta Maddireddy) - add support for Global Fabric Manager Server (GFMS) event to Microsemi Switchtec switch driver (Logan Gunthorpe) - add IDs for Switchtec PSX 24xG3 and PSX 48xG3 (Kelvin Cao) * tag 'pci-v4.16-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (140 commits) PCI: cadence: Add EndPoint Controller driver for Cadence PCIe controller dt-bindings: PCI: cadence: Add DT bindings for Cadence PCIe endpoint controller PCI: endpoint: Fix EPF device name to support multi-function devices PCI: endpoint: Add the function number as argument to EPC ops PCI: cadence: Add host driver for Cadence PCIe controller dt-bindings: PCI: cadence: Add DT bindings for Cadence PCIe host controller PCI: Add vendor ID for Cadence PCI: Add generic function to probe PCI host controllers PCI: generic: fix missing call of pci_free_resource_list() PCI: OF: Add generic function to parse and allocate PCI resources PCI: Regroup all PCI related entries into drivers/pci/Makefile PCI/DPC: Reformat DPC register definitions PCI/DPC: Add and use DPC Status register field definitions PCI/DPC: Squash dpc_rp_pio_get_info() into dpc_process_rp_pio_error() PCI/DPC: Remove unnecessary RP PIO register structs PCI/DPC: Push dpc->rp_pio_status assignment into dpc_rp_pio_get_info() PCI/DPC: Squash dpc_rp_pio_print_error() into dpc_rp_pio_get_info() PCI/DPC: Make RP PIO log size check more generic PCI/DPC: Rename local "status" to "dpc_status" PCI/DPC: Squash dpc_rp_pio_print_tlp_header() into dpc_rp_pio_print_error() ...
810 lines
19 KiB
C
810 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* drivers/pci/iov.c
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*
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* Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
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*
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* PCI Express I/O Virtualization (IOV) support.
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* Single Root IOV 1.0
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* Address Translation Service 1.0
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*/
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/mutex.h>
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#include <linux/export.h>
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#include <linux/string.h>
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#include <linux/delay.h>
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#include <linux/pci-ats.h>
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#include "pci.h"
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#define VIRTFN_ID_LEN 16
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int pci_iov_virtfn_bus(struct pci_dev *dev, int vf_id)
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{
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if (!dev->is_physfn)
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return -EINVAL;
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return dev->bus->number + ((dev->devfn + dev->sriov->offset +
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dev->sriov->stride * vf_id) >> 8);
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}
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int pci_iov_virtfn_devfn(struct pci_dev *dev, int vf_id)
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{
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if (!dev->is_physfn)
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return -EINVAL;
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return (dev->devfn + dev->sriov->offset +
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dev->sriov->stride * vf_id) & 0xff;
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}
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/*
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* Per SR-IOV spec sec 3.3.10 and 3.3.11, First VF Offset and VF Stride may
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* change when NumVFs changes.
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*
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* Update iov->offset and iov->stride when NumVFs is written.
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*/
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static inline void pci_iov_set_numvfs(struct pci_dev *dev, int nr_virtfn)
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{
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struct pci_sriov *iov = dev->sriov;
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pci_write_config_word(dev, iov->pos + PCI_SRIOV_NUM_VF, nr_virtfn);
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pci_read_config_word(dev, iov->pos + PCI_SRIOV_VF_OFFSET, &iov->offset);
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pci_read_config_word(dev, iov->pos + PCI_SRIOV_VF_STRIDE, &iov->stride);
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}
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/*
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* The PF consumes one bus number. NumVFs, First VF Offset, and VF Stride
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* determine how many additional bus numbers will be consumed by VFs.
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*
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* Iterate over all valid NumVFs, validate offset and stride, and calculate
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* the maximum number of bus numbers that could ever be required.
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*/
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static int compute_max_vf_buses(struct pci_dev *dev)
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{
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struct pci_sriov *iov = dev->sriov;
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int nr_virtfn, busnr, rc = 0;
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for (nr_virtfn = iov->total_VFs; nr_virtfn; nr_virtfn--) {
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pci_iov_set_numvfs(dev, nr_virtfn);
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if (!iov->offset || (nr_virtfn > 1 && !iov->stride)) {
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rc = -EIO;
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goto out;
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}
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busnr = pci_iov_virtfn_bus(dev, nr_virtfn - 1);
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if (busnr > iov->max_VF_buses)
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iov->max_VF_buses = busnr;
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}
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out:
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pci_iov_set_numvfs(dev, 0);
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return rc;
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}
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static struct pci_bus *virtfn_add_bus(struct pci_bus *bus, int busnr)
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{
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struct pci_bus *child;
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if (bus->number == busnr)
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return bus;
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child = pci_find_bus(pci_domain_nr(bus), busnr);
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if (child)
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return child;
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child = pci_add_new_bus(bus, NULL, busnr);
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if (!child)
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return NULL;
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pci_bus_insert_busn_res(child, busnr, busnr);
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return child;
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}
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static void virtfn_remove_bus(struct pci_bus *physbus, struct pci_bus *virtbus)
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{
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if (physbus != virtbus && list_empty(&virtbus->devices))
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pci_remove_bus(virtbus);
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}
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resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
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{
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if (!dev->is_physfn)
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return 0;
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return dev->sriov->barsz[resno - PCI_IOV_RESOURCES];
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}
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int pci_iov_add_virtfn(struct pci_dev *dev, int id)
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{
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int i;
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int rc = -ENOMEM;
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u64 size;
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char buf[VIRTFN_ID_LEN];
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struct pci_dev *virtfn;
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struct resource *res;
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struct pci_sriov *iov = dev->sriov;
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struct pci_bus *bus;
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bus = virtfn_add_bus(dev->bus, pci_iov_virtfn_bus(dev, id));
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if (!bus)
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goto failed;
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virtfn = pci_alloc_dev(bus);
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if (!virtfn)
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goto failed0;
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virtfn->devfn = pci_iov_virtfn_devfn(dev, id);
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virtfn->vendor = dev->vendor;
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virtfn->device = iov->vf_device;
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rc = pci_setup_device(virtfn);
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if (rc)
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goto failed0;
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virtfn->dev.parent = dev->dev.parent;
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virtfn->physfn = pci_dev_get(dev);
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virtfn->is_virtfn = 1;
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virtfn->multifunction = 0;
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for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
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res = &dev->resource[i + PCI_IOV_RESOURCES];
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if (!res->parent)
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continue;
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virtfn->resource[i].name = pci_name(virtfn);
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virtfn->resource[i].flags = res->flags;
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size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
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virtfn->resource[i].start = res->start + size * id;
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virtfn->resource[i].end = virtfn->resource[i].start + size - 1;
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rc = request_resource(res, &virtfn->resource[i]);
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BUG_ON(rc);
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}
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pci_device_add(virtfn, virtfn->bus);
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sprintf(buf, "virtfn%u", id);
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rc = sysfs_create_link(&dev->dev.kobj, &virtfn->dev.kobj, buf);
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if (rc)
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goto failed1;
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rc = sysfs_create_link(&virtfn->dev.kobj, &dev->dev.kobj, "physfn");
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if (rc)
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goto failed2;
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kobject_uevent(&virtfn->dev.kobj, KOBJ_CHANGE);
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pci_bus_add_device(virtfn);
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return 0;
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failed2:
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sysfs_remove_link(&dev->dev.kobj, buf);
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failed1:
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pci_dev_put(dev);
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pci_stop_and_remove_bus_device(virtfn);
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failed0:
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virtfn_remove_bus(dev->bus, bus);
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failed:
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return rc;
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}
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void pci_iov_remove_virtfn(struct pci_dev *dev, int id)
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{
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char buf[VIRTFN_ID_LEN];
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struct pci_dev *virtfn;
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virtfn = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus),
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pci_iov_virtfn_bus(dev, id),
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pci_iov_virtfn_devfn(dev, id));
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if (!virtfn)
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return;
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sprintf(buf, "virtfn%u", id);
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sysfs_remove_link(&dev->dev.kobj, buf);
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/*
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* pci_stop_dev() could have been called for this virtfn already,
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* so the directory for the virtfn may have been removed before.
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* Double check to avoid spurious sysfs warnings.
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*/
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if (virtfn->dev.kobj.sd)
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sysfs_remove_link(&virtfn->dev.kobj, "physfn");
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pci_stop_and_remove_bus_device(virtfn);
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virtfn_remove_bus(dev->bus, virtfn->bus);
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/* balance pci_get_domain_bus_and_slot() */
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pci_dev_put(virtfn);
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pci_dev_put(dev);
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}
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int __weak pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
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{
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return 0;
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}
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int __weak pcibios_sriov_disable(struct pci_dev *pdev)
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{
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return 0;
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}
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static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
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{
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int rc;
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int i;
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int nres;
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u16 initial;
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struct resource *res;
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struct pci_dev *pdev;
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struct pci_sriov *iov = dev->sriov;
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int bars = 0;
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int bus;
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if (!nr_virtfn)
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return 0;
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if (iov->num_VFs)
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return -EINVAL;
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pci_read_config_word(dev, iov->pos + PCI_SRIOV_INITIAL_VF, &initial);
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if (initial > iov->total_VFs ||
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(!(iov->cap & PCI_SRIOV_CAP_VFM) && (initial != iov->total_VFs)))
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return -EIO;
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if (nr_virtfn < 0 || nr_virtfn > iov->total_VFs ||
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(!(iov->cap & PCI_SRIOV_CAP_VFM) && (nr_virtfn > initial)))
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return -EINVAL;
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nres = 0;
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for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
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bars |= (1 << (i + PCI_IOV_RESOURCES));
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res = &dev->resource[i + PCI_IOV_RESOURCES];
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if (res->parent)
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nres++;
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}
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if (nres != iov->nres) {
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pci_err(dev, "not enough MMIO resources for SR-IOV\n");
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return -ENOMEM;
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}
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bus = pci_iov_virtfn_bus(dev, nr_virtfn - 1);
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if (bus > dev->bus->busn_res.end) {
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pci_err(dev, "can't enable %d VFs (bus %02x out of range of %pR)\n",
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nr_virtfn, bus, &dev->bus->busn_res);
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return -ENOMEM;
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}
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if (pci_enable_resources(dev, bars)) {
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pci_err(dev, "SR-IOV: IOV BARS not allocated\n");
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return -ENOMEM;
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}
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if (iov->link != dev->devfn) {
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pdev = pci_get_slot(dev->bus, iov->link);
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if (!pdev)
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return -ENODEV;
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if (!pdev->is_physfn) {
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pci_dev_put(pdev);
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return -ENOSYS;
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}
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rc = sysfs_create_link(&dev->dev.kobj,
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&pdev->dev.kobj, "dep_link");
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pci_dev_put(pdev);
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if (rc)
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return rc;
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}
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iov->initial_VFs = initial;
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if (nr_virtfn < initial)
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initial = nr_virtfn;
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rc = pcibios_sriov_enable(dev, initial);
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if (rc) {
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pci_err(dev, "failure %d from pcibios_sriov_enable()\n", rc);
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goto err_pcibios;
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}
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pci_iov_set_numvfs(dev, nr_virtfn);
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iov->ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;
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pci_cfg_access_lock(dev);
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pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
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msleep(100);
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pci_cfg_access_unlock(dev);
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for (i = 0; i < initial; i++) {
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rc = pci_iov_add_virtfn(dev, i);
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if (rc)
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goto failed;
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}
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kobject_uevent(&dev->dev.kobj, KOBJ_CHANGE);
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iov->num_VFs = nr_virtfn;
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return 0;
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failed:
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while (i--)
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pci_iov_remove_virtfn(dev, i);
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err_pcibios:
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iov->ctrl &= ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE);
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pci_cfg_access_lock(dev);
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pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
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ssleep(1);
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pci_cfg_access_unlock(dev);
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pcibios_sriov_disable(dev);
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if (iov->link != dev->devfn)
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sysfs_remove_link(&dev->dev.kobj, "dep_link");
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pci_iov_set_numvfs(dev, 0);
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return rc;
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}
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static void sriov_disable(struct pci_dev *dev)
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{
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int i;
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struct pci_sriov *iov = dev->sriov;
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if (!iov->num_VFs)
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return;
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for (i = 0; i < iov->num_VFs; i++)
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pci_iov_remove_virtfn(dev, i);
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iov->ctrl &= ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE);
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pci_cfg_access_lock(dev);
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pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
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ssleep(1);
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pci_cfg_access_unlock(dev);
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pcibios_sriov_disable(dev);
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if (iov->link != dev->devfn)
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sysfs_remove_link(&dev->dev.kobj, "dep_link");
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iov->num_VFs = 0;
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pci_iov_set_numvfs(dev, 0);
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}
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static int sriov_init(struct pci_dev *dev, int pos)
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{
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int i, bar64;
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int rc;
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int nres;
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u32 pgsz;
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u16 ctrl, total;
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struct pci_sriov *iov;
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struct resource *res;
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struct pci_dev *pdev;
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pci_read_config_word(dev, pos + PCI_SRIOV_CTRL, &ctrl);
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if (ctrl & PCI_SRIOV_CTRL_VFE) {
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pci_write_config_word(dev, pos + PCI_SRIOV_CTRL, 0);
|
|
ssleep(1);
|
|
}
|
|
|
|
ctrl = 0;
|
|
list_for_each_entry(pdev, &dev->bus->devices, bus_list)
|
|
if (pdev->is_physfn)
|
|
goto found;
|
|
|
|
pdev = NULL;
|
|
if (pci_ari_enabled(dev->bus))
|
|
ctrl |= PCI_SRIOV_CTRL_ARI;
|
|
|
|
found:
|
|
pci_write_config_word(dev, pos + PCI_SRIOV_CTRL, ctrl);
|
|
|
|
pci_read_config_word(dev, pos + PCI_SRIOV_TOTAL_VF, &total);
|
|
if (!total)
|
|
return 0;
|
|
|
|
pci_read_config_dword(dev, pos + PCI_SRIOV_SUP_PGSIZE, &pgsz);
|
|
i = PAGE_SHIFT > 12 ? PAGE_SHIFT - 12 : 0;
|
|
pgsz &= ~((1 << i) - 1);
|
|
if (!pgsz)
|
|
return -EIO;
|
|
|
|
pgsz &= ~(pgsz - 1);
|
|
pci_write_config_dword(dev, pos + PCI_SRIOV_SYS_PGSIZE, pgsz);
|
|
|
|
iov = kzalloc(sizeof(*iov), GFP_KERNEL);
|
|
if (!iov)
|
|
return -ENOMEM;
|
|
|
|
nres = 0;
|
|
for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
|
|
res = &dev->resource[i + PCI_IOV_RESOURCES];
|
|
/*
|
|
* If it is already FIXED, don't change it, something
|
|
* (perhaps EA or header fixups) wants it this way.
|
|
*/
|
|
if (res->flags & IORESOURCE_PCI_FIXED)
|
|
bar64 = (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
|
|
else
|
|
bar64 = __pci_read_base(dev, pci_bar_unknown, res,
|
|
pos + PCI_SRIOV_BAR + i * 4);
|
|
if (!res->flags)
|
|
continue;
|
|
if (resource_size(res) & (PAGE_SIZE - 1)) {
|
|
rc = -EIO;
|
|
goto failed;
|
|
}
|
|
iov->barsz[i] = resource_size(res);
|
|
res->end = res->start + resource_size(res) * total - 1;
|
|
pci_info(dev, "VF(n) BAR%d space: %pR (contains BAR%d for %d VFs)\n",
|
|
i, res, i, total);
|
|
i += bar64;
|
|
nres++;
|
|
}
|
|
|
|
iov->pos = pos;
|
|
iov->nres = nres;
|
|
iov->ctrl = ctrl;
|
|
iov->total_VFs = total;
|
|
pci_read_config_word(dev, pos + PCI_SRIOV_VF_DID, &iov->vf_device);
|
|
iov->pgsz = pgsz;
|
|
iov->self = dev;
|
|
iov->drivers_autoprobe = true;
|
|
pci_read_config_dword(dev, pos + PCI_SRIOV_CAP, &iov->cap);
|
|
pci_read_config_byte(dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link);
|
|
if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END)
|
|
iov->link = PCI_DEVFN(PCI_SLOT(dev->devfn), iov->link);
|
|
|
|
if (pdev)
|
|
iov->dev = pci_dev_get(pdev);
|
|
else
|
|
iov->dev = dev;
|
|
|
|
dev->sriov = iov;
|
|
dev->is_physfn = 1;
|
|
rc = compute_max_vf_buses(dev);
|
|
if (rc)
|
|
goto fail_max_buses;
|
|
|
|
return 0;
|
|
|
|
fail_max_buses:
|
|
dev->sriov = NULL;
|
|
dev->is_physfn = 0;
|
|
failed:
|
|
for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
|
|
res = &dev->resource[i + PCI_IOV_RESOURCES];
|
|
res->flags = 0;
|
|
}
|
|
|
|
kfree(iov);
|
|
return rc;
|
|
}
|
|
|
|
static void sriov_release(struct pci_dev *dev)
|
|
{
|
|
BUG_ON(dev->sriov->num_VFs);
|
|
|
|
if (dev != dev->sriov->dev)
|
|
pci_dev_put(dev->sriov->dev);
|
|
|
|
kfree(dev->sriov);
|
|
dev->sriov = NULL;
|
|
}
|
|
|
|
static void sriov_restore_state(struct pci_dev *dev)
|
|
{
|
|
int i;
|
|
u16 ctrl;
|
|
struct pci_sriov *iov = dev->sriov;
|
|
|
|
pci_read_config_word(dev, iov->pos + PCI_SRIOV_CTRL, &ctrl);
|
|
if (ctrl & PCI_SRIOV_CTRL_VFE)
|
|
return;
|
|
|
|
/*
|
|
* Restore PCI_SRIOV_CTRL_ARI before pci_iov_set_numvfs() because
|
|
* it reads offset & stride, which depend on PCI_SRIOV_CTRL_ARI.
|
|
*/
|
|
ctrl &= ~PCI_SRIOV_CTRL_ARI;
|
|
ctrl |= iov->ctrl & PCI_SRIOV_CTRL_ARI;
|
|
pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, ctrl);
|
|
|
|
for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++)
|
|
pci_update_resource(dev, i);
|
|
|
|
pci_write_config_dword(dev, iov->pos + PCI_SRIOV_SYS_PGSIZE, iov->pgsz);
|
|
pci_iov_set_numvfs(dev, iov->num_VFs);
|
|
pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
|
|
if (iov->ctrl & PCI_SRIOV_CTRL_VFE)
|
|
msleep(100);
|
|
}
|
|
|
|
/**
|
|
* pci_iov_init - initialize the IOV capability
|
|
* @dev: the PCI device
|
|
*
|
|
* Returns 0 on success, or negative on failure.
|
|
*/
|
|
int pci_iov_init(struct pci_dev *dev)
|
|
{
|
|
int pos;
|
|
|
|
if (!pci_is_pcie(dev))
|
|
return -ENODEV;
|
|
|
|
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
|
|
if (pos)
|
|
return sriov_init(dev, pos);
|
|
|
|
return -ENODEV;
|
|
}
|
|
|
|
/**
|
|
* pci_iov_release - release resources used by the IOV capability
|
|
* @dev: the PCI device
|
|
*/
|
|
void pci_iov_release(struct pci_dev *dev)
|
|
{
|
|
if (dev->is_physfn)
|
|
sriov_release(dev);
|
|
}
|
|
|
|
/**
|
|
* pci_iov_update_resource - update a VF BAR
|
|
* @dev: the PCI device
|
|
* @resno: the resource number
|
|
*
|
|
* Update a VF BAR in the SR-IOV capability of a PF.
|
|
*/
|
|
void pci_iov_update_resource(struct pci_dev *dev, int resno)
|
|
{
|
|
struct pci_sriov *iov = dev->is_physfn ? dev->sriov : NULL;
|
|
struct resource *res = dev->resource + resno;
|
|
int vf_bar = resno - PCI_IOV_RESOURCES;
|
|
struct pci_bus_region region;
|
|
u16 cmd;
|
|
u32 new;
|
|
int reg;
|
|
|
|
/*
|
|
* The generic pci_restore_bars() path calls this for all devices,
|
|
* including VFs and non-SR-IOV devices. If this is not a PF, we
|
|
* have nothing to do.
|
|
*/
|
|
if (!iov)
|
|
return;
|
|
|
|
pci_read_config_word(dev, iov->pos + PCI_SRIOV_CTRL, &cmd);
|
|
if ((cmd & PCI_SRIOV_CTRL_VFE) && (cmd & PCI_SRIOV_CTRL_MSE)) {
|
|
dev_WARN(&dev->dev, "can't update enabled VF BAR%d %pR\n",
|
|
vf_bar, res);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Ignore unimplemented BARs, unused resource slots for 64-bit
|
|
* BARs, and non-movable resources, e.g., those described via
|
|
* Enhanced Allocation.
|
|
*/
|
|
if (!res->flags)
|
|
return;
|
|
|
|
if (res->flags & IORESOURCE_UNSET)
|
|
return;
|
|
|
|
if (res->flags & IORESOURCE_PCI_FIXED)
|
|
return;
|
|
|
|
pcibios_resource_to_bus(dev->bus, ®ion, res);
|
|
new = region.start;
|
|
new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK;
|
|
|
|
reg = iov->pos + PCI_SRIOV_BAR + 4 * vf_bar;
|
|
pci_write_config_dword(dev, reg, new);
|
|
if (res->flags & IORESOURCE_MEM_64) {
|
|
new = region.start >> 16 >> 16;
|
|
pci_write_config_dword(dev, reg + 4, new);
|
|
}
|
|
}
|
|
|
|
resource_size_t __weak pcibios_iov_resource_alignment(struct pci_dev *dev,
|
|
int resno)
|
|
{
|
|
return pci_iov_resource_size(dev, resno);
|
|
}
|
|
|
|
/**
|
|
* pci_sriov_resource_alignment - get resource alignment for VF BAR
|
|
* @dev: the PCI device
|
|
* @resno: the resource number
|
|
*
|
|
* Returns the alignment of the VF BAR found in the SR-IOV capability.
|
|
* This is not the same as the resource size which is defined as
|
|
* the VF BAR size multiplied by the number of VFs. The alignment
|
|
* is just the VF BAR size.
|
|
*/
|
|
resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno)
|
|
{
|
|
return pcibios_iov_resource_alignment(dev, resno);
|
|
}
|
|
|
|
/**
|
|
* pci_restore_iov_state - restore the state of the IOV capability
|
|
* @dev: the PCI device
|
|
*/
|
|
void pci_restore_iov_state(struct pci_dev *dev)
|
|
{
|
|
if (dev->is_physfn)
|
|
sriov_restore_state(dev);
|
|
}
|
|
|
|
/**
|
|
* pci_vf_drivers_autoprobe - set PF property drivers_autoprobe for VFs
|
|
* @dev: the PCI device
|
|
* @auto_probe: set VF drivers auto probe flag
|
|
*/
|
|
void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool auto_probe)
|
|
{
|
|
if (dev->is_physfn)
|
|
dev->sriov->drivers_autoprobe = auto_probe;
|
|
}
|
|
|
|
/**
|
|
* pci_iov_bus_range - find bus range used by Virtual Function
|
|
* @bus: the PCI bus
|
|
*
|
|
* Returns max number of buses (exclude current one) used by Virtual
|
|
* Functions.
|
|
*/
|
|
int pci_iov_bus_range(struct pci_bus *bus)
|
|
{
|
|
int max = 0;
|
|
struct pci_dev *dev;
|
|
|
|
list_for_each_entry(dev, &bus->devices, bus_list) {
|
|
if (!dev->is_physfn)
|
|
continue;
|
|
if (dev->sriov->max_VF_buses > max)
|
|
max = dev->sriov->max_VF_buses;
|
|
}
|
|
|
|
return max ? max - bus->number : 0;
|
|
}
|
|
|
|
/**
|
|
* pci_enable_sriov - enable the SR-IOV capability
|
|
* @dev: the PCI device
|
|
* @nr_virtfn: number of virtual functions to enable
|
|
*
|
|
* Returns 0 on success, or negative on failure.
|
|
*/
|
|
int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
|
|
{
|
|
might_sleep();
|
|
|
|
if (!dev->is_physfn)
|
|
return -ENOSYS;
|
|
|
|
return sriov_enable(dev, nr_virtfn);
|
|
}
|
|
EXPORT_SYMBOL_GPL(pci_enable_sriov);
|
|
|
|
/**
|
|
* pci_disable_sriov - disable the SR-IOV capability
|
|
* @dev: the PCI device
|
|
*/
|
|
void pci_disable_sriov(struct pci_dev *dev)
|
|
{
|
|
might_sleep();
|
|
|
|
if (!dev->is_physfn)
|
|
return;
|
|
|
|
sriov_disable(dev);
|
|
}
|
|
EXPORT_SYMBOL_GPL(pci_disable_sriov);
|
|
|
|
/**
|
|
* pci_num_vf - return number of VFs associated with a PF device_release_driver
|
|
* @dev: the PCI device
|
|
*
|
|
* Returns number of VFs, or 0 if SR-IOV is not enabled.
|
|
*/
|
|
int pci_num_vf(struct pci_dev *dev)
|
|
{
|
|
if (!dev->is_physfn)
|
|
return 0;
|
|
|
|
return dev->sriov->num_VFs;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pci_num_vf);
|
|
|
|
/**
|
|
* pci_vfs_assigned - returns number of VFs are assigned to a guest
|
|
* @dev: the PCI device
|
|
*
|
|
* Returns number of VFs belonging to this device that are assigned to a guest.
|
|
* If device is not a physical function returns 0.
|
|
*/
|
|
int pci_vfs_assigned(struct pci_dev *dev)
|
|
{
|
|
struct pci_dev *vfdev;
|
|
unsigned int vfs_assigned = 0;
|
|
unsigned short dev_id;
|
|
|
|
/* only search if we are a PF */
|
|
if (!dev->is_physfn)
|
|
return 0;
|
|
|
|
/*
|
|
* determine the device ID for the VFs, the vendor ID will be the
|
|
* same as the PF so there is no need to check for that one
|
|
*/
|
|
dev_id = dev->sriov->vf_device;
|
|
|
|
/* loop through all the VFs to see if we own any that are assigned */
|
|
vfdev = pci_get_device(dev->vendor, dev_id, NULL);
|
|
while (vfdev) {
|
|
/*
|
|
* It is considered assigned if it is a virtual function with
|
|
* our dev as the physical function and the assigned bit is set
|
|
*/
|
|
if (vfdev->is_virtfn && (vfdev->physfn == dev) &&
|
|
pci_is_dev_assigned(vfdev))
|
|
vfs_assigned++;
|
|
|
|
vfdev = pci_get_device(dev->vendor, dev_id, vfdev);
|
|
}
|
|
|
|
return vfs_assigned;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pci_vfs_assigned);
|
|
|
|
/**
|
|
* pci_sriov_set_totalvfs -- reduce the TotalVFs available
|
|
* @dev: the PCI PF device
|
|
* @numvfs: number that should be used for TotalVFs supported
|
|
*
|
|
* Should be called from PF driver's probe routine with
|
|
* device's mutex held.
|
|
*
|
|
* Returns 0 if PF is an SRIOV-capable device and
|
|
* value of numvfs valid. If not a PF return -ENOSYS;
|
|
* if numvfs is invalid return -EINVAL;
|
|
* if VFs already enabled, return -EBUSY.
|
|
*/
|
|
int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
|
|
{
|
|
if (!dev->is_physfn)
|
|
return -ENOSYS;
|
|
if (numvfs > dev->sriov->total_VFs)
|
|
return -EINVAL;
|
|
|
|
/* Shouldn't change if VFs already enabled */
|
|
if (dev->sriov->ctrl & PCI_SRIOV_CTRL_VFE)
|
|
return -EBUSY;
|
|
else
|
|
dev->sriov->driver_max_VFs = numvfs;
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pci_sriov_set_totalvfs);
|
|
|
|
/**
|
|
* pci_sriov_get_totalvfs -- get total VFs supported on this device
|
|
* @dev: the PCI PF device
|
|
*
|
|
* For a PCIe device with SRIOV support, return the PCIe
|
|
* SRIOV capability value of TotalVFs or the value of driver_max_VFs
|
|
* if the driver reduced it. Otherwise 0.
|
|
*/
|
|
int pci_sriov_get_totalvfs(struct pci_dev *dev)
|
|
{
|
|
if (!dev->is_physfn)
|
|
return 0;
|
|
|
|
if (dev->sriov->driver_max_VFs)
|
|
return dev->sriov->driver_max_VFs;
|
|
|
|
return dev->sriov->total_VFs;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pci_sriov_get_totalvfs);
|