![stephen hemminger](/assets/img/avatar_default.png)
The network device operation for reading statistics is only called in one place, and it ignores the return value. Having a structure return value is potentially confusing because some future driver could incorrectly assume that the return value was used. Fix all drivers with ndo_get_stats64 to have a void function. Signed-off-by: Stephen Hemminger <sthemmin@microsoft.com> Signed-off-by: David S. Miller <davem@davemloft.net>
610 lines
14 KiB
C
610 lines
14 KiB
C
/*
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* drivers/net/ethernet/ec_bhf.c
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*
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* Copyright (C) 2014 Darek Marcinkiewicz <reksio@newterm.pl>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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/* This is a driver for EtherCAT master module present on CCAT FPGA.
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* Those can be found on Bechhoff CX50xx industrial PCs.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/ip.h>
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#include <linux/skbuff.h>
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#include <linux/hrtimer.h>
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#include <linux/interrupt.h>
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#include <linux/stat.h>
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#define TIMER_INTERVAL_NSEC 20000
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#define INFO_BLOCK_SIZE 0x10
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#define INFO_BLOCK_TYPE 0x0
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#define INFO_BLOCK_REV 0x2
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#define INFO_BLOCK_BLK_CNT 0x4
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#define INFO_BLOCK_TX_CHAN 0x4
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#define INFO_BLOCK_RX_CHAN 0x5
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#define INFO_BLOCK_OFFSET 0x8
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#define EC_MII_OFFSET 0x4
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#define EC_FIFO_OFFSET 0x8
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#define EC_MAC_OFFSET 0xc
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#define MAC_FRAME_ERR_CNT 0x0
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#define MAC_RX_ERR_CNT 0x1
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#define MAC_CRC_ERR_CNT 0x2
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#define MAC_LNK_LST_ERR_CNT 0x3
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#define MAC_TX_FRAME_CNT 0x10
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#define MAC_RX_FRAME_CNT 0x14
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#define MAC_TX_FIFO_LVL 0x20
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#define MAC_DROPPED_FRMS 0x28
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#define MAC_CONNECTED_CCAT_FLAG 0x78
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#define MII_MAC_ADDR 0x8
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#define MII_MAC_FILT_FLAG 0xe
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#define MII_LINK_STATUS 0xf
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#define FIFO_TX_REG 0x0
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#define FIFO_TX_RESET 0x8
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#define FIFO_RX_REG 0x10
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#define FIFO_RX_ADDR_VALID (1u << 31)
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#define FIFO_RX_RESET 0x18
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#define DMA_CHAN_OFFSET 0x1000
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#define DMA_CHAN_SIZE 0x8
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#define DMA_WINDOW_SIZE_MASK 0xfffffffc
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#define ETHERCAT_MASTER_ID 0x14
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static struct pci_device_id ids[] = {
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{ PCI_DEVICE(0x15ec, 0x5000), },
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{ 0, }
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};
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MODULE_DEVICE_TABLE(pci, ids);
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struct rx_header {
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#define RXHDR_NEXT_ADDR_MASK 0xffffffu
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#define RXHDR_NEXT_VALID (1u << 31)
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__le32 next;
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#define RXHDR_NEXT_RECV_FLAG 0x1
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__le32 recv;
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#define RXHDR_LEN_MASK 0xfffu
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__le16 len;
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__le16 port;
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__le32 reserved;
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u8 timestamp[8];
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} __packed;
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#define PKT_PAYLOAD_SIZE 0x7e8
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struct rx_desc {
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struct rx_header header;
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u8 data[PKT_PAYLOAD_SIZE];
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} __packed;
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struct tx_header {
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__le16 len;
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#define TX_HDR_PORT_0 0x1
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#define TX_HDR_PORT_1 0x2
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u8 port;
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u8 ts_enable;
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#define TX_HDR_SENT 0x1
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__le32 sent;
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u8 timestamp[8];
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} __packed;
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struct tx_desc {
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struct tx_header header;
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u8 data[PKT_PAYLOAD_SIZE];
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} __packed;
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#define FIFO_SIZE 64
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static long polling_frequency = TIMER_INTERVAL_NSEC;
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struct bhf_dma {
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u8 *buf;
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size_t len;
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dma_addr_t buf_phys;
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u8 *alloc;
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size_t alloc_len;
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dma_addr_t alloc_phys;
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};
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struct ec_bhf_priv {
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struct net_device *net_dev;
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struct pci_dev *dev;
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void __iomem *io;
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void __iomem *dma_io;
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struct hrtimer hrtimer;
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int tx_dma_chan;
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int rx_dma_chan;
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void __iomem *ec_io;
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void __iomem *fifo_io;
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void __iomem *mii_io;
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void __iomem *mac_io;
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struct bhf_dma rx_buf;
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struct rx_desc *rx_descs;
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int rx_dnext;
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int rx_dcount;
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struct bhf_dma tx_buf;
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struct tx_desc *tx_descs;
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int tx_dcount;
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int tx_dnext;
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u64 stat_rx_bytes;
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u64 stat_tx_bytes;
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};
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#define PRIV_TO_DEV(priv) (&(priv)->dev->dev)
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static void ec_bhf_reset(struct ec_bhf_priv *priv)
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{
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iowrite8(0, priv->mac_io + MAC_FRAME_ERR_CNT);
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iowrite8(0, priv->mac_io + MAC_RX_ERR_CNT);
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iowrite8(0, priv->mac_io + MAC_CRC_ERR_CNT);
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iowrite8(0, priv->mac_io + MAC_LNK_LST_ERR_CNT);
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iowrite32(0, priv->mac_io + MAC_TX_FRAME_CNT);
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iowrite32(0, priv->mac_io + MAC_RX_FRAME_CNT);
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iowrite8(0, priv->mac_io + MAC_DROPPED_FRMS);
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iowrite8(0, priv->fifo_io + FIFO_TX_RESET);
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iowrite8(0, priv->fifo_io + FIFO_RX_RESET);
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iowrite8(0, priv->mac_io + MAC_TX_FIFO_LVL);
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}
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static void ec_bhf_send_packet(struct ec_bhf_priv *priv, struct tx_desc *desc)
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{
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u32 len = le16_to_cpu(desc->header.len) + sizeof(desc->header);
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u32 addr = (u8 *)desc - priv->tx_buf.buf;
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iowrite32((ALIGN(len, 8) << 24) | addr, priv->fifo_io + FIFO_TX_REG);
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}
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static int ec_bhf_desc_sent(struct tx_desc *desc)
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{
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return le32_to_cpu(desc->header.sent) & TX_HDR_SENT;
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}
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static void ec_bhf_process_tx(struct ec_bhf_priv *priv)
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{
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if (unlikely(netif_queue_stopped(priv->net_dev))) {
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/* Make sure that we perceive changes to tx_dnext. */
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smp_rmb();
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if (ec_bhf_desc_sent(&priv->tx_descs[priv->tx_dnext]))
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netif_wake_queue(priv->net_dev);
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}
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}
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static int ec_bhf_pkt_received(struct rx_desc *desc)
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{
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return le32_to_cpu(desc->header.recv) & RXHDR_NEXT_RECV_FLAG;
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}
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static void ec_bhf_add_rx_desc(struct ec_bhf_priv *priv, struct rx_desc *desc)
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{
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iowrite32(FIFO_RX_ADDR_VALID | ((u8 *)(desc) - priv->rx_buf.buf),
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priv->fifo_io + FIFO_RX_REG);
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}
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static void ec_bhf_process_rx(struct ec_bhf_priv *priv)
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{
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struct rx_desc *desc = &priv->rx_descs[priv->rx_dnext];
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while (ec_bhf_pkt_received(desc)) {
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int pkt_size = (le16_to_cpu(desc->header.len) &
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RXHDR_LEN_MASK) - sizeof(struct rx_header) - 4;
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u8 *data = desc->data;
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struct sk_buff *skb;
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skb = netdev_alloc_skb_ip_align(priv->net_dev, pkt_size);
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if (skb) {
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memcpy(skb_put(skb, pkt_size), data, pkt_size);
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skb->protocol = eth_type_trans(skb, priv->net_dev);
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priv->stat_rx_bytes += pkt_size;
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netif_rx(skb);
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} else {
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dev_err_ratelimited(PRIV_TO_DEV(priv),
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"Couldn't allocate a skb_buff for a packet of size %u\n",
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pkt_size);
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}
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desc->header.recv = 0;
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ec_bhf_add_rx_desc(priv, desc);
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priv->rx_dnext = (priv->rx_dnext + 1) % priv->rx_dcount;
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desc = &priv->rx_descs[priv->rx_dnext];
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}
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}
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static enum hrtimer_restart ec_bhf_timer_fun(struct hrtimer *timer)
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{
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struct ec_bhf_priv *priv = container_of(timer, struct ec_bhf_priv,
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hrtimer);
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ec_bhf_process_rx(priv);
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ec_bhf_process_tx(priv);
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if (!netif_running(priv->net_dev))
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return HRTIMER_NORESTART;
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hrtimer_forward_now(timer, polling_frequency);
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return HRTIMER_RESTART;
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}
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static int ec_bhf_setup_offsets(struct ec_bhf_priv *priv)
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{
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struct device *dev = PRIV_TO_DEV(priv);
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unsigned block_count, i;
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void __iomem *ec_info;
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block_count = ioread8(priv->io + INFO_BLOCK_BLK_CNT);
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for (i = 0; i < block_count; i++) {
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u16 type = ioread16(priv->io + i * INFO_BLOCK_SIZE +
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INFO_BLOCK_TYPE);
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if (type == ETHERCAT_MASTER_ID)
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break;
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}
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if (i == block_count) {
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dev_err(dev, "EtherCAT master with DMA block not found\n");
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return -ENODEV;
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}
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ec_info = priv->io + i * INFO_BLOCK_SIZE;
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priv->tx_dma_chan = ioread8(ec_info + INFO_BLOCK_TX_CHAN);
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priv->rx_dma_chan = ioread8(ec_info + INFO_BLOCK_RX_CHAN);
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priv->ec_io = priv->io + ioread32(ec_info + INFO_BLOCK_OFFSET);
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priv->mii_io = priv->ec_io + ioread32(priv->ec_io + EC_MII_OFFSET);
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priv->fifo_io = priv->ec_io + ioread32(priv->ec_io + EC_FIFO_OFFSET);
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priv->mac_io = priv->ec_io + ioread32(priv->ec_io + EC_MAC_OFFSET);
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return 0;
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}
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static netdev_tx_t ec_bhf_start_xmit(struct sk_buff *skb,
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struct net_device *net_dev)
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{
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struct ec_bhf_priv *priv = netdev_priv(net_dev);
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struct tx_desc *desc;
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unsigned len;
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desc = &priv->tx_descs[priv->tx_dnext];
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skb_copy_and_csum_dev(skb, desc->data);
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len = skb->len;
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memset(&desc->header, 0, sizeof(desc->header));
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desc->header.len = cpu_to_le16(len);
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desc->header.port = TX_HDR_PORT_0;
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ec_bhf_send_packet(priv, desc);
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priv->tx_dnext = (priv->tx_dnext + 1) % priv->tx_dcount;
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if (!ec_bhf_desc_sent(&priv->tx_descs[priv->tx_dnext])) {
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/* Make sure that updates to tx_dnext are perceived
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* by timer routine.
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*/
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smp_wmb();
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netif_stop_queue(net_dev);
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}
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priv->stat_tx_bytes += len;
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dev_kfree_skb(skb);
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return NETDEV_TX_OK;
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}
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static int ec_bhf_alloc_dma_mem(struct ec_bhf_priv *priv,
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struct bhf_dma *buf,
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int channel,
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int size)
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{
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int offset = channel * DMA_CHAN_SIZE + DMA_CHAN_OFFSET;
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struct device *dev = PRIV_TO_DEV(priv);
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u32 mask;
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iowrite32(0xffffffff, priv->dma_io + offset);
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mask = ioread32(priv->dma_io + offset);
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mask &= DMA_WINDOW_SIZE_MASK;
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/* We want to allocate a chunk of memory that is:
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* - aligned to the mask we just read
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* - is of size 2^mask bytes (at most)
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* In order to ensure that we will allocate buffer of
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* 2 * 2^mask bytes.
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*/
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buf->len = min_t(int, ~mask + 1, size);
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buf->alloc_len = 2 * buf->len;
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buf->alloc = dma_alloc_coherent(dev, buf->alloc_len, &buf->alloc_phys,
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GFP_KERNEL);
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if (buf->alloc == NULL) {
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dev_err(dev, "Failed to allocate buffer\n");
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return -ENOMEM;
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}
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buf->buf_phys = (buf->alloc_phys + buf->len) & mask;
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buf->buf = buf->alloc + (buf->buf_phys - buf->alloc_phys);
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iowrite32(0, priv->dma_io + offset + 4);
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iowrite32(buf->buf_phys, priv->dma_io + offset);
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return 0;
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}
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static void ec_bhf_setup_tx_descs(struct ec_bhf_priv *priv)
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{
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int i = 0;
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priv->tx_dcount = priv->tx_buf.len / sizeof(struct tx_desc);
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priv->tx_descs = (struct tx_desc *)priv->tx_buf.buf;
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priv->tx_dnext = 0;
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for (i = 0; i < priv->tx_dcount; i++)
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priv->tx_descs[i].header.sent = cpu_to_le32(TX_HDR_SENT);
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}
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static void ec_bhf_setup_rx_descs(struct ec_bhf_priv *priv)
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{
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int i;
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priv->rx_dcount = priv->rx_buf.len / sizeof(struct rx_desc);
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priv->rx_descs = (struct rx_desc *)priv->rx_buf.buf;
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priv->rx_dnext = 0;
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for (i = 0; i < priv->rx_dcount; i++) {
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struct rx_desc *desc = &priv->rx_descs[i];
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u32 next;
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if (i != priv->rx_dcount - 1)
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next = (u8 *)(desc + 1) - priv->rx_buf.buf;
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else
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next = 0;
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next |= RXHDR_NEXT_VALID;
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desc->header.next = cpu_to_le32(next);
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desc->header.recv = 0;
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ec_bhf_add_rx_desc(priv, desc);
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}
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}
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static int ec_bhf_open(struct net_device *net_dev)
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{
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struct ec_bhf_priv *priv = netdev_priv(net_dev);
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struct device *dev = PRIV_TO_DEV(priv);
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int err = 0;
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ec_bhf_reset(priv);
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err = ec_bhf_alloc_dma_mem(priv, &priv->rx_buf, priv->rx_dma_chan,
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FIFO_SIZE * sizeof(struct rx_desc));
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if (err) {
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dev_err(dev, "Failed to allocate rx buffer\n");
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goto out;
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}
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ec_bhf_setup_rx_descs(priv);
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err = ec_bhf_alloc_dma_mem(priv, &priv->tx_buf, priv->tx_dma_chan,
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FIFO_SIZE * sizeof(struct tx_desc));
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if (err) {
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dev_err(dev, "Failed to allocate tx buffer\n");
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goto error_rx_free;
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}
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iowrite8(0, priv->mii_io + MII_MAC_FILT_FLAG);
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ec_bhf_setup_tx_descs(priv);
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netif_start_queue(net_dev);
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hrtimer_init(&priv->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
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priv->hrtimer.function = ec_bhf_timer_fun;
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hrtimer_start(&priv->hrtimer, polling_frequency, HRTIMER_MODE_REL);
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return 0;
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error_rx_free:
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dma_free_coherent(dev, priv->rx_buf.alloc_len, priv->rx_buf.alloc,
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priv->rx_buf.alloc_len);
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out:
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return err;
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}
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static int ec_bhf_stop(struct net_device *net_dev)
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{
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struct ec_bhf_priv *priv = netdev_priv(net_dev);
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struct device *dev = PRIV_TO_DEV(priv);
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hrtimer_cancel(&priv->hrtimer);
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ec_bhf_reset(priv);
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netif_tx_disable(net_dev);
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dma_free_coherent(dev, priv->tx_buf.alloc_len,
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priv->tx_buf.alloc, priv->tx_buf.alloc_phys);
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dma_free_coherent(dev, priv->rx_buf.alloc_len,
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priv->rx_buf.alloc, priv->rx_buf.alloc_phys);
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return 0;
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}
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static void
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ec_bhf_get_stats(struct net_device *net_dev,
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struct rtnl_link_stats64 *stats)
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{
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struct ec_bhf_priv *priv = netdev_priv(net_dev);
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stats->rx_errors = ioread8(priv->mac_io + MAC_RX_ERR_CNT) +
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ioread8(priv->mac_io + MAC_CRC_ERR_CNT) +
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ioread8(priv->mac_io + MAC_FRAME_ERR_CNT);
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stats->rx_packets = ioread32(priv->mac_io + MAC_RX_FRAME_CNT);
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stats->tx_packets = ioread32(priv->mac_io + MAC_TX_FRAME_CNT);
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stats->rx_dropped = ioread8(priv->mac_io + MAC_DROPPED_FRMS);
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stats->tx_bytes = priv->stat_tx_bytes;
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stats->rx_bytes = priv->stat_rx_bytes;
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}
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static const struct net_device_ops ec_bhf_netdev_ops = {
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.ndo_start_xmit = ec_bhf_start_xmit,
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.ndo_open = ec_bhf_open,
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.ndo_stop = ec_bhf_stop,
|
|
.ndo_get_stats64 = ec_bhf_get_stats,
|
|
.ndo_validate_addr = eth_validate_addr,
|
|
.ndo_set_mac_address = eth_mac_addr
|
|
};
|
|
|
|
static int ec_bhf_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
|
{
|
|
struct net_device *net_dev;
|
|
struct ec_bhf_priv *priv;
|
|
void __iomem *dma_io;
|
|
void __iomem *io;
|
|
int err = 0;
|
|
|
|
err = pci_enable_device(dev);
|
|
if (err)
|
|
return err;
|
|
|
|
pci_set_master(dev);
|
|
|
|
err = pci_set_dma_mask(dev, DMA_BIT_MASK(32));
|
|
if (err) {
|
|
dev_err(&dev->dev,
|
|
"Required dma mask not supported, failed to initialize device\n");
|
|
err = -EIO;
|
|
goto err_disable_dev;
|
|
}
|
|
|
|
err = pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(32));
|
|
if (err) {
|
|
dev_err(&dev->dev,
|
|
"Required dma mask not supported, failed to initialize device\n");
|
|
goto err_disable_dev;
|
|
}
|
|
|
|
err = pci_request_regions(dev, "ec_bhf");
|
|
if (err) {
|
|
dev_err(&dev->dev, "Failed to request pci memory regions\n");
|
|
goto err_disable_dev;
|
|
}
|
|
|
|
io = pci_iomap(dev, 0, 0);
|
|
if (!io) {
|
|
dev_err(&dev->dev, "Failed to map pci card memory bar 0");
|
|
err = -EIO;
|
|
goto err_release_regions;
|
|
}
|
|
|
|
dma_io = pci_iomap(dev, 2, 0);
|
|
if (!dma_io) {
|
|
dev_err(&dev->dev, "Failed to map pci card memory bar 2");
|
|
err = -EIO;
|
|
goto err_unmap;
|
|
}
|
|
|
|
net_dev = alloc_etherdev(sizeof(struct ec_bhf_priv));
|
|
if (net_dev == NULL) {
|
|
err = -ENOMEM;
|
|
goto err_unmap_dma_io;
|
|
}
|
|
|
|
pci_set_drvdata(dev, net_dev);
|
|
SET_NETDEV_DEV(net_dev, &dev->dev);
|
|
|
|
net_dev->features = 0;
|
|
net_dev->flags |= IFF_NOARP;
|
|
|
|
net_dev->netdev_ops = &ec_bhf_netdev_ops;
|
|
|
|
priv = netdev_priv(net_dev);
|
|
priv->net_dev = net_dev;
|
|
priv->io = io;
|
|
priv->dma_io = dma_io;
|
|
priv->dev = dev;
|
|
|
|
err = ec_bhf_setup_offsets(priv);
|
|
if (err < 0)
|
|
goto err_free_net_dev;
|
|
|
|
memcpy_fromio(net_dev->dev_addr, priv->mii_io + MII_MAC_ADDR, 6);
|
|
|
|
err = register_netdev(net_dev);
|
|
if (err < 0)
|
|
goto err_free_net_dev;
|
|
|
|
return 0;
|
|
|
|
err_free_net_dev:
|
|
free_netdev(net_dev);
|
|
err_unmap_dma_io:
|
|
pci_iounmap(dev, dma_io);
|
|
err_unmap:
|
|
pci_iounmap(dev, io);
|
|
err_release_regions:
|
|
pci_release_regions(dev);
|
|
err_disable_dev:
|
|
pci_clear_master(dev);
|
|
pci_disable_device(dev);
|
|
|
|
return err;
|
|
}
|
|
|
|
static void ec_bhf_remove(struct pci_dev *dev)
|
|
{
|
|
struct net_device *net_dev = pci_get_drvdata(dev);
|
|
struct ec_bhf_priv *priv = netdev_priv(net_dev);
|
|
|
|
unregister_netdev(net_dev);
|
|
free_netdev(net_dev);
|
|
|
|
pci_iounmap(dev, priv->dma_io);
|
|
pci_iounmap(dev, priv->io);
|
|
pci_release_regions(dev);
|
|
pci_clear_master(dev);
|
|
pci_disable_device(dev);
|
|
}
|
|
|
|
static struct pci_driver pci_driver = {
|
|
.name = "ec_bhf",
|
|
.id_table = ids,
|
|
.probe = ec_bhf_probe,
|
|
.remove = ec_bhf_remove,
|
|
};
|
|
module_pci_driver(pci_driver);
|
|
|
|
module_param(polling_frequency, long, S_IRUGO);
|
|
MODULE_PARM_DESC(polling_frequency, "Polling timer frequency in ns");
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Dariusz Marcinkiewicz <reksio@newterm.pl>");
|