363c55cae5
[Ralf: SMP support requires CPU hotplugging which MIPS currently doesn't support. As implemented in this patch cache and tlb flushing will also be invoked with interrupts disabled so smp_call_function() will blow up in charming ways. So limit to !SMP.] Reviewed-by: Pavel Machek <pavel@ucw.cz> Reviewed-by: Yan Hua <yanh@lemote.com> Reviewed-by: Arnaud Patard <apatard@mandriva.com> Reviewed-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Wu Zhangjin <wuzj@lemote.com> Signed-off-by: Hu Hongbing <huhb@lemote.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
44 lines
895 B
C
44 lines
895 B
C
/*
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* Suspend support specific for mips.
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*
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* Licensed under the GPLv2
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*
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* Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
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* Author: Hu Hongbing <huhb@lemote.com>
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* Wu Zhangjin <wuzj@lemote.com>
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*/
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#include <asm/suspend.h>
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#include <asm/fpu.h>
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#include <asm/dsp.h>
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static u32 saved_status;
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struct pt_regs saved_regs;
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void save_processor_state(void)
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{
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saved_status = read_c0_status();
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if (is_fpu_owner())
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save_fp(current);
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if (cpu_has_dsp)
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save_dsp(current);
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}
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void restore_processor_state(void)
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{
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write_c0_status(saved_status);
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if (is_fpu_owner())
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restore_fp(current);
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if (cpu_has_dsp)
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restore_dsp(current);
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}
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int pfn_is_nosave(unsigned long pfn)
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{
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unsigned long nosave_begin_pfn = PFN_DOWN(__pa(&__nosave_begin));
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unsigned long nosave_end_pfn = PFN_UP(__pa(&__nosave_end));
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return (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn);
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}
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