![Linus Torvalds](/assets/img/avatar_default.png)
* git://git.kernel.org/pub/scm/linux/kernel/git/rusty/linux-2.6-cpumask: oprofile: Thou shalt not call __exit functions from __init functions cpumask: remove the now-obsoleted pcibus_to_cpumask(): generic cpumask: remove cpumask_t from core cpumask: convert rcutorture.c cpumask: use new cpumask_ functions in core code. cpumask: remove references to struct irqaction's mask field. cpumask: use mm_cpumask() wrapper: kernel/fork.c cpumask: use set_cpu_active in init/main.c cpumask: remove node_to_first_cpu cpumask: fix seq_bitmap_*() functions. cpumask: remove dangerous CPU_MASK_ALL_PTR, &CPU_MASK_ALL
246 lines
5.5 KiB
C
246 lines
5.5 KiB
C
#include <linux/kernel.h>
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#include <linux/mmzone.h>
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#include <linux/nodemask.h>
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#include <linux/spinlock.h>
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#include <linux/smp.h>
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#include <asm/atomic.h>
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#include <asm/sn/types.h>
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#include <asm/sn/addrs.h>
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#include <asm/sn/nmi.h>
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#include <asm/sn/arch.h>
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#include <asm/sn/sn0/hub.h>
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#if 0
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#define NODE_NUM_CPUS(n) CNODE_NUM_CPUS(n)
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#else
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#define NODE_NUM_CPUS(n) CPUS_PER_NODE
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#endif
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#define CNODEID_NONE (cnodeid_t)-1
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#define enter_panic_mode() spin_lock(&nmi_lock)
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typedef unsigned long machreg_t;
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DEFINE_SPINLOCK(nmi_lock);
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/*
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* Lets see what else we need to do here. Set up sp, gp?
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*/
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void nmi_dump(void)
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{
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void cont_nmi_dump(void);
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cont_nmi_dump();
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}
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void install_cpu_nmi_handler(int slice)
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{
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nmi_t *nmi_addr;
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nmi_addr = (nmi_t *)NMI_ADDR(get_nasid(), slice);
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if (nmi_addr->call_addr)
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return;
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nmi_addr->magic = NMI_MAGIC;
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nmi_addr->call_addr = (void *)nmi_dump;
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nmi_addr->call_addr_c =
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(void *)(~((unsigned long)(nmi_addr->call_addr)));
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nmi_addr->call_parm = 0;
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}
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/*
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* Copy the cpu registers which have been saved in the IP27prom format
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* into the eframe format for the node under consideration.
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*/
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void nmi_cpu_eframe_save(nasid_t nasid, int slice)
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{
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struct reg_struct *nr;
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int i;
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/* Get the pointer to the current cpu's register set. */
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nr = (struct reg_struct *)
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(TO_UNCAC(TO_NODE(nasid, IP27_NMI_KREGS_OFFSET)) +
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slice * IP27_NMI_KREGS_CPU_SIZE);
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printk("NMI nasid %d: slice %d\n", nasid, slice);
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/*
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* Saved main processor registers
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*/
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for (i = 0; i < 32; ) {
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if ((i % 4) == 0)
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printk("$%2d :", i);
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printk(" %016lx", nr->gpr[i]);
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i++;
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if ((i % 4) == 0)
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printk("\n");
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}
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printk("Hi : (value lost)\n");
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printk("Lo : (value lost)\n");
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/*
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* Saved cp0 registers
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*/
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printk("epc : %016lx %pS\n", nr->epc, (void *) nr->epc);
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printk("%s\n", print_tainted());
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printk("ErrEPC: %016lx %pS\n", nr->error_epc, (void *) nr->error_epc);
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printk("ra : %016lx %pS\n", nr->gpr[31], (void *) nr->gpr[31]);
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printk("Status: %08lx ", nr->sr);
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if (nr->sr & ST0_KX)
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printk("KX ");
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if (nr->sr & ST0_SX)
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printk("SX ");
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if (nr->sr & ST0_UX)
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printk("UX ");
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switch (nr->sr & ST0_KSU) {
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case KSU_USER:
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printk("USER ");
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break;
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case KSU_SUPERVISOR:
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printk("SUPERVISOR ");
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break;
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case KSU_KERNEL:
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printk("KERNEL ");
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break;
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default:
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printk("BAD_MODE ");
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break;
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}
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if (nr->sr & ST0_ERL)
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printk("ERL ");
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if (nr->sr & ST0_EXL)
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printk("EXL ");
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if (nr->sr & ST0_IE)
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printk("IE ");
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printk("\n");
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printk("Cause : %08lx\n", nr->cause);
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printk("PrId : %08x\n", read_c0_prid());
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printk("BadVA : %016lx\n", nr->badva);
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printk("CErr : %016lx\n", nr->cache_err);
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printk("NMI_SR: %016lx\n", nr->nmi_sr);
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printk("\n");
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}
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void nmi_dump_hub_irq(nasid_t nasid, int slice)
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{
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hubreg_t mask0, mask1, pend0, pend1;
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if (slice == 0) { /* Slice A */
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mask0 = REMOTE_HUB_L(nasid, PI_INT_MASK0_A);
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mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_A);
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} else { /* Slice B */
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mask0 = REMOTE_HUB_L(nasid, PI_INT_MASK0_B);
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mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_B);
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}
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pend0 = REMOTE_HUB_L(nasid, PI_INT_PEND0);
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pend1 = REMOTE_HUB_L(nasid, PI_INT_PEND1);
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printk("PI_INT_MASK0: %16Lx PI_INT_MASK1: %16Lx\n", mask0, mask1);
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printk("PI_INT_PEND0: %16Lx PI_INT_PEND1: %16Lx\n", pend0, pend1);
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printk("\n\n");
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}
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/*
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* Copy the cpu registers which have been saved in the IP27prom format
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* into the eframe format for the node under consideration.
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*/
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void nmi_node_eframe_save(cnodeid_t cnode)
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{
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nasid_t nasid;
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int slice;
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/* Make sure that we have a valid node */
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if (cnode == CNODEID_NONE)
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return;
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nasid = COMPACT_TO_NASID_NODEID(cnode);
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if (nasid == INVALID_NASID)
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return;
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/* Save the registers into eframe for each cpu */
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for (slice = 0; slice < NODE_NUM_CPUS(slice); slice++) {
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nmi_cpu_eframe_save(nasid, slice);
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nmi_dump_hub_irq(nasid, slice);
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}
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}
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/*
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* Save the nmi cpu registers for all cpus in the system.
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*/
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void
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nmi_eframes_save(void)
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{
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cnodeid_t cnode;
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for_each_online_node(cnode)
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nmi_node_eframe_save(cnode);
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}
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void
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cont_nmi_dump(void)
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{
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#ifndef REAL_NMI_SIGNAL
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static atomic_t nmied_cpus = ATOMIC_INIT(0);
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atomic_inc(&nmied_cpus);
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#endif
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/*
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* Use enter_panic_mode to allow only 1 cpu to proceed
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*/
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enter_panic_mode();
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#ifdef REAL_NMI_SIGNAL
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/*
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* Wait up to 15 seconds for the other cpus to respond to the NMI.
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* If a cpu has not responded after 10 sec, send it 1 additional NMI.
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* This is for 2 reasons:
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* - sometimes a MMSC fail to NMI all cpus.
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* - on 512p SN0 system, the MMSC will only send NMIs to
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* half the cpus. Unfortunately, we don't know which cpus may be
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* NMIed - it depends on how the site chooses to configure.
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*
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* Note: it has been measure that it takes the MMSC up to 2.3 secs to
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* send NMIs to all cpus on a 256p system.
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*/
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for (i=0; i < 1500; i++) {
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for_each_online_node(node)
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if (NODEPDA(node)->dump_count == 0)
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break;
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if (node == MAX_NUMNODES)
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break;
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if (i == 1000) {
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for_each_online_node(node)
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if (NODEPDA(node)->dump_count == 0) {
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cpu = cpumask_first(cpumask_of_node(node));
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for (n=0; n < CNODE_NUM_CPUS(node); cpu++, n++) {
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CPUMASK_SETB(nmied_cpus, cpu);
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/*
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* cputonasid, cputoslice
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* needs kernel cpuid
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*/
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SEND_NMI((cputonasid(cpu)), (cputoslice(cpu)));
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}
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}
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}
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udelay(10000);
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}
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#else
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while (atomic_read(&nmied_cpus) != num_online_cpus());
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#endif
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/*
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* Save the nmi cpu registers for all cpu in the eframe format.
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*/
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nmi_eframes_save();
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LOCAL_HUB_S(NI_PORT_RESET, NPR_PORTRESET | NPR_LOCALRESET);
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}
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