bc157b7596
This patchset adds the necessary drivers and infrastructure to access the external flash on the ATSTK1000 board through the MTD subsystem. With this stuff in place, it will be possible to use a jffs2 filesystem stored in the external flash as a root filesystem. It might also be possible to update the boot loader if you drop the write protection of partition 0. As suggested by David Woodhouse, I reworked the patches to use the physmap driver instead of introducing a separate mapping driver for the ATSTK1000. I've also cleaned up the hsmc header by removing useless comments and converting spaces to tabs (my headerfile generator needs some work.) Unfortunately, I couldn't unlock the flash in fixup_use_atmel_lock because the erase regions hadn't been set up yet, so I had to do it from cfi_amdstd_setup instead. This patch: This adds a simple API for configuring the static memory controller along with an implementation for the Atmel HSMC. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Cc: David Woodhouse <dwmw2@infradead.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
61 lines
1.4 KiB
C
61 lines
1.4 KiB
C
/*
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* Static Memory Controller for AT32 chips
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*
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* Copyright (C) 2006 Atmel Corporation
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*
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* Inspired by the OMAP2 General-Purpose Memory Controller interface
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ARCH_AT32AP_SMC_H
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#define __ARCH_AT32AP_SMC_H
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/*
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* All timing parameters are in nanoseconds.
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*/
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struct smc_config {
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/* Delay from address valid to assertion of given strobe */
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u16 ncs_read_setup;
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u16 nrd_setup;
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u16 ncs_write_setup;
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u16 nwe_setup;
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/* Pulse length of given strobe */
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u16 ncs_read_pulse;
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u16 nrd_pulse;
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u16 ncs_write_pulse;
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u16 nwe_pulse;
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/* Total cycle length of given operation */
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u16 read_cycle;
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u16 write_cycle;
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/* Bus width in bytes */
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u8 bus_width;
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/*
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* 0: Data is sampled on rising edge of NCS
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* 1: Data is sampled on rising edge of NRD
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*/
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unsigned int nrd_controlled:1;
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/*
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* 0: Data is driven on falling edge of NCS
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* 1: Data is driven on falling edge of NWR
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*/
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unsigned int nwe_controlled:1;
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/*
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* 0: Byte select access type
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* 1: Byte write access type
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*/
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unsigned int byte_write:1;
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};
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extern int smc_set_configuration(int cs, const struct smc_config *config);
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extern struct smc_config *smc_get_configuration(int cs);
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#endif /* __ARCH_AT32AP_SMC_H */
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