91af127fd7
The plan is to pass requests around as the basic submission tracking structure rather than rings and contexts. This patch updates the i915_gem_object_sync() code path. v2: Much more complex patch to share a single request between the sync and the page flip. The _sync() function now supports lazy allocation of the request structure. That is, if one is passed in then that will be used. If one is not, then a request will be allocated and passed back out. Note that the _sync() code does not necessarily require a request. Thus one will only be created until certain situations. The reason the lazy allocation must be done within the _sync() code itself is because the decision to need one or not is not really something that code above can second guess (except in the case where one is definitely not required because no ring is passed in). The call chains above _sync() now support passing a request through which most callers passing in NULL and assuming that no request will be required (because they also pass in NULL for the ring and therefore can't be generating any ring code). The exeception is intel_crtc_page_flip() which now supports having a request returned from _sync(). If one is, then that request is shared by the page flip (if the page flip is of a type to need a request). If _sync() does not generate a request but the page flip does need one, then the page flip path will create its own request. v3: Updated comment description to be clearer about 'to_req' parameter (Tomas Elf review request). Rebased onto newer tree that significantly changed the synchronisation code. v4: Updated comments from review feedback (Tomas Elf) For: VIZ-5115 Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Reviewed-by: Tomas Elf <tomas.elf@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
1445 lines
48 KiB
C
1445 lines
48 KiB
C
/*
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* Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
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* Copyright (c) 2007-2008 Intel Corporation
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* Jesse Barnes <jesse.barnes@intel.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef __INTEL_DRV_H__
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#define __INTEL_DRV_H__
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#include <linux/async.h>
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#include <linux/i2c.h>
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#include <linux/hdmi.h>
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_dp_mst_helper.h>
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#include <drm/drm_rect.h>
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#include <drm/drm_atomic.h>
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/**
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* _wait_for - magic (register) wait macro
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*
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* Does the right thing for modeset paths when run under kdgb or similar atomic
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* contexts. Note that it's important that we check the condition again after
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* having timed out, since the timeout could be due to preemption or similar and
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* we've never had a chance to check the condition before the timeout.
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*/
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#define _wait_for(COND, MS, W) ({ \
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unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
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int ret__ = 0; \
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while (!(COND)) { \
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if (time_after(jiffies, timeout__)) { \
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if (!(COND)) \
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ret__ = -ETIMEDOUT; \
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break; \
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} \
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if ((W) && drm_can_sleep()) { \
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usleep_range((W)*1000, (W)*2000); \
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} else { \
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cpu_relax(); \
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} \
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} \
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ret__; \
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})
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#define wait_for(COND, MS) _wait_for(COND, MS, 1)
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#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
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#define wait_for_atomic_us(COND, US) _wait_for((COND), \
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DIV_ROUND_UP((US), 1000), 0)
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#define KHz(x) (1000 * (x))
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#define MHz(x) KHz(1000 * (x))
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/*
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* Display related stuff
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*/
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/* store information about an Ixxx DVO */
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/* The i830->i865 use multiple DVOs with multiple i2cs */
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/* the i915, i945 have a single sDVO i2c bus - which is different */
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#define MAX_OUTPUTS 6
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/* maximum connectors per crtcs in the mode set */
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/* Maximum cursor sizes */
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#define GEN2_CURSOR_WIDTH 64
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#define GEN2_CURSOR_HEIGHT 64
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#define MAX_CURSOR_WIDTH 256
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#define MAX_CURSOR_HEIGHT 256
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#define INTEL_I2C_BUS_DVO 1
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#define INTEL_I2C_BUS_SDVO 2
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/* these are outputs from the chip - integrated only
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external chips are via DVO or SDVO output */
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enum intel_output_type {
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INTEL_OUTPUT_UNUSED = 0,
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INTEL_OUTPUT_ANALOG = 1,
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INTEL_OUTPUT_DVO = 2,
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INTEL_OUTPUT_SDVO = 3,
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INTEL_OUTPUT_LVDS = 4,
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INTEL_OUTPUT_TVOUT = 5,
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INTEL_OUTPUT_HDMI = 6,
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INTEL_OUTPUT_DISPLAYPORT = 7,
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INTEL_OUTPUT_EDP = 8,
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INTEL_OUTPUT_DSI = 9,
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INTEL_OUTPUT_UNKNOWN = 10,
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INTEL_OUTPUT_DP_MST = 11,
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};
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#define INTEL_DVO_CHIP_NONE 0
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#define INTEL_DVO_CHIP_LVDS 1
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#define INTEL_DVO_CHIP_TMDS 2
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#define INTEL_DVO_CHIP_TVOUT 4
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#define INTEL_DSI_VIDEO_MODE 0
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#define INTEL_DSI_COMMAND_MODE 1
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struct intel_framebuffer {
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struct drm_framebuffer base;
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struct drm_i915_gem_object *obj;
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};
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struct intel_fbdev {
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struct drm_fb_helper helper;
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struct intel_framebuffer *fb;
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struct list_head fbdev_list;
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struct drm_display_mode *our_mode;
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int preferred_bpp;
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};
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struct intel_encoder {
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struct drm_encoder base;
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/*
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* The new crtc this encoder will be driven from. Only differs from
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* base->crtc while a modeset is in progress.
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*/
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struct intel_crtc *new_crtc;
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enum intel_output_type type;
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unsigned int cloneable;
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bool connectors_active;
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void (*hot_plug)(struct intel_encoder *);
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bool (*compute_config)(struct intel_encoder *,
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struct intel_crtc_state *);
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void (*pre_pll_enable)(struct intel_encoder *);
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void (*pre_enable)(struct intel_encoder *);
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void (*enable)(struct intel_encoder *);
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void (*mode_set)(struct intel_encoder *intel_encoder);
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void (*disable)(struct intel_encoder *);
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void (*post_disable)(struct intel_encoder *);
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/* Read out the current hw state of this connector, returning true if
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* the encoder is active. If the encoder is enabled it also set the pipe
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* it is connected to in the pipe parameter. */
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bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
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/* Reconstructs the equivalent mode flags for the current hardware
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* state. This must be called _after_ display->get_pipe_config has
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* pre-filled the pipe config. Note that intel_encoder->base.crtc must
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* be set correctly before calling this function. */
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void (*get_config)(struct intel_encoder *,
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struct intel_crtc_state *pipe_config);
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/*
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* Called during system suspend after all pending requests for the
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* encoder are flushed (for example for DP AUX transactions) and
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* device interrupts are disabled.
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*/
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void (*suspend)(struct intel_encoder *);
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int crtc_mask;
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enum hpd_pin hpd_pin;
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};
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struct intel_panel {
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struct drm_display_mode *fixed_mode;
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struct drm_display_mode *downclock_mode;
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int fitting_mode;
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/* backlight */
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struct {
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bool present;
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u32 level;
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u32 min;
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u32 max;
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bool enabled;
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bool combination_mode; /* gen 2/4 only */
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bool active_low_pwm;
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struct backlight_device *device;
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} backlight;
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void (*backlight_power)(struct intel_connector *, bool enable);
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};
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struct intel_connector {
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struct drm_connector base;
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/*
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* The fixed encoder this connector is connected to.
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*/
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struct intel_encoder *encoder;
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/*
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* The new encoder this connector will be driven. Only differs from
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* encoder while a modeset is in progress.
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*/
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struct intel_encoder *new_encoder;
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/* Reads out the current hw, returning true if the connector is enabled
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* and active (i.e. dpms ON state). */
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bool (*get_hw_state)(struct intel_connector *);
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/*
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* Removes all interfaces through which the connector is accessible
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* - like sysfs, debugfs entries -, so that no new operations can be
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* started on the connector. Also makes sure all currently pending
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* operations finish before returing.
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*/
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void (*unregister)(struct intel_connector *);
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/* Panel info for eDP and LVDS */
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struct intel_panel panel;
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/* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
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struct edid *edid;
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struct edid *detect_edid;
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/* since POLL and HPD connectors may use the same HPD line keep the native
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state of connector->polled in case hotplug storm detection changes it */
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u8 polled;
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void *port; /* store this opaque as its illegal to dereference it */
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struct intel_dp *mst_port;
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};
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typedef struct dpll {
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/* given values */
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int n;
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int m1, m2;
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int p1, p2;
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/* derived values */
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int dot;
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int vco;
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int m;
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int p;
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} intel_clock_t;
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struct intel_atomic_state {
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struct drm_atomic_state base;
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unsigned int cdclk;
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bool dpll_set;
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struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
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};
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struct intel_plane_state {
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struct drm_plane_state base;
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struct drm_rect src;
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struct drm_rect dst;
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struct drm_rect clip;
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bool visible;
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/*
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* scaler_id
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* = -1 : not using a scaler
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* >= 0 : using a scalers
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*
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* plane requiring a scaler:
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* - During check_plane, its bit is set in
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* crtc_state->scaler_state.scaler_users by calling helper function
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* update_scaler_plane.
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* - scaler_id indicates the scaler it got assigned.
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*
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* plane doesn't require a scaler:
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* - this can happen when scaling is no more required or plane simply
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* got disabled.
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* - During check_plane, corresponding bit is reset in
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* crtc_state->scaler_state.scaler_users by calling helper function
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* update_scaler_plane.
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*/
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int scaler_id;
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struct drm_intel_sprite_colorkey ckey;
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};
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struct intel_initial_plane_config {
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struct intel_framebuffer *fb;
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unsigned int tiling;
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int size;
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u32 base;
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};
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#define SKL_MIN_SRC_W 8
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#define SKL_MAX_SRC_W 4096
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#define SKL_MIN_SRC_H 8
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#define SKL_MAX_SRC_H 4096
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#define SKL_MIN_DST_W 8
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#define SKL_MAX_DST_W 4096
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#define SKL_MIN_DST_H 8
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#define SKL_MAX_DST_H 4096
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|
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struct intel_scaler {
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int in_use;
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uint32_t mode;
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};
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struct intel_crtc_scaler_state {
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#define SKL_NUM_SCALERS 2
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struct intel_scaler scalers[SKL_NUM_SCALERS];
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/*
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* scaler_users: keeps track of users requesting scalers on this crtc.
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*
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* If a bit is set, a user is using a scaler.
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* Here user can be a plane or crtc as defined below:
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* bits 0-30 - plane (bit position is index from drm_plane_index)
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* bit 31 - crtc
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*
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* Instead of creating a new index to cover planes and crtc, using
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* existing drm_plane_index for planes which is well less than 31
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* planes and bit 31 for crtc. This should be fine to cover all
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* our platforms.
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*
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* intel_atomic_setup_scalers will setup available scalers to users
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* requesting scalers. It will gracefully fail if request exceeds
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* avilability.
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*/
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#define SKL_CRTC_INDEX 31
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unsigned scaler_users;
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|
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/* scaler used by crtc for panel fitting purpose */
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int scaler_id;
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};
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|
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struct intel_crtc_state {
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struct drm_crtc_state base;
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|
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/**
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* quirks - bitfield with hw state readout quirks
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*
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* For various reasons the hw state readout code might not be able to
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* completely faithfully read out the current state. These cases are
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* tracked with quirk flags so that fastboot and state checker can act
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* accordingly.
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*/
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#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
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#define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
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#define PIPE_CONFIG_QUIRK_INITIAL_PLANES (1<<2) /* planes are in unknown state */
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unsigned long quirks;
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/* Pipe source size (ie. panel fitter input size)
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* All planes will be positioned inside this space,
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* and get clipped at the edges. */
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int pipe_src_w, pipe_src_h;
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|
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/* Whether to set up the PCH/FDI. Note that we never allow sharing
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* between pch encoders and cpu encoders. */
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bool has_pch_encoder;
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/* Are we sending infoframes on the attached port */
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bool has_infoframe;
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/* CPU Transcoder for the pipe. Currently this can only differ from the
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* pipe on Haswell (where we have a special eDP transcoder). */
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enum transcoder cpu_transcoder;
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/*
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* Use reduced/limited/broadcast rbg range, compressing from the full
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* range fed into the crtcs.
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*/
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bool limited_color_range;
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|
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/* DP has a bunch of special case unfortunately, so mark the pipe
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* accordingly. */
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bool has_dp_encoder;
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|
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/* Whether we should send NULL infoframes. Required for audio. */
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bool has_hdmi_sink;
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|
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/* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
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* has_dp_encoder is set. */
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bool has_audio;
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/*
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* Enable dithering, used when the selected pipe bpp doesn't match the
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* plane bpp.
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*/
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bool dither;
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|
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/* Controls for the clock computation, to override various stages. */
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bool clock_set;
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|
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/* SDVO TV has a bunch of special case. To make multifunction encoders
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* work correctly, we need to track this at runtime.*/
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bool sdvo_tv_clock;
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|
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/*
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* crtc bandwidth limit, don't increase pipe bpp or clock if not really
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* required. This is set in the 2nd loop of calling encoder's
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* ->compute_config if the first pick doesn't work out.
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*/
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bool bw_constrained;
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|
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/* Settings for the intel dpll used on pretty much everything but
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* haswell. */
|
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struct dpll dpll;
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|
|
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/* Selected dpll when shared or DPLL_ID_PRIVATE. */
|
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enum intel_dpll_id shared_dpll;
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|
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/*
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* - PORT_CLK_SEL for DDI ports on HSW/BDW.
|
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* - enum skl_dpll on SKL
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*/
|
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uint32_t ddi_pll_sel;
|
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|
|
/* Actual register state of the dpll, for shared dpll cross-checking. */
|
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struct intel_dpll_hw_state dpll_hw_state;
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|
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int pipe_bpp;
|
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struct intel_link_m_n dp_m_n;
|
|
|
|
/* m2_n2 for eDP downclock */
|
|
struct intel_link_m_n dp_m2_n2;
|
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bool has_drrs;
|
|
|
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/*
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|
* Frequence the dpll for the port should run at. Differs from the
|
|
* adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
|
|
* already multiplied by pixel_multiplier.
|
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*/
|
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int port_clock;
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|
|
|
/* Used by SDVO (and if we ever fix it, HDMI). */
|
|
unsigned pixel_multiplier;
|
|
|
|
/* Panel fitter controls for gen2-gen4 + VLV */
|
|
struct {
|
|
u32 control;
|
|
u32 pgm_ratios;
|
|
u32 lvds_border_bits;
|
|
} gmch_pfit;
|
|
|
|
/* Panel fitter placement and size for Ironlake+ */
|
|
struct {
|
|
u32 pos;
|
|
u32 size;
|
|
bool enabled;
|
|
bool force_thru;
|
|
} pch_pfit;
|
|
|
|
/* FDI configuration, only valid if has_pch_encoder is set. */
|
|
int fdi_lanes;
|
|
struct intel_link_m_n fdi_m_n;
|
|
|
|
bool ips_enabled;
|
|
|
|
bool double_wide;
|
|
|
|
bool dp_encoder_is_mst;
|
|
int pbn;
|
|
|
|
struct intel_crtc_scaler_state scaler_state;
|
|
|
|
/* w/a for waiting 2 vblanks during crtc enable */
|
|
enum pipe hsw_workaround_pipe;
|
|
};
|
|
|
|
struct intel_pipe_wm {
|
|
struct intel_wm_level wm[5];
|
|
uint32_t linetime;
|
|
bool fbc_wm_enabled;
|
|
bool pipe_enabled;
|
|
bool sprites_enabled;
|
|
bool sprites_scaled;
|
|
};
|
|
|
|
struct intel_mmio_flip {
|
|
struct work_struct work;
|
|
struct drm_i915_private *i915;
|
|
struct drm_i915_gem_request *req;
|
|
struct intel_crtc *crtc;
|
|
};
|
|
|
|
struct skl_pipe_wm {
|
|
struct skl_wm_level wm[8];
|
|
struct skl_wm_level trans_wm;
|
|
uint32_t linetime;
|
|
};
|
|
|
|
/*
|
|
* Tracking of operations that need to be performed at the beginning/end of an
|
|
* atomic commit, outside the atomic section where interrupts are disabled.
|
|
* These are generally operations that grab mutexes or might otherwise sleep
|
|
* and thus can't be run with interrupts disabled.
|
|
*/
|
|
struct intel_crtc_atomic_commit {
|
|
/* vblank evasion */
|
|
bool evade;
|
|
unsigned start_vbl_count;
|
|
|
|
/* Sleepable operations to perform before commit */
|
|
bool wait_for_flips;
|
|
bool disable_fbc;
|
|
bool pre_disable_primary;
|
|
bool update_wm;
|
|
unsigned disabled_planes;
|
|
|
|
/* Sleepable operations to perform after commit */
|
|
unsigned fb_bits;
|
|
bool wait_vblank;
|
|
bool update_fbc;
|
|
bool post_enable_primary;
|
|
unsigned update_sprite_watermarks;
|
|
};
|
|
|
|
struct intel_crtc {
|
|
struct drm_crtc base;
|
|
enum pipe pipe;
|
|
enum plane plane;
|
|
u8 lut_r[256], lut_g[256], lut_b[256];
|
|
/*
|
|
* Whether the crtc and the connected output pipeline is active. Implies
|
|
* that crtc->enabled is set, i.e. the current mode configuration has
|
|
* some outputs connected to this crtc.
|
|
*/
|
|
bool active;
|
|
unsigned long enabled_power_domains;
|
|
bool lowfreq_avail;
|
|
struct intel_overlay *overlay;
|
|
struct intel_unpin_work *unpin_work;
|
|
|
|
atomic_t unpin_work_count;
|
|
|
|
/* Display surface base address adjustement for pageflips. Note that on
|
|
* gen4+ this only adjusts up to a tile, offsets within a tile are
|
|
* handled in the hw itself (with the TILEOFF register). */
|
|
unsigned long dspaddr_offset;
|
|
|
|
struct drm_i915_gem_object *cursor_bo;
|
|
uint32_t cursor_addr;
|
|
uint32_t cursor_cntl;
|
|
uint32_t cursor_size;
|
|
uint32_t cursor_base;
|
|
|
|
struct intel_initial_plane_config plane_config;
|
|
struct intel_crtc_state *config;
|
|
bool new_enabled;
|
|
|
|
/* reset counter value when the last flip was submitted */
|
|
unsigned int reset_counter;
|
|
|
|
/* Access to these should be protected by dev_priv->irq_lock. */
|
|
bool cpu_fifo_underrun_disabled;
|
|
bool pch_fifo_underrun_disabled;
|
|
|
|
/* per-pipe watermark state */
|
|
struct {
|
|
/* watermarks currently being used */
|
|
struct intel_pipe_wm active;
|
|
/* SKL wm values currently in use */
|
|
struct skl_pipe_wm skl_active;
|
|
} wm;
|
|
|
|
int scanline_offset;
|
|
|
|
struct intel_crtc_atomic_commit atomic;
|
|
|
|
/* scalers available on this crtc */
|
|
int num_scalers;
|
|
};
|
|
|
|
struct intel_plane_wm_parameters {
|
|
uint32_t horiz_pixels;
|
|
uint32_t vert_pixels;
|
|
/*
|
|
* For packed pixel formats:
|
|
* bytes_per_pixel - holds bytes per pixel
|
|
* For planar pixel formats:
|
|
* bytes_per_pixel - holds bytes per pixel for uv-plane
|
|
* y_bytes_per_pixel - holds bytes per pixel for y-plane
|
|
*/
|
|
uint8_t bytes_per_pixel;
|
|
uint8_t y_bytes_per_pixel;
|
|
bool enabled;
|
|
bool scaled;
|
|
u64 tiling;
|
|
unsigned int rotation;
|
|
};
|
|
|
|
struct intel_plane {
|
|
struct drm_plane base;
|
|
int plane;
|
|
enum pipe pipe;
|
|
bool can_scale;
|
|
int max_downscale;
|
|
|
|
/* Since we need to change the watermarks before/after
|
|
* enabling/disabling the planes, we need to store the parameters here
|
|
* as the other pieces of the struct may not reflect the values we want
|
|
* for the watermark calculations. Currently only Haswell uses this.
|
|
*/
|
|
struct intel_plane_wm_parameters wm;
|
|
|
|
/*
|
|
* NOTE: Do not place new plane state fields here (e.g., when adding
|
|
* new plane properties). New runtime state should now be placed in
|
|
* the intel_plane_state structure and accessed via drm_plane->state.
|
|
*/
|
|
|
|
void (*update_plane)(struct drm_plane *plane,
|
|
struct drm_crtc *crtc,
|
|
struct drm_framebuffer *fb,
|
|
int crtc_x, int crtc_y,
|
|
unsigned int crtc_w, unsigned int crtc_h,
|
|
uint32_t x, uint32_t y,
|
|
uint32_t src_w, uint32_t src_h);
|
|
void (*disable_plane)(struct drm_plane *plane,
|
|
struct drm_crtc *crtc);
|
|
int (*check_plane)(struct drm_plane *plane,
|
|
struct intel_crtc_state *crtc_state,
|
|
struct intel_plane_state *state);
|
|
void (*commit_plane)(struct drm_plane *plane,
|
|
struct intel_plane_state *state);
|
|
};
|
|
|
|
struct intel_watermark_params {
|
|
unsigned long fifo_size;
|
|
unsigned long max_wm;
|
|
unsigned long default_wm;
|
|
unsigned long guard_size;
|
|
unsigned long cacheline_size;
|
|
};
|
|
|
|
struct cxsr_latency {
|
|
int is_desktop;
|
|
int is_ddr3;
|
|
unsigned long fsb_freq;
|
|
unsigned long mem_freq;
|
|
unsigned long display_sr;
|
|
unsigned long display_hpll_disable;
|
|
unsigned long cursor_sr;
|
|
unsigned long cursor_hpll_disable;
|
|
};
|
|
|
|
#define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
|
|
#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
|
|
#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
|
|
#define to_intel_connector(x) container_of(x, struct intel_connector, base)
|
|
#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
|
|
#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
|
|
#define to_intel_plane(x) container_of(x, struct intel_plane, base)
|
|
#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
|
|
#define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
|
|
|
|
struct intel_hdmi {
|
|
u32 hdmi_reg;
|
|
int ddc_bus;
|
|
uint32_t color_range;
|
|
bool color_range_auto;
|
|
bool has_hdmi_sink;
|
|
bool has_audio;
|
|
enum hdmi_force_audio force_audio;
|
|
bool rgb_quant_range_selectable;
|
|
enum hdmi_picture_aspect aspect_ratio;
|
|
void (*write_infoframe)(struct drm_encoder *encoder,
|
|
enum hdmi_infoframe_type type,
|
|
const void *frame, ssize_t len);
|
|
void (*set_infoframes)(struct drm_encoder *encoder,
|
|
bool enable,
|
|
struct drm_display_mode *adjusted_mode);
|
|
bool (*infoframe_enabled)(struct drm_encoder *encoder);
|
|
};
|
|
|
|
struct intel_dp_mst_encoder;
|
|
#define DP_MAX_DOWNSTREAM_PORTS 0x10
|
|
|
|
/*
|
|
* enum link_m_n_set:
|
|
* When platform provides two set of M_N registers for dp, we can
|
|
* program them and switch between them incase of DRRS.
|
|
* But When only one such register is provided, we have to program the
|
|
* required divider value on that registers itself based on the DRRS state.
|
|
*
|
|
* M1_N1 : Program dp_m_n on M1_N1 registers
|
|
* dp_m2_n2 on M2_N2 registers (If supported)
|
|
*
|
|
* M2_N2 : Program dp_m2_n2 on M1_N1 registers
|
|
* M2_N2 registers are not supported
|
|
*/
|
|
|
|
enum link_m_n_set {
|
|
/* Sets the m1_n1 and m2_n2 */
|
|
M1_N1 = 0,
|
|
M2_N2
|
|
};
|
|
|
|
struct intel_dp {
|
|
uint32_t output_reg;
|
|
uint32_t aux_ch_ctl_reg;
|
|
uint32_t DP;
|
|
bool has_audio;
|
|
enum hdmi_force_audio force_audio;
|
|
uint32_t color_range;
|
|
bool color_range_auto;
|
|
uint8_t link_bw;
|
|
uint8_t rate_select;
|
|
uint8_t lane_count;
|
|
uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
|
|
uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
|
|
uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
|
|
/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
|
|
uint8_t num_sink_rates;
|
|
int sink_rates[DP_MAX_SUPPORTED_RATES];
|
|
struct drm_dp_aux aux;
|
|
uint8_t train_set[4];
|
|
int panel_power_up_delay;
|
|
int panel_power_down_delay;
|
|
int panel_power_cycle_delay;
|
|
int backlight_on_delay;
|
|
int backlight_off_delay;
|
|
struct delayed_work panel_vdd_work;
|
|
bool want_panel_vdd;
|
|
unsigned long last_power_cycle;
|
|
unsigned long last_power_on;
|
|
unsigned long last_backlight_off;
|
|
|
|
struct notifier_block edp_notifier;
|
|
|
|
/*
|
|
* Pipe whose power sequencer is currently locked into
|
|
* this port. Only relevant on VLV/CHV.
|
|
*/
|
|
enum pipe pps_pipe;
|
|
struct edp_power_seq pps_delays;
|
|
|
|
bool use_tps3;
|
|
bool can_mst; /* this port supports mst */
|
|
bool is_mst;
|
|
int active_mst_links;
|
|
/* connector directly attached - won't be use for modeset in mst world */
|
|
struct intel_connector *attached_connector;
|
|
|
|
/* mst connector list */
|
|
struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
|
|
struct drm_dp_mst_topology_mgr mst_mgr;
|
|
|
|
uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
|
|
/*
|
|
* This function returns the value we have to program the AUX_CTL
|
|
* register with to kick off an AUX transaction.
|
|
*/
|
|
uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
|
|
bool has_aux_irq,
|
|
int send_bytes,
|
|
uint32_t aux_clock_divider);
|
|
bool train_set_valid;
|
|
|
|
/* Displayport compliance testing */
|
|
unsigned long compliance_test_type;
|
|
unsigned long compliance_test_data;
|
|
bool compliance_test_active;
|
|
};
|
|
|
|
struct intel_digital_port {
|
|
struct intel_encoder base;
|
|
enum port port;
|
|
u32 saved_port_bits;
|
|
struct intel_dp dp;
|
|
struct intel_hdmi hdmi;
|
|
enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
|
|
};
|
|
|
|
struct intel_dp_mst_encoder {
|
|
struct intel_encoder base;
|
|
enum pipe pipe;
|
|
struct intel_digital_port *primary;
|
|
void *port; /* store this opaque as its illegal to dereference it */
|
|
};
|
|
|
|
static inline int
|
|
vlv_dport_to_channel(struct intel_digital_port *dport)
|
|
{
|
|
switch (dport->port) {
|
|
case PORT_B:
|
|
case PORT_D:
|
|
return DPIO_CH0;
|
|
case PORT_C:
|
|
return DPIO_CH1;
|
|
default:
|
|
BUG();
|
|
}
|
|
}
|
|
|
|
static inline int
|
|
vlv_pipe_to_channel(enum pipe pipe)
|
|
{
|
|
switch (pipe) {
|
|
case PIPE_A:
|
|
case PIPE_C:
|
|
return DPIO_CH0;
|
|
case PIPE_B:
|
|
return DPIO_CH1;
|
|
default:
|
|
BUG();
|
|
}
|
|
}
|
|
|
|
static inline struct drm_crtc *
|
|
intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
return dev_priv->pipe_to_crtc_mapping[pipe];
|
|
}
|
|
|
|
static inline struct drm_crtc *
|
|
intel_get_crtc_for_plane(struct drm_device *dev, int plane)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
return dev_priv->plane_to_crtc_mapping[plane];
|
|
}
|
|
|
|
struct intel_unpin_work {
|
|
struct work_struct work;
|
|
struct drm_crtc *crtc;
|
|
struct drm_framebuffer *old_fb;
|
|
struct drm_i915_gem_object *pending_flip_obj;
|
|
struct drm_pending_vblank_event *event;
|
|
atomic_t pending;
|
|
#define INTEL_FLIP_INACTIVE 0
|
|
#define INTEL_FLIP_PENDING 1
|
|
#define INTEL_FLIP_COMPLETE 2
|
|
u32 flip_count;
|
|
u32 gtt_offset;
|
|
struct drm_i915_gem_request *flip_queued_req;
|
|
int flip_queued_vblank;
|
|
int flip_ready_vblank;
|
|
bool enable_stall_check;
|
|
};
|
|
|
|
struct intel_load_detect_pipe {
|
|
struct drm_framebuffer *release_fb;
|
|
bool load_detect_temp;
|
|
int dpms_mode;
|
|
};
|
|
|
|
static inline struct intel_encoder *
|
|
intel_attached_encoder(struct drm_connector *connector)
|
|
{
|
|
return to_intel_connector(connector)->encoder;
|
|
}
|
|
|
|
static inline struct intel_digital_port *
|
|
enc_to_dig_port(struct drm_encoder *encoder)
|
|
{
|
|
return container_of(encoder, struct intel_digital_port, base.base);
|
|
}
|
|
|
|
static inline struct intel_dp_mst_encoder *
|
|
enc_to_mst(struct drm_encoder *encoder)
|
|
{
|
|
return container_of(encoder, struct intel_dp_mst_encoder, base.base);
|
|
}
|
|
|
|
static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
|
|
{
|
|
return &enc_to_dig_port(encoder)->dp;
|
|
}
|
|
|
|
static inline struct intel_digital_port *
|
|
dp_to_dig_port(struct intel_dp *intel_dp)
|
|
{
|
|
return container_of(intel_dp, struct intel_digital_port, dp);
|
|
}
|
|
|
|
static inline struct intel_digital_port *
|
|
hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
|
|
{
|
|
return container_of(intel_hdmi, struct intel_digital_port, hdmi);
|
|
}
|
|
|
|
/*
|
|
* Returns the number of planes for this pipe, ie the number of sprites + 1
|
|
* (primary plane). This doesn't count the cursor plane then.
|
|
*/
|
|
static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
|
|
{
|
|
return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
|
|
}
|
|
|
|
/* intel_fifo_underrun.c */
|
|
bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
|
|
enum pipe pipe, bool enable);
|
|
bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
|
|
enum transcoder pch_transcoder,
|
|
bool enable);
|
|
void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
|
|
enum pipe pipe);
|
|
void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
|
|
enum transcoder pch_transcoder);
|
|
void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
|
|
|
|
/* i915_irq.c */
|
|
void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
|
|
void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
|
|
void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
|
|
void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
|
|
void gen6_reset_rps_interrupts(struct drm_device *dev);
|
|
void gen6_enable_rps_interrupts(struct drm_device *dev);
|
|
void gen6_disable_rps_interrupts(struct drm_device *dev);
|
|
u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
|
|
void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
|
|
void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
|
|
static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
|
|
{
|
|
/*
|
|
* We only use drm_irq_uninstall() at unload and VT switch, so
|
|
* this is the only thing we need to check.
|
|
*/
|
|
return dev_priv->pm.irqs_enabled;
|
|
}
|
|
|
|
int intel_get_crtc_scanline(struct intel_crtc *crtc);
|
|
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
|
|
unsigned int pipe_mask);
|
|
|
|
/* intel_crt.c */
|
|
void intel_crt_init(struct drm_device *dev);
|
|
|
|
|
|
/* intel_ddi.c */
|
|
void intel_prepare_ddi(struct drm_device *dev);
|
|
void hsw_fdi_link_train(struct drm_crtc *crtc);
|
|
void intel_ddi_init(struct drm_device *dev, enum port port);
|
|
enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
|
|
bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
|
|
void intel_ddi_pll_init(struct drm_device *dev);
|
|
void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
|
|
void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
|
|
enum transcoder cpu_transcoder);
|
|
void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
|
|
void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
|
|
bool intel_ddi_pll_select(struct intel_crtc *crtc,
|
|
struct intel_crtc_state *crtc_state);
|
|
void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
|
|
void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
|
|
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
|
|
void intel_ddi_fdi_disable(struct drm_crtc *crtc);
|
|
void intel_ddi_get_config(struct intel_encoder *encoder,
|
|
struct intel_crtc_state *pipe_config);
|
|
struct intel_encoder *
|
|
intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
|
|
|
|
void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
|
|
void intel_ddi_clock_get(struct intel_encoder *encoder,
|
|
struct intel_crtc_state *pipe_config);
|
|
void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
|
|
void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
|
|
enum port port, int type);
|
|
|
|
/* intel_frontbuffer.c */
|
|
void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
|
|
enum fb_op_origin origin);
|
|
void intel_frontbuffer_flip_prepare(struct drm_device *dev,
|
|
unsigned frontbuffer_bits);
|
|
void intel_frontbuffer_flip_complete(struct drm_device *dev,
|
|
unsigned frontbuffer_bits);
|
|
void intel_frontbuffer_flush(struct drm_device *dev,
|
|
unsigned frontbuffer_bits);
|
|
/**
|
|
* intel_frontbuffer_flip - synchronous frontbuffer flip
|
|
* @dev: DRM device
|
|
* @frontbuffer_bits: frontbuffer plane tracking bits
|
|
*
|
|
* This function gets called after scheduling a flip on @obj. This is for
|
|
* synchronous plane updates which will happen on the next vblank and which will
|
|
* not get delayed by pending gpu rendering.
|
|
*
|
|
* Can be called without any locks held.
|
|
*/
|
|
static inline
|
|
void intel_frontbuffer_flip(struct drm_device *dev,
|
|
unsigned frontbuffer_bits)
|
|
{
|
|
intel_frontbuffer_flush(dev, frontbuffer_bits);
|
|
}
|
|
|
|
unsigned int intel_fb_align_height(struct drm_device *dev,
|
|
unsigned int height,
|
|
uint32_t pixel_format,
|
|
uint64_t fb_format_modifier);
|
|
void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
|
|
|
|
u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
|
|
uint32_t pixel_format);
|
|
|
|
/* intel_audio.c */
|
|
void intel_init_audio(struct drm_device *dev);
|
|
void intel_audio_codec_enable(struct intel_encoder *encoder);
|
|
void intel_audio_codec_disable(struct intel_encoder *encoder);
|
|
void i915_audio_component_init(struct drm_i915_private *dev_priv);
|
|
void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
|
|
|
|
/* intel_display.c */
|
|
extern const struct drm_plane_funcs intel_plane_funcs;
|
|
bool intel_has_pending_fb_unpin(struct drm_device *dev);
|
|
int intel_pch_rawclk(struct drm_device *dev);
|
|
void intel_mark_busy(struct drm_device *dev);
|
|
void intel_mark_idle(struct drm_device *dev);
|
|
void intel_crtc_restore_mode(struct drm_crtc *crtc);
|
|
void intel_display_suspend(struct drm_device *dev);
|
|
int intel_crtc_control(struct drm_crtc *crtc, bool enable);
|
|
void intel_crtc_update_dpms(struct drm_crtc *crtc);
|
|
void intel_encoder_destroy(struct drm_encoder *encoder);
|
|
int intel_connector_init(struct intel_connector *);
|
|
struct intel_connector *intel_connector_alloc(void);
|
|
void intel_connector_dpms(struct drm_connector *, int mode);
|
|
bool intel_connector_get_hw_state(struct intel_connector *connector);
|
|
void intel_modeset_check_state(struct drm_device *dev);
|
|
bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
|
|
struct intel_digital_port *port);
|
|
void intel_connector_attach_encoder(struct intel_connector *connector,
|
|
struct intel_encoder *encoder);
|
|
struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
|
|
struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
|
|
struct drm_crtc *crtc);
|
|
enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
|
|
int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
|
|
enum pipe pipe);
|
|
bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
|
|
static inline void
|
|
intel_wait_for_vblank(struct drm_device *dev, int pipe)
|
|
{
|
|
drm_wait_one_vblank(dev, pipe);
|
|
}
|
|
int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
|
|
void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
|
|
struct intel_digital_port *dport,
|
|
unsigned int expected_mask);
|
|
bool intel_get_load_detect_pipe(struct drm_connector *connector,
|
|
struct drm_display_mode *mode,
|
|
struct intel_load_detect_pipe *old,
|
|
struct drm_modeset_acquire_ctx *ctx);
|
|
void intel_release_load_detect_pipe(struct drm_connector *connector,
|
|
struct intel_load_detect_pipe *old,
|
|
struct drm_modeset_acquire_ctx *ctx);
|
|
int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
|
|
struct drm_framebuffer *fb,
|
|
const struct drm_plane_state *plane_state,
|
|
struct intel_engine_cs *pipelined,
|
|
struct drm_i915_gem_request **pipelined_request);
|
|
struct drm_framebuffer *
|
|
__intel_framebuffer_create(struct drm_device *dev,
|
|
struct drm_mode_fb_cmd2 *mode_cmd,
|
|
struct drm_i915_gem_object *obj);
|
|
void intel_prepare_page_flip(struct drm_device *dev, int plane);
|
|
void intel_finish_page_flip(struct drm_device *dev, int pipe);
|
|
void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
|
|
void intel_check_page_flip(struct drm_device *dev, int pipe);
|
|
int intel_prepare_plane_fb(struct drm_plane *plane,
|
|
struct drm_framebuffer *fb,
|
|
const struct drm_plane_state *new_state);
|
|
void intel_cleanup_plane_fb(struct drm_plane *plane,
|
|
struct drm_framebuffer *fb,
|
|
const struct drm_plane_state *old_state);
|
|
int intel_plane_atomic_get_property(struct drm_plane *plane,
|
|
const struct drm_plane_state *state,
|
|
struct drm_property *property,
|
|
uint64_t *val);
|
|
int intel_plane_atomic_set_property(struct drm_plane *plane,
|
|
struct drm_plane_state *state,
|
|
struct drm_property *property,
|
|
uint64_t val);
|
|
int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
|
|
struct drm_plane_state *plane_state);
|
|
|
|
unsigned int
|
|
intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
|
|
uint64_t fb_format_modifier);
|
|
|
|
static inline bool
|
|
intel_rotation_90_or_270(unsigned int rotation)
|
|
{
|
|
return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
|
|
}
|
|
|
|
void intel_create_rotation_property(struct drm_device *dev,
|
|
struct intel_plane *plane);
|
|
|
|
/* shared dpll functions */
|
|
struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
|
|
void assert_shared_dpll(struct drm_i915_private *dev_priv,
|
|
struct intel_shared_dpll *pll,
|
|
bool state);
|
|
#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
|
|
#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
|
|
struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
|
|
struct intel_crtc_state *state);
|
|
|
|
void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
|
|
const struct dpll *dpll);
|
|
void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
|
|
|
|
/* modesetting asserts */
|
|
void assert_panel_unlocked(struct drm_i915_private *dev_priv,
|
|
enum pipe pipe);
|
|
void assert_pll(struct drm_i915_private *dev_priv,
|
|
enum pipe pipe, bool state);
|
|
#define assert_pll_enabled(d, p) assert_pll(d, p, true)
|
|
#define assert_pll_disabled(d, p) assert_pll(d, p, false)
|
|
void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
|
|
enum pipe pipe, bool state);
|
|
#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
|
|
#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
|
|
void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
|
|
#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
|
|
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
|
|
unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
|
|
int *x, int *y,
|
|
unsigned int tiling_mode,
|
|
unsigned int bpp,
|
|
unsigned int pitch);
|
|
void intel_prepare_reset(struct drm_device *dev);
|
|
void intel_finish_reset(struct drm_device *dev);
|
|
void hsw_enable_pc8(struct drm_i915_private *dev_priv);
|
|
void hsw_disable_pc8(struct drm_i915_private *dev_priv);
|
|
void broxton_init_cdclk(struct drm_device *dev);
|
|
void broxton_uninit_cdclk(struct drm_device *dev);
|
|
void broxton_ddi_phy_init(struct drm_device *dev);
|
|
void broxton_ddi_phy_uninit(struct drm_device *dev);
|
|
void bxt_enable_dc9(struct drm_i915_private *dev_priv);
|
|
void bxt_disable_dc9(struct drm_i915_private *dev_priv);
|
|
void skl_init_cdclk(struct drm_i915_private *dev_priv);
|
|
void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
|
|
void intel_dp_get_m_n(struct intel_crtc *crtc,
|
|
struct intel_crtc_state *pipe_config);
|
|
void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
|
|
int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
|
|
void
|
|
ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
|
|
int dotclock);
|
|
bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
|
|
intel_clock_t *best_clock);
|
|
bool intel_crtc_active(struct drm_crtc *crtc);
|
|
void hsw_enable_ips(struct intel_crtc *crtc);
|
|
void hsw_disable_ips(struct intel_crtc *crtc);
|
|
enum intel_display_power_domain
|
|
intel_display_port_power_domain(struct intel_encoder *intel_encoder);
|
|
void intel_mode_from_pipe_config(struct drm_display_mode *mode,
|
|
struct intel_crtc_state *pipe_config);
|
|
void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
|
|
void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
|
|
|
|
int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state, int force_detach);
|
|
int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
|
|
|
|
unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
|
|
struct drm_i915_gem_object *obj);
|
|
u32 skl_plane_ctl_format(uint32_t pixel_format);
|
|
u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
|
|
u32 skl_plane_ctl_rotation(unsigned int rotation);
|
|
|
|
/* intel_csr.c */
|
|
void intel_csr_ucode_init(struct drm_device *dev);
|
|
enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv);
|
|
void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
|
|
enum csr_state state);
|
|
void intel_csr_load_program(struct drm_device *dev);
|
|
void intel_csr_ucode_fini(struct drm_device *dev);
|
|
void assert_csr_loaded(struct drm_i915_private *dev_priv);
|
|
|
|
/* intel_dp.c */
|
|
void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
|
|
bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
|
|
struct intel_connector *intel_connector);
|
|
void intel_dp_start_link_train(struct intel_dp *intel_dp);
|
|
void intel_dp_complete_link_train(struct intel_dp *intel_dp);
|
|
void intel_dp_stop_link_train(struct intel_dp *intel_dp);
|
|
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
|
|
void intel_dp_encoder_destroy(struct drm_encoder *encoder);
|
|
int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
|
|
bool intel_dp_compute_config(struct intel_encoder *encoder,
|
|
struct intel_crtc_state *pipe_config);
|
|
bool intel_dp_is_edp(struct drm_device *dev, enum port port);
|
|
enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
|
|
bool long_hpd);
|
|
void intel_edp_backlight_on(struct intel_dp *intel_dp);
|
|
void intel_edp_backlight_off(struct intel_dp *intel_dp);
|
|
void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
|
|
void intel_edp_panel_on(struct intel_dp *intel_dp);
|
|
void intel_edp_panel_off(struct intel_dp *intel_dp);
|
|
void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
|
|
void intel_dp_mst_suspend(struct drm_device *dev);
|
|
void intel_dp_mst_resume(struct drm_device *dev);
|
|
int intel_dp_max_link_rate(struct intel_dp *intel_dp);
|
|
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
|
|
void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
|
|
void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
|
|
uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
|
|
void intel_plane_destroy(struct drm_plane *plane);
|
|
void intel_edp_drrs_enable(struct intel_dp *intel_dp);
|
|
void intel_edp_drrs_disable(struct intel_dp *intel_dp);
|
|
void intel_edp_drrs_invalidate(struct drm_device *dev,
|
|
unsigned frontbuffer_bits);
|
|
void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
|
|
|
|
/* intel_dp_mst.c */
|
|
int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
|
|
void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
|
|
/* intel_dsi.c */
|
|
void intel_dsi_init(struct drm_device *dev);
|
|
|
|
|
|
/* intel_dvo.c */
|
|
void intel_dvo_init(struct drm_device *dev);
|
|
|
|
|
|
/* legacy fbdev emulation in intel_fbdev.c */
|
|
#ifdef CONFIG_DRM_I915_FBDEV
|
|
extern int intel_fbdev_init(struct drm_device *dev);
|
|
extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
|
|
extern void intel_fbdev_fini(struct drm_device *dev);
|
|
extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
|
|
extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
|
|
extern void intel_fbdev_restore_mode(struct drm_device *dev);
|
|
#else
|
|
static inline int intel_fbdev_init(struct drm_device *dev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
|
|
{
|
|
}
|
|
|
|
static inline void intel_fbdev_fini(struct drm_device *dev)
|
|
{
|
|
}
|
|
|
|
static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
|
|
{
|
|
}
|
|
|
|
static inline void intel_fbdev_restore_mode(struct drm_device *dev)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
/* intel_fbc.c */
|
|
bool intel_fbc_enabled(struct drm_device *dev);
|
|
void intel_fbc_update(struct drm_device *dev);
|
|
void intel_fbc_init(struct drm_i915_private *dev_priv);
|
|
void intel_fbc_disable(struct drm_device *dev);
|
|
void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
|
|
unsigned int frontbuffer_bits,
|
|
enum fb_op_origin origin);
|
|
void intel_fbc_flush(struct drm_i915_private *dev_priv,
|
|
unsigned int frontbuffer_bits);
|
|
const char *intel_no_fbc_reason_str(enum no_fbc_reason reason);
|
|
|
|
/* intel_hdmi.c */
|
|
void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
|
|
void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
|
|
struct intel_connector *intel_connector);
|
|
struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
|
|
bool intel_hdmi_compute_config(struct intel_encoder *encoder,
|
|
struct intel_crtc_state *pipe_config);
|
|
|
|
|
|
/* intel_lvds.c */
|
|
void intel_lvds_init(struct drm_device *dev);
|
|
bool intel_is_dual_link_lvds(struct drm_device *dev);
|
|
|
|
|
|
/* intel_modes.c */
|
|
int intel_connector_update_modes(struct drm_connector *connector,
|
|
struct edid *edid);
|
|
int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
|
|
void intel_attach_force_audio_property(struct drm_connector *connector);
|
|
void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
|
|
|
|
|
|
/* intel_overlay.c */
|
|
void intel_setup_overlay(struct drm_device *dev);
|
|
void intel_cleanup_overlay(struct drm_device *dev);
|
|
int intel_overlay_switch_off(struct intel_overlay *overlay);
|
|
int intel_overlay_put_image(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int intel_overlay_attrs(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
void intel_overlay_reset(struct drm_i915_private *dev_priv);
|
|
|
|
|
|
/* intel_panel.c */
|
|
int intel_panel_init(struct intel_panel *panel,
|
|
struct drm_display_mode *fixed_mode,
|
|
struct drm_display_mode *downclock_mode);
|
|
void intel_panel_fini(struct intel_panel *panel);
|
|
void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
|
|
struct drm_display_mode *adjusted_mode);
|
|
void intel_pch_panel_fitting(struct intel_crtc *crtc,
|
|
struct intel_crtc_state *pipe_config,
|
|
int fitting_mode);
|
|
void intel_gmch_panel_fitting(struct intel_crtc *crtc,
|
|
struct intel_crtc_state *pipe_config,
|
|
int fitting_mode);
|
|
void intel_panel_set_backlight_acpi(struct intel_connector *connector,
|
|
u32 level, u32 max);
|
|
int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
|
|
void intel_panel_enable_backlight(struct intel_connector *connector);
|
|
void intel_panel_disable_backlight(struct intel_connector *connector);
|
|
void intel_panel_destroy_backlight(struct drm_connector *connector);
|
|
void intel_panel_init_backlight_funcs(struct drm_device *dev);
|
|
enum drm_connector_status intel_panel_detect(struct drm_device *dev);
|
|
extern struct drm_display_mode *intel_find_panel_downclock(
|
|
struct drm_device *dev,
|
|
struct drm_display_mode *fixed_mode,
|
|
struct drm_connector *connector);
|
|
void intel_backlight_register(struct drm_device *dev);
|
|
void intel_backlight_unregister(struct drm_device *dev);
|
|
|
|
|
|
/* intel_psr.c */
|
|
void intel_psr_enable(struct intel_dp *intel_dp);
|
|
void intel_psr_disable(struct intel_dp *intel_dp);
|
|
void intel_psr_invalidate(struct drm_device *dev,
|
|
unsigned frontbuffer_bits);
|
|
void intel_psr_flush(struct drm_device *dev,
|
|
unsigned frontbuffer_bits);
|
|
void intel_psr_init(struct drm_device *dev);
|
|
void intel_psr_single_frame_update(struct drm_device *dev);
|
|
|
|
/* intel_runtime_pm.c */
|
|
int intel_power_domains_init(struct drm_i915_private *);
|
|
void intel_power_domains_fini(struct drm_i915_private *);
|
|
void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
|
|
void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
|
|
|
|
bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
|
|
enum intel_display_power_domain domain);
|
|
bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
|
|
enum intel_display_power_domain domain);
|
|
void intel_display_power_get(struct drm_i915_private *dev_priv,
|
|
enum intel_display_power_domain domain);
|
|
void intel_display_power_put(struct drm_i915_private *dev_priv,
|
|
enum intel_display_power_domain domain);
|
|
void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
|
|
void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
|
|
void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
|
|
void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
|
|
void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
|
|
|
|
void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
|
|
|
|
/* intel_pm.c */
|
|
void intel_init_clock_gating(struct drm_device *dev);
|
|
void intel_suspend_hw(struct drm_device *dev);
|
|
int ilk_wm_max_level(const struct drm_device *dev);
|
|
void intel_update_watermarks(struct drm_crtc *crtc);
|
|
void intel_update_sprite_watermarks(struct drm_plane *plane,
|
|
struct drm_crtc *crtc,
|
|
uint32_t sprite_width,
|
|
uint32_t sprite_height,
|
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int pixel_size,
|
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bool enabled, bool scaled);
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void intel_init_pm(struct drm_device *dev);
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void intel_pm_setup(struct drm_device *dev);
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void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
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void intel_gpu_ips_teardown(void);
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void intel_init_gt_powersave(struct drm_device *dev);
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|
void intel_cleanup_gt_powersave(struct drm_device *dev);
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|
void intel_enable_gt_powersave(struct drm_device *dev);
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|
void intel_disable_gt_powersave(struct drm_device *dev);
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|
void intel_suspend_gt_powersave(struct drm_device *dev);
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|
void intel_reset_gt_powersave(struct drm_device *dev);
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|
void gen6_update_ring_freq(struct drm_device *dev);
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|
void gen6_rps_busy(struct drm_i915_private *dev_priv);
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|
void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
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|
void gen6_rps_idle(struct drm_i915_private *dev_priv);
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|
void gen6_rps_boost(struct drm_i915_private *dev_priv,
|
|
struct intel_rps_client *rps,
|
|
unsigned long submitted);
|
|
void intel_queue_rps_boost_for_request(struct drm_device *dev,
|
|
struct drm_i915_gem_request *req);
|
|
void ilk_wm_get_hw_state(struct drm_device *dev);
|
|
void skl_wm_get_hw_state(struct drm_device *dev);
|
|
void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
|
|
struct skl_ddb_allocation *ddb /* out */);
|
|
uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
|
|
|
|
/* intel_sdvo.c */
|
|
bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
|
|
|
|
|
|
/* intel_sprite.c */
|
|
int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
|
|
int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
bool intel_pipe_update_start(struct intel_crtc *crtc,
|
|
uint32_t *start_vbl_count);
|
|
void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
|
|
|
|
/* intel_tv.c */
|
|
void intel_tv_init(struct drm_device *dev);
|
|
|
|
/* intel_atomic.c */
|
|
int intel_atomic_check(struct drm_device *dev,
|
|
struct drm_atomic_state *state);
|
|
int intel_atomic_commit(struct drm_device *dev,
|
|
struct drm_atomic_state *state,
|
|
bool async);
|
|
int intel_connector_atomic_get_property(struct drm_connector *connector,
|
|
const struct drm_connector_state *state,
|
|
struct drm_property *property,
|
|
uint64_t *val);
|
|
struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
|
|
void intel_crtc_destroy_state(struct drm_crtc *crtc,
|
|
struct drm_crtc_state *state);
|
|
struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
|
|
void intel_atomic_state_clear(struct drm_atomic_state *);
|
|
struct intel_shared_dpll_config *
|
|
intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
|
|
|
|
static inline struct intel_crtc_state *
|
|
intel_atomic_get_crtc_state(struct drm_atomic_state *state,
|
|
struct intel_crtc *crtc)
|
|
{
|
|
struct drm_crtc_state *crtc_state;
|
|
crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
|
|
if (IS_ERR(crtc_state))
|
|
return ERR_CAST(crtc_state);
|
|
|
|
return to_intel_crtc_state(crtc_state);
|
|
}
|
|
int intel_atomic_setup_scalers(struct drm_device *dev,
|
|
struct intel_crtc *intel_crtc,
|
|
struct intel_crtc_state *crtc_state);
|
|
|
|
/* intel_atomic_plane.c */
|
|
struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
|
|
struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
|
|
void intel_plane_destroy_state(struct drm_plane *plane,
|
|
struct drm_plane_state *state);
|
|
extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
|
|
|
|
#endif /* __INTEL_DRV_H__ */
|