![Linus Torvalds](/assets/img/avatar_default.png)
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
170 lines
4.6 KiB
C
170 lines
4.6 KiB
C
/*
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*
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* BRIEF MODULE DESCRIPTION
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* Galileo EV96100 board specific pci support.
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*
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* Copyright 2000 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ppopov@mvista.com or source@mvista.com
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*
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* This file was derived from Carsten Langgaard's
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* arch/mips/mips-boards/generic/pci.c
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*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <asm/delay.h>
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#include <asm/gt64120.h>
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#include <asm/galileo-boards/ev96100.h>
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_WRITE 1
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static int static gt96100_config_access(unsigned char access_type,
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struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
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{
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unsigned char bus = bus->number;
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u32 intr;
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/*
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* Because of a bug in the galileo (for slot 31).
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*/
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if (bus == 0 && devfn >= PCI_DEVFN(31, 0))
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return PCIBIOS_DEVICE_NOT_FOUND;
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/* Clear cause register bits */
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GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
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GT_INTRCAUSE_TARABORT0_BIT));
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/* Setup address */
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GT_WRITE(GT_PCI0_CFGADDR_OFS,
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(bus << GT_PCI0_CFGADDR_BUSNUM_SHF) |
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(devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
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((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
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GT_PCI0_CFGADDR_CONFIGEN_BIT);
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udelay(2);
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if (access_type == PCI_ACCESS_WRITE) {
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if (devfn != 0)
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*data = le32_to_cpu(*data);
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GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);
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} else {
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*data = GT_READ(GT_PCI0_CFGDATA_OFS);
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if (devfn != 0)
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*data = le32_to_cpu(*data);
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}
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udelay(2);
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/* Check for master or target abort */
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intr = GT_READ(GT_INTRCAUSE_OFS);
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if (intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) {
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/* Error occured */
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/* Clear bits */
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GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
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GT_INTRCAUSE_TARABORT0_BIT));
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return -1;
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}
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return 0;
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}
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/*
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* We can't address 8 and 16 bit words directly. Instead we have to
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* read/write a 32bit word and mask/modify the data we actually want.
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*/
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static int gt96100_pcibios_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 * val)
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{
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u32 data = 0;
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if (gt96100_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
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return PCIBIOS_DEVICE_NOT_FOUND;
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switch (size) {
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case 1:
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*val = (data >> ((where & 3) << 3)) & 0xff;
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break;
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case 2:
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*val = (data >> ((where & 3) << 3)) & 0xffff;
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break;
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case 4:
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*val = data;
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int gt96100_pcibios_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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u32 data = 0;
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switch (size) {
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case 1:
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if (gt96100_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
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return -1;
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data = (data & ~(0xff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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if (gt96100_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
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return -1;
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return PCIBIOS_SUCCESSFUL;
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case 2:
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if (gt96100_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
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return -1;
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data = (data & ~(0xffff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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if (gt96100_config_access(PCI_ACCESS_WRITE, dev, where, &data))
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return -1;
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return PCIBIOS_SUCCESSFUL;
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case 4:
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if (gt96100_config_access(PCI_ACCESS_WRITE, dev, where, &val))
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return -1;
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return PCIBIOS_SUCCESSFUL;
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}
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}
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struct pci_ops gt96100_pci_ops = {
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.read = gt96100_pcibios_read,
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.write = gt96100_pcibios_write
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};
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