![Linus Torvalds](/assets/img/avatar_default.png)
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
216 lines
5 KiB
C
216 lines
5 KiB
C
/*
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*
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* BRIEF MODULE DESCRIPTION
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* IT8172 system controller specific pci support.
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*
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* Copyright 2000 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ppopov@mvista.com or source@mvista.com
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*
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* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <asm/it8172/it8172.h>
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#include <asm/it8172/it8172_pci.h>
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_WRITE 1
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(x...) printk(x)
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#else
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#define DBG(x...)
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#endif
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static struct resource pci_mem_resource_1;
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static struct resource pci_io_resource = {
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"io pci IO space",
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0x14018000,
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0x17FFFFFF,
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IORESOURCE_IO
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};
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static struct resource pci_mem_resource_0 = {
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"ext pci memory space 0/1",
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0x10101000,
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0x13FFFFFF,
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IORESOURCE_MEM,
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&pci_mem_resource_0,
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NULL,
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&pci_mem_resource_1
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};
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static struct resource pci_mem_resource_1 = {
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"ext pci memory space 2/3",
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0x1A000000,
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0x1FBFFFFF,
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IORESOURCE_MEM,
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&pci_mem_resource_0,
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NULL,
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NULL
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};
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extern struct pci_ops it8172_pci_ops;
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struct pci_controller it8172_controller = {
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.pci_ops = &it8172_pci_ops,
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.io_resource = &pci_io_resource,
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.mem_resource = &pci_mem_resource_0,
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};
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static int it8172_pcibios_config_access(unsigned char access_type,
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struct pci_bus *bus,
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unsigned int devfn, int where,
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u32 * data)
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{
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/*
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* config cycles are on 4 byte boundary only
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*/
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/* Setup address */
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IT_WRITE(IT_CONFADDR, (bus->number << IT_BUSNUM_SHF) |
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(devfn << IT_FUNCNUM_SHF) | (where & ~0x3));
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if (access_type == PCI_ACCESS_WRITE) {
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IT_WRITE(IT_CONFDATA, *data);
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} else {
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IT_READ(IT_CONFDATA, *data);
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}
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/*
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* Revisit: check for master or target abort.
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*/
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return 0;
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}
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/*
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* We can't address 8 and 16 bit words directly. Instead we have to
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* read/write a 32bit word and mask/modify the data we actually want.
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*/
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static write_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 val)
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{
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u32 data = 0;
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switch (size) {
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case 1:
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if (it8172_pcibios_config_access
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(PCI_ACCESS_READ, dev, where, &data))
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return -1;
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*val = (data >> ((where & 3) << 3)) & 0xff;
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return PCIBIOS_SUCCESSFUL;
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case 2:
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if (where & 1)
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return PCIBIOS_BAD_REGISTER_NUMBER;
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if (it8172_pcibios_config_access
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(PCI_ACCESS_READ, dev, where, &data))
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return -1;
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*val = (data >> ((where & 3) << 3)) & 0xffff;
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DBG("cfg read word: bus %d dev_fn %x where %x: val %x\n",
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dev->bus->number, dev->devfn, where, *val);
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return PCIBIOS_SUCCESSFUL;
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case 4:
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if (where & 3)
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return PCIBIOS_BAD_REGISTER_NUMBER;
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if (it8172_pcibios_config_access
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(PCI_ACCESS_READ, dev, where, &data))
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return -1;
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*val = data;
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return PCIBIOS_SUCCESSFUL;
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}
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}
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static write_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 val)
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{
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u32 data = 0;
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switch (size) {
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case 1:
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if (it8172_pcibios_config_access
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(PCI_ACCESS_READ, dev, where, &data))
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return -1;
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data = (data & ~(0xff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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if (it8172_pcibios_config_access
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(PCI_ACCESS_WRITE, dev, where, &data))
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return -1;
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return PCIBIOS_SUCCESSFUL;
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case 2:
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if (where & 1)
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return PCIBIOS_BAD_REGISTER_NUMBER;
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if (it8172_pcibios_config_access
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(PCI_ACCESS_READ, dev, where, &data))
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eturn - 1;
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data = (data & ~(0xffff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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if (it8172_pcibios_config_access
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(PCI_ACCESS_WRITE, dev, where, &data))
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return -1;
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return PCIBIOS_SUCCESSFUL;
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case 4:
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if (where & 3)
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return PCIBIOS_BAD_REGISTER_NUMBER;
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if (it8172_pcibios_config_access
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(PCI_ACCESS_WRITE, dev, where, &val))
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return -1;
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return PCIBIOS_SUCCESSFUL;
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}
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}
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struct pci_ops it8172_pci_ops = {
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.read = read_config,
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.write = write_config,
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};
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