![Alex Deucher](/assets/img/avatar_default.png)
Change vddci as well as vddc when changing power modes on evergreen/ni. Also, properly set vddci on boot up for ni cards. The vbios only sets the limited clocks and voltages on boot until the mc ucode is loaded. This should fix stability problems on some btc cards. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
865 lines
26 KiB
C
865 lines
26 KiB
C
/*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Rafał Miłecki <zajec5@gmail.com>
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* Alex Deucher <alexdeucher@gmail.com>
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*/
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#include "drmP.h"
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#include "radeon.h"
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#include "avivod.h"
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#include "atom.h"
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#ifdef CONFIG_ACPI
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#include <linux/acpi.h>
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#endif
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#include <linux/power_supply.h>
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#include <linux/hwmon.h>
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#include <linux/hwmon-sysfs.h>
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#define RADEON_IDLE_LOOP_MS 100
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#define RADEON_RECLOCK_DELAY_MS 200
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#define RADEON_WAIT_VBLANK_TIMEOUT 200
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#define RADEON_WAIT_IDLE_TIMEOUT 200
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static const char *radeon_pm_state_type_name[5] = {
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"Default",
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"Powersave",
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"Battery",
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"Balanced",
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"Performance",
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};
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static void radeon_dynpm_idle_work_handler(struct work_struct *work);
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static int radeon_debugfs_pm_init(struct radeon_device *rdev);
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static bool radeon_pm_in_vbl(struct radeon_device *rdev);
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static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
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static void radeon_pm_update_profile(struct radeon_device *rdev);
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static void radeon_pm_set_clocks(struct radeon_device *rdev);
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#define ACPI_AC_CLASS "ac_adapter"
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#ifdef CONFIG_ACPI
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static int radeon_acpi_event(struct notifier_block *nb,
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unsigned long val,
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void *data)
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{
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struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
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struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
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if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
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if (power_supply_is_system_supplied() > 0)
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DRM_DEBUG_DRIVER("pm: AC\n");
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else
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DRM_DEBUG_DRIVER("pm: DC\n");
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if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
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if (rdev->pm.profile == PM_PROFILE_AUTO) {
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mutex_lock(&rdev->pm.mutex);
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radeon_pm_update_profile(rdev);
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radeon_pm_set_clocks(rdev);
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mutex_unlock(&rdev->pm.mutex);
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}
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}
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}
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return NOTIFY_OK;
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}
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#endif
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static void radeon_pm_update_profile(struct radeon_device *rdev)
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{
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switch (rdev->pm.profile) {
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case PM_PROFILE_DEFAULT:
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rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
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break;
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case PM_PROFILE_AUTO:
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if (power_supply_is_system_supplied() > 0) {
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if (rdev->pm.active_crtc_count > 1)
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rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
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else
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rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
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} else {
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if (rdev->pm.active_crtc_count > 1)
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rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
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else
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rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
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}
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break;
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case PM_PROFILE_LOW:
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if (rdev->pm.active_crtc_count > 1)
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rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
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else
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rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
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break;
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case PM_PROFILE_MID:
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if (rdev->pm.active_crtc_count > 1)
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rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
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else
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rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
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break;
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case PM_PROFILE_HIGH:
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if (rdev->pm.active_crtc_count > 1)
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rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
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else
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rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
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break;
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}
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if (rdev->pm.active_crtc_count == 0) {
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rdev->pm.requested_power_state_index =
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rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
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rdev->pm.requested_clock_mode_index =
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rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
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} else {
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rdev->pm.requested_power_state_index =
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rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
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rdev->pm.requested_clock_mode_index =
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rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
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}
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}
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static void radeon_unmap_vram_bos(struct radeon_device *rdev)
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{
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struct radeon_bo *bo, *n;
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if (list_empty(&rdev->gem.objects))
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return;
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list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
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if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
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ttm_bo_unmap_virtual(&bo->tbo);
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}
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}
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static void radeon_sync_with_vblank(struct radeon_device *rdev)
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{
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if (rdev->pm.active_crtcs) {
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rdev->pm.vblank_sync = false;
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wait_event_timeout(
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rdev->irq.vblank_queue, rdev->pm.vblank_sync,
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msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
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}
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}
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static void radeon_set_power_state(struct radeon_device *rdev)
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{
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u32 sclk, mclk;
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bool misc_after = false;
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if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
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(rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
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return;
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if (radeon_gui_idle(rdev)) {
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sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
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clock_info[rdev->pm.requested_clock_mode_index].sclk;
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if (sclk > rdev->pm.default_sclk)
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sclk = rdev->pm.default_sclk;
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mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
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clock_info[rdev->pm.requested_clock_mode_index].mclk;
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if (mclk > rdev->pm.default_mclk)
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mclk = rdev->pm.default_mclk;
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/* upvolt before raising clocks, downvolt after lowering clocks */
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if (sclk < rdev->pm.current_sclk)
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misc_after = true;
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radeon_sync_with_vblank(rdev);
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if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
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if (!radeon_pm_in_vbl(rdev))
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return;
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}
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radeon_pm_prepare(rdev);
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if (!misc_after)
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/* voltage, pcie lanes, etc.*/
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radeon_pm_misc(rdev);
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/* set engine clock */
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if (sclk != rdev->pm.current_sclk) {
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radeon_pm_debug_check_in_vbl(rdev, false);
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radeon_set_engine_clock(rdev, sclk);
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radeon_pm_debug_check_in_vbl(rdev, true);
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rdev->pm.current_sclk = sclk;
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DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
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}
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/* set memory clock */
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if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
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radeon_pm_debug_check_in_vbl(rdev, false);
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radeon_set_memory_clock(rdev, mclk);
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radeon_pm_debug_check_in_vbl(rdev, true);
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rdev->pm.current_mclk = mclk;
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DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
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}
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if (misc_after)
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/* voltage, pcie lanes, etc.*/
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radeon_pm_misc(rdev);
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radeon_pm_finish(rdev);
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rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
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rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
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} else
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DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
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}
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static void radeon_pm_set_clocks(struct radeon_device *rdev)
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{
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int i;
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/* no need to take locks, etc. if nothing's going to change */
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if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
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(rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
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return;
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mutex_lock(&rdev->ddev->struct_mutex);
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mutex_lock(&rdev->vram_mutex);
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mutex_lock(&rdev->cp.mutex);
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/* gui idle int has issues on older chips it seems */
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if (rdev->family >= CHIP_R600) {
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if (rdev->irq.installed) {
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/* wait for GPU idle */
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rdev->pm.gui_idle = false;
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rdev->irq.gui_idle = true;
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radeon_irq_set(rdev);
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wait_event_interruptible_timeout(
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rdev->irq.idle_queue, rdev->pm.gui_idle,
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msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
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rdev->irq.gui_idle = false;
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radeon_irq_set(rdev);
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}
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} else {
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if (rdev->cp.ready) {
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struct radeon_fence *fence;
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radeon_ring_alloc(rdev, 64);
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radeon_fence_create(rdev, &fence);
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radeon_fence_emit(rdev, fence);
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radeon_ring_commit(rdev);
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radeon_fence_wait(fence, false);
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radeon_fence_unref(&fence);
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}
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}
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radeon_unmap_vram_bos(rdev);
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if (rdev->irq.installed) {
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for (i = 0; i < rdev->num_crtc; i++) {
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if (rdev->pm.active_crtcs & (1 << i)) {
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rdev->pm.req_vblank |= (1 << i);
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drm_vblank_get(rdev->ddev, i);
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}
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}
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}
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radeon_set_power_state(rdev);
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if (rdev->irq.installed) {
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for (i = 0; i < rdev->num_crtc; i++) {
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if (rdev->pm.req_vblank & (1 << i)) {
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rdev->pm.req_vblank &= ~(1 << i);
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drm_vblank_put(rdev->ddev, i);
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}
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}
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}
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/* update display watermarks based on new power state */
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radeon_update_bandwidth_info(rdev);
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if (rdev->pm.active_crtc_count)
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radeon_bandwidth_update(rdev);
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rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
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mutex_unlock(&rdev->cp.mutex);
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mutex_unlock(&rdev->vram_mutex);
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mutex_unlock(&rdev->ddev->struct_mutex);
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}
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static void radeon_pm_print_states(struct radeon_device *rdev)
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{
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int i, j;
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struct radeon_power_state *power_state;
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struct radeon_pm_clock_info *clock_info;
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DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
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for (i = 0; i < rdev->pm.num_power_states; i++) {
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power_state = &rdev->pm.power_state[i];
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DRM_DEBUG_DRIVER("State %d: %s\n", i,
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radeon_pm_state_type_name[power_state->type]);
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if (i == rdev->pm.default_power_state_index)
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DRM_DEBUG_DRIVER("\tDefault");
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if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
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DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
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if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
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DRM_DEBUG_DRIVER("\tSingle display only\n");
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DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
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for (j = 0; j < power_state->num_clock_modes; j++) {
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clock_info = &(power_state->clock_info[j]);
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if (rdev->flags & RADEON_IS_IGP)
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DRM_DEBUG_DRIVER("\t\t%d e: %d%s\n",
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j,
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clock_info->sclk * 10,
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clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
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else
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DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d%s\n",
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j,
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clock_info->sclk * 10,
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clock_info->mclk * 10,
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clock_info->voltage.voltage,
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clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
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}
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}
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}
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static ssize_t radeon_get_pm_profile(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
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struct radeon_device *rdev = ddev->dev_private;
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int cp = rdev->pm.profile;
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return snprintf(buf, PAGE_SIZE, "%s\n",
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(cp == PM_PROFILE_AUTO) ? "auto" :
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(cp == PM_PROFILE_LOW) ? "low" :
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(cp == PM_PROFILE_MID) ? "mid" :
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(cp == PM_PROFILE_HIGH) ? "high" : "default");
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}
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static ssize_t radeon_set_pm_profile(struct device *dev,
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struct device_attribute *attr,
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const char *buf,
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size_t count)
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{
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struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
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struct radeon_device *rdev = ddev->dev_private;
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mutex_lock(&rdev->pm.mutex);
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if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
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if (strncmp("default", buf, strlen("default")) == 0)
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rdev->pm.profile = PM_PROFILE_DEFAULT;
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else if (strncmp("auto", buf, strlen("auto")) == 0)
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rdev->pm.profile = PM_PROFILE_AUTO;
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else if (strncmp("low", buf, strlen("low")) == 0)
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rdev->pm.profile = PM_PROFILE_LOW;
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else if (strncmp("mid", buf, strlen("mid")) == 0)
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rdev->pm.profile = PM_PROFILE_MID;
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else if (strncmp("high", buf, strlen("high")) == 0)
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rdev->pm.profile = PM_PROFILE_HIGH;
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else {
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count = -EINVAL;
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goto fail;
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}
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radeon_pm_update_profile(rdev);
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radeon_pm_set_clocks(rdev);
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} else
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count = -EINVAL;
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fail:
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mutex_unlock(&rdev->pm.mutex);
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return count;
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}
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static ssize_t radeon_get_pm_method(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
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struct radeon_device *rdev = ddev->dev_private;
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int pm = rdev->pm.pm_method;
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return snprintf(buf, PAGE_SIZE, "%s\n",
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(pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
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}
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static ssize_t radeon_set_pm_method(struct device *dev,
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struct device_attribute *attr,
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const char *buf,
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size_t count)
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{
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struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
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struct radeon_device *rdev = ddev->dev_private;
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|
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if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
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mutex_lock(&rdev->pm.mutex);
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rdev->pm.pm_method = PM_METHOD_DYNPM;
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rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
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rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
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mutex_unlock(&rdev->pm.mutex);
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} else if (strncmp("profile", buf, strlen("profile")) == 0) {
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mutex_lock(&rdev->pm.mutex);
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/* disable dynpm */
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rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
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rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
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rdev->pm.pm_method = PM_METHOD_PROFILE;
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mutex_unlock(&rdev->pm.mutex);
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cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
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} else {
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count = -EINVAL;
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goto fail;
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}
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radeon_pm_compute_clocks(rdev);
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fail:
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return count;
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}
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static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
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static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
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static ssize_t radeon_hwmon_show_temp(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
|
|
struct radeon_device *rdev = ddev->dev_private;
|
|
int temp;
|
|
|
|
switch (rdev->pm.int_thermal_type) {
|
|
case THERMAL_TYPE_RV6XX:
|
|
temp = rv6xx_get_temp(rdev);
|
|
break;
|
|
case THERMAL_TYPE_RV770:
|
|
temp = rv770_get_temp(rdev);
|
|
break;
|
|
case THERMAL_TYPE_EVERGREEN:
|
|
case THERMAL_TYPE_NI:
|
|
temp = evergreen_get_temp(rdev);
|
|
break;
|
|
case THERMAL_TYPE_SUMO:
|
|
temp = sumo_get_temp(rdev);
|
|
break;
|
|
default:
|
|
temp = 0;
|
|
break;
|
|
}
|
|
|
|
return snprintf(buf, PAGE_SIZE, "%d\n", temp);
|
|
}
|
|
|
|
static ssize_t radeon_hwmon_show_name(struct device *dev,
|
|
struct device_attribute *attr,
|
|
char *buf)
|
|
{
|
|
return sprintf(buf, "radeon\n");
|
|
}
|
|
|
|
static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
|
|
static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
|
|
|
|
static struct attribute *hwmon_attributes[] = {
|
|
&sensor_dev_attr_temp1_input.dev_attr.attr,
|
|
&sensor_dev_attr_name.dev_attr.attr,
|
|
NULL
|
|
};
|
|
|
|
static const struct attribute_group hwmon_attrgroup = {
|
|
.attrs = hwmon_attributes,
|
|
};
|
|
|
|
static int radeon_hwmon_init(struct radeon_device *rdev)
|
|
{
|
|
int err = 0;
|
|
|
|
rdev->pm.int_hwmon_dev = NULL;
|
|
|
|
switch (rdev->pm.int_thermal_type) {
|
|
case THERMAL_TYPE_RV6XX:
|
|
case THERMAL_TYPE_RV770:
|
|
case THERMAL_TYPE_EVERGREEN:
|
|
case THERMAL_TYPE_SUMO:
|
|
rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
|
|
if (IS_ERR(rdev->pm.int_hwmon_dev)) {
|
|
err = PTR_ERR(rdev->pm.int_hwmon_dev);
|
|
dev_err(rdev->dev,
|
|
"Unable to register hwmon device: %d\n", err);
|
|
break;
|
|
}
|
|
dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
|
|
err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
|
|
&hwmon_attrgroup);
|
|
if (err) {
|
|
dev_err(rdev->dev,
|
|
"Unable to create hwmon sysfs file: %d\n", err);
|
|
hwmon_device_unregister(rdev->dev);
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
static void radeon_hwmon_fini(struct radeon_device *rdev)
|
|
{
|
|
if (rdev->pm.int_hwmon_dev) {
|
|
sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
|
|
hwmon_device_unregister(rdev->pm.int_hwmon_dev);
|
|
}
|
|
}
|
|
|
|
void radeon_pm_suspend(struct radeon_device *rdev)
|
|
{
|
|
mutex_lock(&rdev->pm.mutex);
|
|
if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
|
|
if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
|
|
rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
|
|
}
|
|
mutex_unlock(&rdev->pm.mutex);
|
|
|
|
cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
|
|
}
|
|
|
|
void radeon_pm_resume(struct radeon_device *rdev)
|
|
{
|
|
/* set up the default clocks if the MC ucode is loaded */
|
|
if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
|
|
if (rdev->pm.default_vddc)
|
|
radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
|
|
SET_VOLTAGE_TYPE_ASIC_VDDC);
|
|
if (rdev->pm.default_vddci)
|
|
radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
|
|
SET_VOLTAGE_TYPE_ASIC_VDDCI);
|
|
if (rdev->pm.default_sclk)
|
|
radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
|
|
if (rdev->pm.default_mclk)
|
|
radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
|
|
}
|
|
/* asic init will reset the default power state */
|
|
mutex_lock(&rdev->pm.mutex);
|
|
rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
|
|
rdev->pm.current_clock_mode_index = 0;
|
|
rdev->pm.current_sclk = rdev->pm.default_sclk;
|
|
rdev->pm.current_mclk = rdev->pm.default_mclk;
|
|
rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
|
|
rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
|
|
if (rdev->pm.pm_method == PM_METHOD_DYNPM
|
|
&& rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
|
|
rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
|
|
schedule_delayed_work(&rdev->pm.dynpm_idle_work,
|
|
msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
|
|
}
|
|
mutex_unlock(&rdev->pm.mutex);
|
|
radeon_pm_compute_clocks(rdev);
|
|
}
|
|
|
|
int radeon_pm_init(struct radeon_device *rdev)
|
|
{
|
|
int ret;
|
|
|
|
/* default to profile method */
|
|
rdev->pm.pm_method = PM_METHOD_PROFILE;
|
|
rdev->pm.profile = PM_PROFILE_DEFAULT;
|
|
rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
|
|
rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
|
|
rdev->pm.dynpm_can_upclock = true;
|
|
rdev->pm.dynpm_can_downclock = true;
|
|
rdev->pm.default_sclk = rdev->clock.default_sclk;
|
|
rdev->pm.default_mclk = rdev->clock.default_mclk;
|
|
rdev->pm.current_sclk = rdev->clock.default_sclk;
|
|
rdev->pm.current_mclk = rdev->clock.default_mclk;
|
|
rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
|
|
|
|
if (rdev->bios) {
|
|
if (rdev->is_atom_bios)
|
|
radeon_atombios_get_power_modes(rdev);
|
|
else
|
|
radeon_combios_get_power_modes(rdev);
|
|
radeon_pm_print_states(rdev);
|
|
radeon_pm_init_profile(rdev);
|
|
/* set up the default clocks if the MC ucode is loaded */
|
|
if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
|
|
if (rdev->pm.default_vddc)
|
|
radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
|
|
SET_VOLTAGE_TYPE_ASIC_VDDC);
|
|
if (rdev->pm.default_sclk)
|
|
radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
|
|
if (rdev->pm.default_mclk)
|
|
radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
|
|
}
|
|
}
|
|
|
|
/* set up the internal thermal sensor if applicable */
|
|
ret = radeon_hwmon_init(rdev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
|
|
|
|
if (rdev->pm.num_power_states > 1) {
|
|
/* where's the best place to put these? */
|
|
ret = device_create_file(rdev->dev, &dev_attr_power_profile);
|
|
if (ret)
|
|
DRM_ERROR("failed to create device file for power profile\n");
|
|
ret = device_create_file(rdev->dev, &dev_attr_power_method);
|
|
if (ret)
|
|
DRM_ERROR("failed to create device file for power method\n");
|
|
|
|
#ifdef CONFIG_ACPI
|
|
rdev->acpi_nb.notifier_call = radeon_acpi_event;
|
|
register_acpi_notifier(&rdev->acpi_nb);
|
|
#endif
|
|
if (radeon_debugfs_pm_init(rdev)) {
|
|
DRM_ERROR("Failed to register debugfs file for PM!\n");
|
|
}
|
|
|
|
DRM_INFO("radeon: power management initialized\n");
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void radeon_pm_fini(struct radeon_device *rdev)
|
|
{
|
|
if (rdev->pm.num_power_states > 1) {
|
|
mutex_lock(&rdev->pm.mutex);
|
|
if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
|
|
rdev->pm.profile = PM_PROFILE_DEFAULT;
|
|
radeon_pm_update_profile(rdev);
|
|
radeon_pm_set_clocks(rdev);
|
|
} else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
|
|
/* reset default clocks */
|
|
rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
|
|
rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
|
|
radeon_pm_set_clocks(rdev);
|
|
}
|
|
mutex_unlock(&rdev->pm.mutex);
|
|
|
|
cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
|
|
|
|
device_remove_file(rdev->dev, &dev_attr_power_profile);
|
|
device_remove_file(rdev->dev, &dev_attr_power_method);
|
|
#ifdef CONFIG_ACPI
|
|
unregister_acpi_notifier(&rdev->acpi_nb);
|
|
#endif
|
|
}
|
|
|
|
if (rdev->pm.power_state)
|
|
kfree(rdev->pm.power_state);
|
|
|
|
radeon_hwmon_fini(rdev);
|
|
}
|
|
|
|
void radeon_pm_compute_clocks(struct radeon_device *rdev)
|
|
{
|
|
struct drm_device *ddev = rdev->ddev;
|
|
struct drm_crtc *crtc;
|
|
struct radeon_crtc *radeon_crtc;
|
|
|
|
if (rdev->pm.num_power_states < 2)
|
|
return;
|
|
|
|
mutex_lock(&rdev->pm.mutex);
|
|
|
|
rdev->pm.active_crtcs = 0;
|
|
rdev->pm.active_crtc_count = 0;
|
|
list_for_each_entry(crtc,
|
|
&ddev->mode_config.crtc_list, head) {
|
|
radeon_crtc = to_radeon_crtc(crtc);
|
|
if (radeon_crtc->enabled) {
|
|
rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
|
|
rdev->pm.active_crtc_count++;
|
|
}
|
|
}
|
|
|
|
if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
|
|
radeon_pm_update_profile(rdev);
|
|
radeon_pm_set_clocks(rdev);
|
|
} else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
|
|
if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
|
|
if (rdev->pm.active_crtc_count > 1) {
|
|
if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
|
|
cancel_delayed_work(&rdev->pm.dynpm_idle_work);
|
|
|
|
rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
|
|
rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
|
|
radeon_pm_get_dynpm_state(rdev);
|
|
radeon_pm_set_clocks(rdev);
|
|
|
|
DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
|
|
}
|
|
} else if (rdev->pm.active_crtc_count == 1) {
|
|
/* TODO: Increase clocks if needed for current mode */
|
|
|
|
if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
|
|
rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
|
|
rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
|
|
radeon_pm_get_dynpm_state(rdev);
|
|
radeon_pm_set_clocks(rdev);
|
|
|
|
schedule_delayed_work(&rdev->pm.dynpm_idle_work,
|
|
msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
|
|
} else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
|
|
rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
|
|
schedule_delayed_work(&rdev->pm.dynpm_idle_work,
|
|
msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
|
|
DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
|
|
}
|
|
} else { /* count == 0 */
|
|
if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
|
|
cancel_delayed_work(&rdev->pm.dynpm_idle_work);
|
|
|
|
rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
|
|
rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
|
|
radeon_pm_get_dynpm_state(rdev);
|
|
radeon_pm_set_clocks(rdev);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
mutex_unlock(&rdev->pm.mutex);
|
|
}
|
|
|
|
static bool radeon_pm_in_vbl(struct radeon_device *rdev)
|
|
{
|
|
int crtc, vpos, hpos, vbl_status;
|
|
bool in_vbl = true;
|
|
|
|
/* Iterate over all active crtc's. All crtc's must be in vblank,
|
|
* otherwise return in_vbl == false.
|
|
*/
|
|
for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
|
|
if (rdev->pm.active_crtcs & (1 << crtc)) {
|
|
vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
|
|
if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
|
|
!(vbl_status & DRM_SCANOUTPOS_INVBL))
|
|
in_vbl = false;
|
|
}
|
|
}
|
|
|
|
return in_vbl;
|
|
}
|
|
|
|
static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
|
|
{
|
|
u32 stat_crtc = 0;
|
|
bool in_vbl = radeon_pm_in_vbl(rdev);
|
|
|
|
if (in_vbl == false)
|
|
DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
|
|
finish ? "exit" : "entry");
|
|
return in_vbl;
|
|
}
|
|
|
|
static void radeon_dynpm_idle_work_handler(struct work_struct *work)
|
|
{
|
|
struct radeon_device *rdev;
|
|
int resched;
|
|
rdev = container_of(work, struct radeon_device,
|
|
pm.dynpm_idle_work.work);
|
|
|
|
resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
|
|
mutex_lock(&rdev->pm.mutex);
|
|
if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
|
|
unsigned long irq_flags;
|
|
int not_processed = 0;
|
|
|
|
read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
|
|
if (!list_empty(&rdev->fence_drv.emited)) {
|
|
struct list_head *ptr;
|
|
list_for_each(ptr, &rdev->fence_drv.emited) {
|
|
/* count up to 3, that's enought info */
|
|
if (++not_processed >= 3)
|
|
break;
|
|
}
|
|
}
|
|
read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
|
|
|
|
if (not_processed >= 3) { /* should upclock */
|
|
if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
|
|
rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
|
|
} else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
|
|
rdev->pm.dynpm_can_upclock) {
|
|
rdev->pm.dynpm_planned_action =
|
|
DYNPM_ACTION_UPCLOCK;
|
|
rdev->pm.dynpm_action_timeout = jiffies +
|
|
msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
|
|
}
|
|
} else if (not_processed == 0) { /* should downclock */
|
|
if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
|
|
rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
|
|
} else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
|
|
rdev->pm.dynpm_can_downclock) {
|
|
rdev->pm.dynpm_planned_action =
|
|
DYNPM_ACTION_DOWNCLOCK;
|
|
rdev->pm.dynpm_action_timeout = jiffies +
|
|
msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
|
|
}
|
|
}
|
|
|
|
/* Note, radeon_pm_set_clocks is called with static_switch set
|
|
* to false since we want to wait for vbl to avoid flicker.
|
|
*/
|
|
if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
|
|
jiffies > rdev->pm.dynpm_action_timeout) {
|
|
radeon_pm_get_dynpm_state(rdev);
|
|
radeon_pm_set_clocks(rdev);
|
|
}
|
|
|
|
schedule_delayed_work(&rdev->pm.dynpm_idle_work,
|
|
msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
|
|
}
|
|
mutex_unlock(&rdev->pm.mutex);
|
|
ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
|
|
}
|
|
|
|
/*
|
|
* Debugfs info
|
|
*/
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
|
|
static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
|
|
{
|
|
struct drm_info_node *node = (struct drm_info_node *) m->private;
|
|
struct drm_device *dev = node->minor->dev;
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
|
|
seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
|
|
seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
|
|
seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
|
|
if (rdev->asic->get_memory_clock)
|
|
seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
|
|
if (rdev->pm.current_vddc)
|
|
seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
|
|
if (rdev->asic->get_pcie_lanes)
|
|
seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct drm_info_list radeon_pm_info_list[] = {
|
|
{"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
|
|
};
|
|
#endif
|
|
|
|
static int radeon_debugfs_pm_init(struct radeon_device *rdev)
|
|
{
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
|
|
#else
|
|
return 0;
|
|
#endif
|
|
}
|