27f6cabc0e
This defines __smp_xxx barriers for blackfin, for use by virtualization. smp_xxx barriers are removed as they are defined correctly by asm-generic/barriers.h Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
87 lines
2.5 KiB
C
87 lines
2.5 KiB
C
/*
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* Copyright 2004-2009 Analog Devices Inc.
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* Tony Kou (tonyko@lineo.ca)
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*
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* Licensed under the GPL-2 or later
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*/
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#ifndef _BLACKFIN_BARRIER_H
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#define _BLACKFIN_BARRIER_H
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#include <asm/cache.h>
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#define nop() __asm__ __volatile__ ("nop;\n\t" : : )
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/*
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* Force strict CPU ordering.
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*/
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#ifdef CONFIG_SMP
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#ifdef __ARCH_SYNC_CORE_DCACHE
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/* Force Core data cache coherence */
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# define mb() do { barrier(); smp_check_barrier(); smp_mark_barrier(); } while (0)
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# define rmb() do { barrier(); smp_check_barrier(); } while (0)
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# define wmb() do { barrier(); smp_mark_barrier(); } while (0)
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/*
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* read_barrier_depends - Flush all pending reads that subsequents reads
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* depend on.
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*
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* No data-dependent reads from memory-like regions are ever reordered
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* over this barrier. All reads preceding this primitive are guaranteed
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* to access memory (but not necessarily other CPUs' caches) before any
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* reads following this primitive that depend on the data return by
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* any of the preceding reads. This primitive is much lighter weight than
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* rmb() on most CPUs, and is never heavier weight than is
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* rmb().
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*
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* These ordering constraints are respected by both the local CPU
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* and the compiler.
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*
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* Ordering is not guaranteed by anything other than these primitives,
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* not even by data dependencies. See the documentation for
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* memory_barrier() for examples and URLs to more information.
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*
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* For example, the following code would force ordering (the initial
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* value of "a" is zero, "b" is one, and "p" is "&a"):
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*
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* <programlisting>
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* CPU 0 CPU 1
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*
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* b = 2;
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* memory_barrier();
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* p = &b; q = p;
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* read_barrier_depends();
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* d = *q;
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* </programlisting>
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*
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* because the read of "*q" depends on the read of "p" and these
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* two reads are separated by a read_barrier_depends(). However,
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* the following code, with the same initial values for "a" and "b":
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*
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* <programlisting>
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* CPU 0 CPU 1
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*
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* a = 2;
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* memory_barrier();
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* b = 3; y = b;
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* read_barrier_depends();
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* x = a;
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* </programlisting>
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*
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* does not enforce ordering, since there is no data dependency between
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* the read of "a" and the read of "b". Therefore, on some CPUs, such
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* as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
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* in cases like this where there are no data dependencies.
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*/
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# define read_barrier_depends() do { barrier(); smp_check_barrier(); } while (0)
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#endif
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#endif /* !CONFIG_SMP */
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#define __smp_mb__before_atomic() barrier()
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#define __smp_mb__after_atomic() barrier()
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#include <asm-generic/barrier.h>
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#endif /* _BLACKFIN_BARRIER_H */
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