Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 cpu-feature updates from Ingo Molnar: - Rework the Intel model names symbols/macros, which were decades of ad-hoc extensions and added random noise. It's now a coherent, easy to follow nomenclature. - Add new Intel CPU model IDs: - "Tiger Lake" desktop and mobile models - "Elkhart Lake" model ID - and the "Lightning Mountain" variant of Airmont, plus support code - Add the new AVX512_VP2INTERSECT instruction to cpufeatures - Remove Intel MPX user-visible APIs and the self-tests, because the toolchain (gcc) is not supporting it going forward. This is the first, lowest-risk phase of MPX removal. - Remove X86_FEATURE_MFENCE_RDTSC - Various smaller cleanups and fixes * 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (25 commits) x86/cpu: Update init data for new Airmont CPU model x86/cpu: Add new Airmont variant to Intel family x86/cpu: Add Elkhart Lake to Intel family x86/cpu: Add Tiger Lake to Intel family x86: Correct misc typos x86/intel: Add common OPTDIFFs x86/intel: Aggregate microserver naming x86/intel: Aggregate big core graphics naming x86/intel: Aggregate big core mobile naming x86/intel: Aggregate big core client naming x86/cpufeature: Explain the macro duplication x86/ftrace: Remove mcount() declaration x86/PCI: Remove superfluous returns from void functions x86/msr-index: Move AMD MSRs where they belong x86/cpu: Use constant definitions for CPU models lib: Remove redundant ftrace flag removal x86/crash: Remove unnecessary comparison x86/bitops: Use __builtin_constant_p() directly instead of IS_IMMEDIATE() x86: Remove X86_FEATURE_MFENCE_RDTSC x86/mpx: Remove MPX APIs ...
This commit is contained in:
commit
22331f8952
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@ -3987,31 +3987,31 @@ static __init void intel_clovertown_quirk(void)
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}
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static const struct x86_cpu_desc isolation_ucodes[] = {
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INTEL_CPU_DESC(INTEL_FAM6_HASWELL_CORE, 3, 0x0000001f),
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INTEL_CPU_DESC(INTEL_FAM6_HASWELL_ULT, 1, 0x0000001e),
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INTEL_CPU_DESC(INTEL_FAM6_HASWELL_GT3E, 1, 0x00000015),
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INTEL_CPU_DESC(INTEL_FAM6_HASWELL, 3, 0x0000001f),
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INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L, 1, 0x0000001e),
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INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G, 1, 0x00000015),
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INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 2, 0x00000037),
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INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 4, 0x0000000a),
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INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_CORE, 4, 0x00000023),
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INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_GT3E, 1, 0x00000014),
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INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_XEON_D, 2, 0x00000010),
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INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_XEON_D, 3, 0x07000009),
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INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_XEON_D, 4, 0x0f000009),
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INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_XEON_D, 5, 0x0e000002),
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INTEL_CPU_DESC(INTEL_FAM6_BROADWELL, 4, 0x00000023),
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INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G, 1, 0x00000014),
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INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 2, 0x00000010),
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INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 3, 0x07000009),
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INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 4, 0x0f000009),
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INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 5, 0x0e000002),
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INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X, 2, 0x0b000014),
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INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 3, 0x00000021),
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INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 4, 0x00000000),
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INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_MOBILE, 3, 0x0000007c),
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INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_DESKTOP, 3, 0x0000007c),
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INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_DESKTOP, 9, 0x0000004e),
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INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_MOBILE, 9, 0x0000004e),
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INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_MOBILE, 10, 0x0000004e),
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INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_MOBILE, 11, 0x0000004e),
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INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_MOBILE, 12, 0x0000004e),
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INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_DESKTOP, 10, 0x0000004e),
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INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_DESKTOP, 11, 0x0000004e),
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INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_DESKTOP, 12, 0x0000004e),
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INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_DESKTOP, 13, 0x0000004e),
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INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_L, 3, 0x0000007c),
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INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE, 3, 0x0000007c),
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INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 9, 0x0000004e),
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INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 9, 0x0000004e),
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INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 10, 0x0000004e),
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INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 11, 0x0000004e),
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INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 12, 0x0000004e),
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INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 10, 0x0000004e),
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INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 11, 0x0000004e),
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INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 12, 0x0000004e),
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INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 13, 0x0000004e),
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{}
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};
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@ -4169,7 +4169,7 @@ static const struct x86_cpu_desc counter_freezing_ucodes[] = {
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INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 2, 0x0000000e),
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INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 9, 0x0000002e),
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INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 10, 0x00000008),
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INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_X, 1, 0x00000028),
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INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_D, 1, 0x00000028),
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INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 1, 0x00000028),
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INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 8, 0x00000006),
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{}
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@ -4667,7 +4667,7 @@ __init int intel_pmu_init(void)
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break;
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case INTEL_FAM6_ATOM_SILVERMONT:
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case INTEL_FAM6_ATOM_SILVERMONT_X:
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case INTEL_FAM6_ATOM_SILVERMONT_D:
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case INTEL_FAM6_ATOM_SILVERMONT_MID:
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case INTEL_FAM6_ATOM_AIRMONT:
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case INTEL_FAM6_ATOM_AIRMONT_MID:
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@ -4689,7 +4689,7 @@ __init int intel_pmu_init(void)
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break;
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case INTEL_FAM6_ATOM_GOLDMONT:
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case INTEL_FAM6_ATOM_GOLDMONT_X:
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case INTEL_FAM6_ATOM_GOLDMONT_D:
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x86_add_quirk(intel_counter_freezing_quirk);
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memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
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sizeof(hw_cache_event_ids));
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@ -4745,7 +4745,7 @@ __init int intel_pmu_init(void)
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name = "goldmont_plus";
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break;
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case INTEL_FAM6_ATOM_TREMONT_X:
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case INTEL_FAM6_ATOM_TREMONT_D:
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x86_pmu.late_ack = true;
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memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
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sizeof(hw_cache_event_ids));
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@ -4881,10 +4881,10 @@ __init int intel_pmu_init(void)
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break;
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case INTEL_FAM6_HASWELL_CORE:
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case INTEL_FAM6_HASWELL:
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case INTEL_FAM6_HASWELL_X:
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case INTEL_FAM6_HASWELL_ULT:
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case INTEL_FAM6_HASWELL_GT3E:
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case INTEL_FAM6_HASWELL_L:
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case INTEL_FAM6_HASWELL_G:
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x86_add_quirk(intel_ht_bug);
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x86_add_quirk(intel_pebs_isolation_quirk);
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x86_pmu.late_ack = true;
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@ -4914,9 +4914,9 @@ __init int intel_pmu_init(void)
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name = "haswell";
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break;
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case INTEL_FAM6_BROADWELL_CORE:
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case INTEL_FAM6_BROADWELL_XEON_D:
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case INTEL_FAM6_BROADWELL_GT3E:
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case INTEL_FAM6_BROADWELL:
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case INTEL_FAM6_BROADWELL_D:
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case INTEL_FAM6_BROADWELL_G:
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case INTEL_FAM6_BROADWELL_X:
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x86_add_quirk(intel_pebs_isolation_quirk);
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x86_pmu.late_ack = true;
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@ -4979,10 +4979,10 @@ __init int intel_pmu_init(void)
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case INTEL_FAM6_SKYLAKE_X:
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pmem = true;
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/* fall through */
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case INTEL_FAM6_SKYLAKE_MOBILE:
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case INTEL_FAM6_SKYLAKE_DESKTOP:
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case INTEL_FAM6_KABYLAKE_MOBILE:
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case INTEL_FAM6_KABYLAKE_DESKTOP:
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case INTEL_FAM6_SKYLAKE_L:
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case INTEL_FAM6_SKYLAKE:
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case INTEL_FAM6_KABYLAKE_L:
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case INTEL_FAM6_KABYLAKE:
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x86_add_quirk(intel_pebs_isolation_quirk);
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x86_pmu.late_ack = true;
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memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
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@ -5026,11 +5026,11 @@ __init int intel_pmu_init(void)
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break;
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case INTEL_FAM6_ICELAKE_X:
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case INTEL_FAM6_ICELAKE_XEON_D:
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case INTEL_FAM6_ICELAKE_D:
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pmem = true;
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/* fall through */
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case INTEL_FAM6_ICELAKE_MOBILE:
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case INTEL_FAM6_ICELAKE_DESKTOP:
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case INTEL_FAM6_ICELAKE_L:
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case INTEL_FAM6_ICELAKE:
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x86_pmu.late_ack = true;
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memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
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memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
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@ -593,40 +593,40 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
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X86_CSTATES_MODEL(INTEL_FAM6_IVYBRIDGE, snb_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_IVYBRIDGE_X, snb_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_CORE, snb_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_HASWELL, snb_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_X, snb_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_GT3E, snb_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_G, snb_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_ULT, hswult_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_L, hswult_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT, slm_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT_X, slm_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT_D, slm_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_ATOM_AIRMONT, slm_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_CORE, snb_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_XEON_D, snb_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_GT3E, snb_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL, snb_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_D, snb_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_G, snb_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_X, snb_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_MOBILE, snb_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_DESKTOP, snb_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_L, snb_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE, snb_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_X, snb_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_MOBILE, hswult_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_DESKTOP, hswult_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_L, hswult_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE, hswult_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_CANNONLAKE_MOBILE, cnl_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_CANNONLAKE_L, cnl_cstates),
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|
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X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNL, knl_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates),
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|
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X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT, glm_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_X, glm_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_D, glm_cstates),
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|
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X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_PLUS, glm_cstates),
|
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|
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X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_MOBILE, snb_cstates),
|
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X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_DESKTOP, snb_cstates),
|
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X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_L, snb_cstates),
|
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X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE, snb_cstates),
|
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{ },
|
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};
|
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MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
|
||||
|
|
|
@ -204,9 +204,9 @@ static int __init pt_pmu_hw_init(void)
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|||
|
||||
/* model-specific quirks */
|
||||
switch (boot_cpu_data.x86_model) {
|
||||
case INTEL_FAM6_BROADWELL_CORE:
|
||||
case INTEL_FAM6_BROADWELL_XEON_D:
|
||||
case INTEL_FAM6_BROADWELL_GT3E:
|
||||
case INTEL_FAM6_BROADWELL:
|
||||
case INTEL_FAM6_BROADWELL_D:
|
||||
case INTEL_FAM6_BROADWELL_G:
|
||||
case INTEL_FAM6_BROADWELL_X:
|
||||
/* not setting BRANCH_EN will #GP, erratum BDM106 */
|
||||
pt_pmu.branch_en_always_on = true;
|
||||
|
|
|
@ -720,27 +720,27 @@ static const struct x86_cpu_id rapl_model_match[] __initconst = {
|
|||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_SANDYBRIDGE_X, model_snbep),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_IVYBRIDGE, model_snb),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_IVYBRIDGE_X, model_snbep),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_HASWELL_CORE, model_hsw),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_HASWELL, model_hsw),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_HASWELL_X, model_hsx),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_HASWELL_ULT, model_hsw),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_HASWELL_GT3E, model_hsw),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_CORE, model_hsw),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_GT3E, model_hsw),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_HASWELL_L, model_hsw),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_HASWELL_G, model_hsw),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL, model_hsw),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_G, model_hsw),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_X, model_hsx),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_XEON_D, model_hsx),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_D, model_hsx),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_XEON_PHI_KNL, model_knl),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_XEON_PHI_KNM, model_knl),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_MOBILE, model_skl),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_DESKTOP, model_skl),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_L, model_skl),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE, model_skl),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_X, model_hsx),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_MOBILE, model_skl),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_DESKTOP, model_skl),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_CANNONLAKE_MOBILE, model_skl),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_L, model_skl),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE, model_skl),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_CANNONLAKE_L, model_skl),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT, model_hsw),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT_X, model_hsw),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT_D, model_hsw),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT_PLUS, model_hsw),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_ICELAKE_MOBILE, model_skl),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_ICELAKE_DESKTOP, model_skl),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_ICELAKE_L, model_skl),
|
||||
X86_RAPL_MODEL_MATCH(INTEL_FAM6_ICELAKE, model_skl),
|
||||
{},
|
||||
};
|
||||
|
||||
|
|
|
@ -1451,29 +1451,29 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = {
|
|||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_WESTMERE_EP, nhm_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SANDYBRIDGE, snb_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_IVYBRIDGE, ivb_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_HASWELL_CORE, hsw_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_HASWELL_ULT, hsw_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_HASWELL_GT3E, hsw_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL_CORE, bdw_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL_GT3E, bdw_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_HASWELL, hsw_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_HASWELL_L, hsw_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_HASWELL_G, hsw_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL, bdw_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL_G, bdw_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SANDYBRIDGE_X, snbep_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_NEHALEM_EX, nhmex_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_WESTMERE_EX, nhmex_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_IVYBRIDGE_X, ivbep_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_HASWELL_X, hswep_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL_X, bdx_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL_XEON_D, bdx_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL_D, bdx_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_XEON_PHI_KNL, knl_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_XEON_PHI_KNM, knl_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SKYLAKE_DESKTOP,skl_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SKYLAKE_MOBILE, skl_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SKYLAKE, skl_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SKYLAKE_L, skl_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SKYLAKE_X, skx_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_KABYLAKE_MOBILE, skl_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_KABYLAKE_DESKTOP, skl_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_ICELAKE_MOBILE, icl_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_KABYLAKE_L, skl_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_KABYLAKE, skl_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_ICELAKE_L, icl_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_ICELAKE_NNPI, icl_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_ICELAKE_DESKTOP, icl_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_ATOM_TREMONT_X, snr_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_ICELAKE, icl_uncore_init),
|
||||
X86_UNCORE_MODEL_MATCH(INTEL_FAM6_ATOM_TREMONT_D, snr_uncore_init),
|
||||
{},
|
||||
};
|
||||
|
||||
|
|
|
@ -59,22 +59,22 @@ static bool test_intel(int idx, void *data)
|
|||
case INTEL_FAM6_IVYBRIDGE:
|
||||
case INTEL_FAM6_IVYBRIDGE_X:
|
||||
|
||||
case INTEL_FAM6_HASWELL_CORE:
|
||||
case INTEL_FAM6_HASWELL:
|
||||
case INTEL_FAM6_HASWELL_X:
|
||||
case INTEL_FAM6_HASWELL_ULT:
|
||||
case INTEL_FAM6_HASWELL_GT3E:
|
||||
case INTEL_FAM6_HASWELL_L:
|
||||
case INTEL_FAM6_HASWELL_G:
|
||||
|
||||
case INTEL_FAM6_BROADWELL_CORE:
|
||||
case INTEL_FAM6_BROADWELL_XEON_D:
|
||||
case INTEL_FAM6_BROADWELL_GT3E:
|
||||
case INTEL_FAM6_BROADWELL:
|
||||
case INTEL_FAM6_BROADWELL_D:
|
||||
case INTEL_FAM6_BROADWELL_G:
|
||||
case INTEL_FAM6_BROADWELL_X:
|
||||
|
||||
case INTEL_FAM6_ATOM_SILVERMONT:
|
||||
case INTEL_FAM6_ATOM_SILVERMONT_X:
|
||||
case INTEL_FAM6_ATOM_SILVERMONT_D:
|
||||
case INTEL_FAM6_ATOM_AIRMONT:
|
||||
|
||||
case INTEL_FAM6_ATOM_GOLDMONT:
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_X:
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_D:
|
||||
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
|
||||
|
||||
|
@ -84,12 +84,12 @@ static bool test_intel(int idx, void *data)
|
|||
return true;
|
||||
break;
|
||||
|
||||
case INTEL_FAM6_SKYLAKE_MOBILE:
|
||||
case INTEL_FAM6_SKYLAKE_DESKTOP:
|
||||
case INTEL_FAM6_SKYLAKE_L:
|
||||
case INTEL_FAM6_SKYLAKE:
|
||||
case INTEL_FAM6_SKYLAKE_X:
|
||||
case INTEL_FAM6_KABYLAKE_MOBILE:
|
||||
case INTEL_FAM6_KABYLAKE_DESKTOP:
|
||||
case INTEL_FAM6_ICELAKE_MOBILE:
|
||||
case INTEL_FAM6_KABYLAKE_L:
|
||||
case INTEL_FAM6_KABYLAKE:
|
||||
case INTEL_FAM6_ICELAKE_L:
|
||||
if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
|
||||
return true;
|
||||
break;
|
||||
|
|
|
@ -49,8 +49,7 @@ static inline unsigned long array_index_mask_nospec(unsigned long index,
|
|||
#define array_index_mask_nospec array_index_mask_nospec
|
||||
|
||||
/* Prevent speculative execution past this barrier. */
|
||||
#define barrier_nospec() alternative_2("", "mfence", X86_FEATURE_MFENCE_RDTSC, \
|
||||
"lfence", X86_FEATURE_LFENCE_RDTSC)
|
||||
#define barrier_nospec() alternative("", "lfence", X86_FEATURE_LFENCE_RDTSC)
|
||||
|
||||
#define dma_rmb() barrier()
|
||||
#define dma_wmb() barrier()
|
||||
|
|
|
@ -45,14 +45,13 @@
|
|||
* We do the locked ops that don't return the old value as
|
||||
* a mask operation on a byte.
|
||||
*/
|
||||
#define IS_IMMEDIATE(nr) (__builtin_constant_p(nr))
|
||||
#define CONST_MASK_ADDR(nr, addr) WBYTE_ADDR((void *)(addr) + ((nr)>>3))
|
||||
#define CONST_MASK(nr) (1 << ((nr) & 7))
|
||||
|
||||
static __always_inline void
|
||||
arch_set_bit(long nr, volatile unsigned long *addr)
|
||||
{
|
||||
if (IS_IMMEDIATE(nr)) {
|
||||
if (__builtin_constant_p(nr)) {
|
||||
asm volatile(LOCK_PREFIX "orb %1,%0"
|
||||
: CONST_MASK_ADDR(nr, addr)
|
||||
: "iq" ((u8)CONST_MASK(nr))
|
||||
|
@ -72,7 +71,7 @@ arch___set_bit(long nr, volatile unsigned long *addr)
|
|||
static __always_inline void
|
||||
arch_clear_bit(long nr, volatile unsigned long *addr)
|
||||
{
|
||||
if (IS_IMMEDIATE(nr)) {
|
||||
if (__builtin_constant_p(nr)) {
|
||||
asm volatile(LOCK_PREFIX "andb %1,%0"
|
||||
: CONST_MASK_ADDR(nr, addr)
|
||||
: "iq" ((u8)~CONST_MASK(nr)));
|
||||
|
@ -123,7 +122,7 @@ arch___change_bit(long nr, volatile unsigned long *addr)
|
|||
static __always_inline void
|
||||
arch_change_bit(long nr, volatile unsigned long *addr)
|
||||
{
|
||||
if (IS_IMMEDIATE(nr)) {
|
||||
if (__builtin_constant_p(nr)) {
|
||||
asm volatile(LOCK_PREFIX "xorb %1,%0"
|
||||
: CONST_MASK_ADDR(nr, addr)
|
||||
: "iq" ((u8)CONST_MASK(nr)));
|
||||
|
|
|
@ -61,6 +61,13 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
|
|||
#define CHECK_BIT_IN_MASK_WORD(maskname, word, bit) \
|
||||
(((bit)>>5)==(word) && (1UL<<((bit)&31) & maskname##word ))
|
||||
|
||||
/*
|
||||
* {REQUIRED,DISABLED}_MASK_CHECK below may seem duplicated with the
|
||||
* following BUILD_BUG_ON_ZERO() check but when NCAPINTS gets changed, all
|
||||
* header macros which use NCAPINTS need to be changed. The duplicated macro
|
||||
* use causes the compiler to issue errors for all headers so that all usage
|
||||
* sites can be corrected.
|
||||
*/
|
||||
#define REQUIRED_MASK_BIT_SET(feature_bit) \
|
||||
( CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 0, feature_bit) || \
|
||||
CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 1, feature_bit) || \
|
||||
|
|
|
@ -96,7 +96,6 @@
|
|||
#define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in IA32 userspace */
|
||||
#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */
|
||||
#define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */
|
||||
#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" MFENCE synchronizes RDTSC */
|
||||
#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */
|
||||
#define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */
|
||||
#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */
|
||||
|
@ -355,6 +354,7 @@
|
|||
/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
|
||||
#define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */
|
||||
#define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
|
||||
#define X86_FEATURE_AVX512_VP2INTERSECT (18*32+ 8) /* AVX-512 Intersect for D/Q */
|
||||
#define X86_FEATURE_MD_CLEAR (18*32+10) /* VERW clears CPU buffers */
|
||||
#define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */
|
||||
#define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */
|
||||
|
|
|
@ -5,9 +5,6 @@
|
|||
/*
|
||||
* "Big Core" Processors (Branded as Core, Xeon, etc...)
|
||||
*
|
||||
* The "_X" parts are generally the EP and EX Xeons, or the
|
||||
* "Extreme" ones, like Broadwell-E, or Atom microserver.
|
||||
*
|
||||
* While adding a new CPUID for a new microarchitecture, add a new
|
||||
* group to keep logically sorted out in chronological order. Within
|
||||
* that group keep the CPUID for the variants sorted by model number.
|
||||
|
@ -21,9 +18,19 @@
|
|||
* MICROARCH Is the code name for the micro-architecture for this core.
|
||||
* N.B. Not the platform name.
|
||||
* OPTDIFF If needed, a short string to differentiate by market segment.
|
||||
* Exact strings here will vary over time. _DESKTOP, _MOBILE, and
|
||||
* _X (short for Xeon server) should be used when they are
|
||||
* appropriate.
|
||||
*
|
||||
* Common OPTDIFFs:
|
||||
*
|
||||
* - regular client parts
|
||||
* _L - regular mobile parts
|
||||
* _G - parts with extra graphics on
|
||||
* _X - regular server parts
|
||||
* _D - micro server parts
|
||||
*
|
||||
* Historical OPTDIFFs:
|
||||
*
|
||||
* _EP - 2 socket server parts
|
||||
* _EX - 4+ socket server parts
|
||||
*
|
||||
* The #define line may optionally include a comment including platform names.
|
||||
*/
|
||||
|
@ -49,30 +56,33 @@
|
|||
#define INTEL_FAM6_IVYBRIDGE 0x3A
|
||||
#define INTEL_FAM6_IVYBRIDGE_X 0x3E
|
||||
|
||||
#define INTEL_FAM6_HASWELL_CORE 0x3C
|
||||
#define INTEL_FAM6_HASWELL 0x3C
|
||||
#define INTEL_FAM6_HASWELL_X 0x3F
|
||||
#define INTEL_FAM6_HASWELL_ULT 0x45
|
||||
#define INTEL_FAM6_HASWELL_GT3E 0x46
|
||||
#define INTEL_FAM6_HASWELL_L 0x45
|
||||
#define INTEL_FAM6_HASWELL_G 0x46
|
||||
|
||||
#define INTEL_FAM6_BROADWELL_CORE 0x3D
|
||||
#define INTEL_FAM6_BROADWELL_GT3E 0x47
|
||||
#define INTEL_FAM6_BROADWELL 0x3D
|
||||
#define INTEL_FAM6_BROADWELL_G 0x47
|
||||
#define INTEL_FAM6_BROADWELL_X 0x4F
|
||||
#define INTEL_FAM6_BROADWELL_XEON_D 0x56
|
||||
#define INTEL_FAM6_BROADWELL_D 0x56
|
||||
|
||||
#define INTEL_FAM6_SKYLAKE_MOBILE 0x4E
|
||||
#define INTEL_FAM6_SKYLAKE_DESKTOP 0x5E
|
||||
#define INTEL_FAM6_SKYLAKE_L 0x4E
|
||||
#define INTEL_FAM6_SKYLAKE 0x5E
|
||||
#define INTEL_FAM6_SKYLAKE_X 0x55
|
||||
#define INTEL_FAM6_KABYLAKE_MOBILE 0x8E
|
||||
#define INTEL_FAM6_KABYLAKE_DESKTOP 0x9E
|
||||
#define INTEL_FAM6_KABYLAKE_L 0x8E
|
||||
#define INTEL_FAM6_KABYLAKE 0x9E
|
||||
|
||||
#define INTEL_FAM6_CANNONLAKE_MOBILE 0x66
|
||||
#define INTEL_FAM6_CANNONLAKE_L 0x66
|
||||
|
||||
#define INTEL_FAM6_ICELAKE_X 0x6A
|
||||
#define INTEL_FAM6_ICELAKE_XEON_D 0x6C
|
||||
#define INTEL_FAM6_ICELAKE_DESKTOP 0x7D
|
||||
#define INTEL_FAM6_ICELAKE_MOBILE 0x7E
|
||||
#define INTEL_FAM6_ICELAKE_D 0x6C
|
||||
#define INTEL_FAM6_ICELAKE 0x7D
|
||||
#define INTEL_FAM6_ICELAKE_L 0x7E
|
||||
#define INTEL_FAM6_ICELAKE_NNPI 0x9D
|
||||
|
||||
#define INTEL_FAM6_TIGERLAKE_L 0x8C
|
||||
#define INTEL_FAM6_TIGERLAKE 0x8D
|
||||
|
||||
/* "Small Core" Processors (Atom) */
|
||||
|
||||
#define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */
|
||||
|
@ -83,17 +93,21 @@
|
|||
#define INTEL_FAM6_ATOM_SALTWELL_TABLET 0x35 /* Cloverview */
|
||||
|
||||
#define INTEL_FAM6_ATOM_SILVERMONT 0x37 /* Bay Trail, Valleyview */
|
||||
#define INTEL_FAM6_ATOM_SILVERMONT_X 0x4D /* Avaton, Rangely */
|
||||
#define INTEL_FAM6_ATOM_SILVERMONT_D 0x4D /* Avaton, Rangely */
|
||||
#define INTEL_FAM6_ATOM_SILVERMONT_MID 0x4A /* Merriefield */
|
||||
|
||||
#define INTEL_FAM6_ATOM_AIRMONT 0x4C /* Cherry Trail, Braswell */
|
||||
#define INTEL_FAM6_ATOM_AIRMONT_MID 0x5A /* Moorefield */
|
||||
#define INTEL_FAM6_ATOM_AIRMONT_NP 0x75 /* Lightning Mountain */
|
||||
|
||||
#define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */
|
||||
#define INTEL_FAM6_ATOM_GOLDMONT_X 0x5F /* Denverton */
|
||||
#define INTEL_FAM6_ATOM_GOLDMONT_D 0x5F /* Denverton */
|
||||
|
||||
/* Note: the micro-architecture is "Goldmont Plus" */
|
||||
#define INTEL_FAM6_ATOM_GOLDMONT_PLUS 0x7A /* Gemini Lake */
|
||||
|
||||
#define INTEL_FAM6_ATOM_TREMONT_X 0x86 /* Jacobsville */
|
||||
#define INTEL_FAM6_ATOM_TREMONT_D 0x86 /* Jacobsville */
|
||||
#define INTEL_FAM6_ATOM_TREMONT 0x96 /* Elkhart Lake */
|
||||
|
||||
/* Xeon Phi */
|
||||
|
||||
|
|
|
@ -379,14 +379,18 @@
|
|||
#define MSR_RELOAD_PMC0 0x000014c1
|
||||
#define MSR_RELOAD_FIXED_CTR0 0x00001309
|
||||
|
||||
/* AMD64 MSRs. Not complete. See the architecture manual for a more
|
||||
complete list. */
|
||||
|
||||
/*
|
||||
* AMD64 MSRs. Not complete. See the architecture manual for a more
|
||||
* complete list.
|
||||
*/
|
||||
#define MSR_AMD64_PATCH_LEVEL 0x0000008b
|
||||
#define MSR_AMD64_TSC_RATIO 0xc0000104
|
||||
#define MSR_AMD64_NB_CFG 0xc001001f
|
||||
#define MSR_AMD64_CPUID_FN_1 0xc0011004
|
||||
#define MSR_AMD64_PATCH_LOADER 0xc0010020
|
||||
#define MSR_AMD_PERF_CTL 0xc0010062
|
||||
#define MSR_AMD_PERF_STATUS 0xc0010063
|
||||
#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
|
||||
#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
|
||||
#define MSR_AMD64_OSVW_STATUS 0xc0010141
|
||||
#define MSR_AMD64_LS_CFG 0xc0011020
|
||||
|
@ -565,9 +569,6 @@
|
|||
#define MSR_IA32_PERF_STATUS 0x00000198
|
||||
#define MSR_IA32_PERF_CTL 0x00000199
|
||||
#define INTEL_PERF_CTL_MASK 0xffff
|
||||
#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
|
||||
#define MSR_AMD_PERF_STATUS 0xc0010063
|
||||
#define MSR_AMD_PERF_CTL 0xc0010062
|
||||
|
||||
#define MSR_IA32_MPERF 0x000000e7
|
||||
#define MSR_IA32_APERF 0x000000e8
|
||||
|
|
|
@ -233,8 +233,7 @@ static __always_inline unsigned long long rdtsc_ordered(void)
|
|||
* Thus, use the preferred barrier on the respective CPU, aiming for
|
||||
* RDTSCP as the default.
|
||||
*/
|
||||
asm volatile(ALTERNATIVE_3("rdtsc",
|
||||
"mfence; rdtsc", X86_FEATURE_MFENCE_RDTSC,
|
||||
asm volatile(ALTERNATIVE_2("rdtsc",
|
||||
"lfence; rdtsc", X86_FEATURE_LFENCE_RDTSC,
|
||||
"rdtscp", X86_FEATURE_RDTSCP)
|
||||
: EAX_EDX_RET(val, low, high)
|
||||
|
|
|
@ -20,7 +20,6 @@ struct real_mode_header {
|
|||
u32 ro_end;
|
||||
/* SMP trampoline */
|
||||
u32 trampoline_start;
|
||||
u32 trampoline_status;
|
||||
u32 trampoline_header;
|
||||
#ifdef CONFIG_X86_64
|
||||
u32 trampoline_pgd;
|
||||
|
|
|
@ -45,8 +45,8 @@ extern void text_poke_early(void *addr, const void *opcode, size_t len);
|
|||
* no thread can be preempted in the instructions being modified (no iret to an
|
||||
* invalid instruction possible) or if the instructions are changed from a
|
||||
* consistent state to another consistent state atomically.
|
||||
* On the local CPU you need to be protected again NMI or MCE handlers seeing an
|
||||
* inconsistent instruction while you patch.
|
||||
* On the local CPU you need to be protected against NMI or MCE handlers seeing
|
||||
* an inconsistent instruction while you patch.
|
||||
*/
|
||||
extern void *text_poke(void *addr, const void *opcode, size_t len);
|
||||
extern void *text_poke_kgdb(void *addr, const void *opcode, size_t len);
|
||||
|
|
|
@ -713,7 +713,7 @@ void __init alternative_instructions(void)
|
|||
* Don't stop machine check exceptions while patching.
|
||||
* MCEs only happen when something got corrupted and in this
|
||||
* case we must do something about the corruption.
|
||||
* Ignoring it is worse than a unlikely patching race.
|
||||
* Ignoring it is worse than an unlikely patching race.
|
||||
* Also machine checks tend to be broadcast and if one CPU
|
||||
* goes into machine check the others follow quickly, so we don't
|
||||
* expect a machine check to cause undue problems during to code
|
||||
|
@ -753,8 +753,8 @@ void __init alternative_instructions(void)
|
|||
* When you use this code to patch more than one byte of an instruction
|
||||
* you need to make sure that other CPUs cannot execute this code in parallel.
|
||||
* Also no thread must be currently preempted in the middle of these
|
||||
* instructions. And on the local CPU you need to be protected again NMI or MCE
|
||||
* handlers seeing an inconsistent instruction while you patch.
|
||||
* instructions. And on the local CPU you need to be protected against NMI or
|
||||
* MCE handlers seeing an inconsistent instruction while you patch.
|
||||
*/
|
||||
void __init_or_module text_poke_early(void *addr, const void *opcode,
|
||||
size_t len)
|
||||
|
|
|
@ -590,21 +590,21 @@ static u32 skx_deadline_rev(void)
|
|||
static const struct x86_cpu_id deadline_match[] = {
|
||||
DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X, hsx_deadline_rev),
|
||||
DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X, 0x0b000020),
|
||||
DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D, bdx_deadline_rev),
|
||||
DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_D, bdx_deadline_rev),
|
||||
DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_SKYLAKE_X, skx_deadline_rev),
|
||||
|
||||
DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE, 0x22),
|
||||
DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT, 0x20),
|
||||
DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E, 0x17),
|
||||
DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL, 0x22),
|
||||
DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_L, 0x20),
|
||||
DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_G, 0x17),
|
||||
|
||||
DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE, 0x25),
|
||||
DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E, 0x17),
|
||||
DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL, 0x25),
|
||||
DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_G, 0x17),
|
||||
|
||||
DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE, 0xb2),
|
||||
DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP, 0xb2),
|
||||
DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_L, 0xb2),
|
||||
DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE, 0xb2),
|
||||
|
||||
DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE, 0x52),
|
||||
DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52),
|
||||
DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_L, 0x52),
|
||||
DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE, 0x52),
|
||||
|
||||
{},
|
||||
};
|
||||
|
|
|
@ -950,12 +950,8 @@ static void init_amd(struct cpuinfo_x86 *c)
|
|||
init_amd_cacheinfo(c);
|
||||
|
||||
if (cpu_has(c, X86_FEATURE_XMM2)) {
|
||||
unsigned long long val;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* A serializing LFENCE has less overhead than MFENCE, so
|
||||
* use it for execution serialization. On families which
|
||||
* Use LFENCE for execution serialization. On families which
|
||||
* don't have that MSR, LFENCE is already serializing.
|
||||
* msr_set_bit() uses the safe accessors, too, even if the MSR
|
||||
* is not present.
|
||||
|
@ -963,19 +959,8 @@ static void init_amd(struct cpuinfo_x86 *c)
|
|||
msr_set_bit(MSR_F10H_DECFG,
|
||||
MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
|
||||
|
||||
/*
|
||||
* Verify that the MSR write was successful (could be running
|
||||
* under a hypervisor) and only then assume that LFENCE is
|
||||
* serializing.
|
||||
*/
|
||||
ret = rdmsrl_safe(MSR_F10H_DECFG, &val);
|
||||
if (!ret && (val & MSR_F10H_DECFG_LFENCE_SERIALIZE)) {
|
||||
/* A serializing LFENCE stops RDTSC speculation */
|
||||
set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
|
||||
} else {
|
||||
/* MFENCE stops RDTSC speculation */
|
||||
set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
@ -1184,15 +1184,15 @@ static void override_cache_bits(struct cpuinfo_x86 *c)
|
|||
case INTEL_FAM6_WESTMERE:
|
||||
case INTEL_FAM6_SANDYBRIDGE:
|
||||
case INTEL_FAM6_IVYBRIDGE:
|
||||
case INTEL_FAM6_HASWELL_CORE:
|
||||
case INTEL_FAM6_HASWELL_ULT:
|
||||
case INTEL_FAM6_HASWELL_GT3E:
|
||||
case INTEL_FAM6_BROADWELL_CORE:
|
||||
case INTEL_FAM6_BROADWELL_GT3E:
|
||||
case INTEL_FAM6_SKYLAKE_MOBILE:
|
||||
case INTEL_FAM6_SKYLAKE_DESKTOP:
|
||||
case INTEL_FAM6_KABYLAKE_MOBILE:
|
||||
case INTEL_FAM6_KABYLAKE_DESKTOP:
|
||||
case INTEL_FAM6_HASWELL:
|
||||
case INTEL_FAM6_HASWELL_L:
|
||||
case INTEL_FAM6_HASWELL_G:
|
||||
case INTEL_FAM6_BROADWELL:
|
||||
case INTEL_FAM6_BROADWELL_G:
|
||||
case INTEL_FAM6_SKYLAKE_L:
|
||||
case INTEL_FAM6_SKYLAKE:
|
||||
case INTEL_FAM6_KABYLAKE_L:
|
||||
case INTEL_FAM6_KABYLAKE:
|
||||
if (c->x86_cache_bits < 44)
|
||||
c->x86_cache_bits = 44;
|
||||
break;
|
||||
|
|
|
@ -1050,7 +1050,7 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
|
|||
VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION),
|
||||
|
||||
VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
|
||||
VULNWL_INTEL(ATOM_SILVERMONT_X, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
|
||||
VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
|
||||
VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
|
||||
VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
|
||||
VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
|
||||
|
@ -1059,9 +1059,10 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
|
|||
VULNWL_INTEL(CORE_YONAH, NO_SSB),
|
||||
|
||||
VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
|
||||
VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS),
|
||||
|
||||
VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS),
|
||||
VULNWL_INTEL(ATOM_GOLDMONT_X, NO_MDS | NO_L1TF | NO_SWAPGS),
|
||||
VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS),
|
||||
VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS),
|
||||
|
||||
/*
|
||||
|
|
|
@ -64,6 +64,7 @@ static const struct cpuid_dep cpuid_deps[] = {
|
|||
{ X86_FEATURE_AVX512_4VNNIW, X86_FEATURE_AVX512F },
|
||||
{ X86_FEATURE_AVX512_4FMAPS, X86_FEATURE_AVX512F },
|
||||
{ X86_FEATURE_AVX512_VPOPCNTDQ, X86_FEATURE_AVX512F },
|
||||
{ X86_FEATURE_AVX512_VP2INTERSECT, X86_FEATURE_AVX512VL },
|
||||
{ X86_FEATURE_CQM_OCCUP_LLC, X86_FEATURE_CQM_LLC },
|
||||
{ X86_FEATURE_CQM_MBM_TOTAL, X86_FEATURE_CQM_LLC },
|
||||
{ X86_FEATURE_CQM_MBM_LOCAL, X86_FEATURE_CQM_LLC },
|
||||
|
|
|
@ -330,12 +330,8 @@ static void init_hygon(struct cpuinfo_x86 *c)
|
|||
init_hygon_cacheinfo(c);
|
||||
|
||||
if (cpu_has(c, X86_FEATURE_XMM2)) {
|
||||
unsigned long long val;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* A serializing LFENCE has less overhead than MFENCE, so
|
||||
* use it for execution serialization. On families which
|
||||
* Use LFENCE for execution serialization. On families which
|
||||
* don't have that MSR, LFENCE is already serializing.
|
||||
* msr_set_bit() uses the safe accessors, too, even if the MSR
|
||||
* is not present.
|
||||
|
@ -343,19 +339,8 @@ static void init_hygon(struct cpuinfo_x86 *c)
|
|||
msr_set_bit(MSR_F10H_DECFG,
|
||||
MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
|
||||
|
||||
/*
|
||||
* Verify that the MSR write was successful (could be running
|
||||
* under a hypervisor) and only then assume that LFENCE is
|
||||
* serializing.
|
||||
*/
|
||||
ret = rdmsrl_safe(MSR_F10H_DECFG, &val);
|
||||
if (!ret && (val & MSR_F10H_DECFG_LFENCE_SERIALIZE)) {
|
||||
/* A serializing LFENCE stops RDTSC speculation */
|
||||
set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
|
||||
} else {
|
||||
/* MFENCE stops RDTSC speculation */
|
||||
set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
@ -142,21 +142,21 @@ struct sku_microcode {
|
|||
u32 microcode;
|
||||
};
|
||||
static const struct sku_microcode spectre_bad_microcodes[] = {
|
||||
{ INTEL_FAM6_KABYLAKE_DESKTOP, 0x0B, 0x80 },
|
||||
{ INTEL_FAM6_KABYLAKE_DESKTOP, 0x0A, 0x80 },
|
||||
{ INTEL_FAM6_KABYLAKE_DESKTOP, 0x09, 0x80 },
|
||||
{ INTEL_FAM6_KABYLAKE_MOBILE, 0x0A, 0x80 },
|
||||
{ INTEL_FAM6_KABYLAKE_MOBILE, 0x09, 0x80 },
|
||||
{ INTEL_FAM6_KABYLAKE, 0x0B, 0x80 },
|
||||
{ INTEL_FAM6_KABYLAKE, 0x0A, 0x80 },
|
||||
{ INTEL_FAM6_KABYLAKE, 0x09, 0x80 },
|
||||
{ INTEL_FAM6_KABYLAKE_L, 0x0A, 0x80 },
|
||||
{ INTEL_FAM6_KABYLAKE_L, 0x09, 0x80 },
|
||||
{ INTEL_FAM6_SKYLAKE_X, 0x03, 0x0100013e },
|
||||
{ INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003c },
|
||||
{ INTEL_FAM6_BROADWELL_CORE, 0x04, 0x28 },
|
||||
{ INTEL_FAM6_BROADWELL_GT3E, 0x01, 0x1b },
|
||||
{ INTEL_FAM6_BROADWELL_XEON_D, 0x02, 0x14 },
|
||||
{ INTEL_FAM6_BROADWELL_XEON_D, 0x03, 0x07000011 },
|
||||
{ INTEL_FAM6_BROADWELL, 0x04, 0x28 },
|
||||
{ INTEL_FAM6_BROADWELL_G, 0x01, 0x1b },
|
||||
{ INTEL_FAM6_BROADWELL_D, 0x02, 0x14 },
|
||||
{ INTEL_FAM6_BROADWELL_D, 0x03, 0x07000011 },
|
||||
{ INTEL_FAM6_BROADWELL_X, 0x01, 0x0b000025 },
|
||||
{ INTEL_FAM6_HASWELL_ULT, 0x01, 0x21 },
|
||||
{ INTEL_FAM6_HASWELL_GT3E, 0x01, 0x18 },
|
||||
{ INTEL_FAM6_HASWELL_CORE, 0x03, 0x23 },
|
||||
{ INTEL_FAM6_HASWELL_L, 0x01, 0x21 },
|
||||
{ INTEL_FAM6_HASWELL_G, 0x01, 0x18 },
|
||||
{ INTEL_FAM6_HASWELL, 0x03, 0x23 },
|
||||
{ INTEL_FAM6_HASWELL_X, 0x02, 0x3b },
|
||||
{ INTEL_FAM6_HASWELL_X, 0x04, 0x10 },
|
||||
{ INTEL_FAM6_IVYBRIDGE_X, 0x04, 0x42a },
|
||||
|
@ -265,9 +265,10 @@ static void early_init_intel(struct cpuinfo_x86 *c)
|
|||
/* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
|
||||
if (c->x86 == 6) {
|
||||
switch (c->x86_model) {
|
||||
case 0x27: /* Penwell */
|
||||
case 0x35: /* Cloverview */
|
||||
case 0x4a: /* Merrifield */
|
||||
case INTEL_FAM6_ATOM_SALTWELL_MID:
|
||||
case INTEL_FAM6_ATOM_SALTWELL_TABLET:
|
||||
case INTEL_FAM6_ATOM_SILVERMONT_MID:
|
||||
case INTEL_FAM6_ATOM_AIRMONT_NP:
|
||||
set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
|
||||
break;
|
||||
default:
|
||||
|
|
|
@ -479,7 +479,7 @@ static void intel_ppin_init(struct cpuinfo_x86 *c)
|
|||
switch (c->x86_model) {
|
||||
case INTEL_FAM6_IVYBRIDGE_X:
|
||||
case INTEL_FAM6_HASWELL_X:
|
||||
case INTEL_FAM6_BROADWELL_XEON_D:
|
||||
case INTEL_FAM6_BROADWELL_D:
|
||||
case INTEL_FAM6_BROADWELL_X:
|
||||
case INTEL_FAM6_SKYLAKE_X:
|
||||
case INTEL_FAM6_XEON_PHI_KNL:
|
||||
|
|
|
@ -225,8 +225,6 @@ static int elf_header_exclude_ranges(struct crash_mem *cmem)
|
|||
if (crashk_low_res.end) {
|
||||
ret = crash_exclude_mem_range(cmem, crashk_low_res.start,
|
||||
crashk_low_res.end);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
|
|
@ -403,7 +403,7 @@ int arch_prepare_optimized_kprobe(struct optimized_kprobe *op,
|
|||
(u8 *)op->kp.addr + op->optinsn.size);
|
||||
len += RELATIVEJUMP_SIZE;
|
||||
|
||||
/* We have to use text_poke for instuction buffer because it is RO */
|
||||
/* We have to use text_poke() for instruction buffer because it is RO */
|
||||
text_poke(slot, buf, len);
|
||||
ret = 0;
|
||||
out:
|
||||
|
|
|
@ -90,8 +90,6 @@ static void ich_force_hpet_resume(void)
|
|||
BUG();
|
||||
else
|
||||
printk(KERN_DEBUG "Force enabled HPET at resume\n");
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static void ich_force_enable_hpet(struct pci_dev *dev)
|
||||
|
@ -448,7 +446,6 @@ static void nvidia_force_enable_hpet(struct pci_dev *dev)
|
|||
dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
|
||||
force_hpet_address);
|
||||
cached_dev = dev;
|
||||
return;
|
||||
}
|
||||
|
||||
/* ISA Bridges */
|
||||
|
@ -513,7 +510,6 @@ static void e6xx_force_enable_hpet(struct pci_dev *dev)
|
|||
force_hpet_resume_type = NONE_FORCE_HPET_RESUME;
|
||||
dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
|
||||
"0x%lx\n", force_hpet_address);
|
||||
return;
|
||||
}
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E6XX_CU,
|
||||
e6xx_force_enable_hpet);
|
||||
|
|
|
@ -1023,8 +1023,6 @@ int common_cpu_up(unsigned int cpu, struct task_struct *idle)
|
|||
static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
|
||||
int *cpu0_nmi_registered)
|
||||
{
|
||||
volatile u32 *trampoline_status =
|
||||
(volatile u32 *) __va(real_mode_header->trampoline_status);
|
||||
/* start_ip had better be page-aligned! */
|
||||
unsigned long start_ip = real_mode_header->trampoline_start;
|
||||
|
||||
|
@ -1116,9 +1114,6 @@ static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
|
|||
}
|
||||
}
|
||||
|
||||
/* mark "stuck" area as not stuck */
|
||||
*trampoline_status = 0;
|
||||
|
||||
if (x86_platform.legacy.warm_reset) {
|
||||
/*
|
||||
* Cleanup possible dangling ends...
|
||||
|
|
|
@ -638,7 +638,7 @@ unsigned long native_calibrate_tsc(void)
|
|||
* clock.
|
||||
*/
|
||||
if (crystal_khz == 0 &&
|
||||
boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT_X)
|
||||
boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT_D)
|
||||
crystal_khz = 25000;
|
||||
|
||||
/*
|
||||
|
|
|
@ -58,6 +58,10 @@ static const struct freq_desc freq_desc_ann = {
|
|||
1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 }
|
||||
};
|
||||
|
||||
static const struct freq_desc freq_desc_lgm = {
|
||||
1, { 78000, 78000, 78000, 78000, 78000, 78000, 78000, 78000 }
|
||||
};
|
||||
|
||||
static const struct x86_cpu_id tsc_msr_cpu_ids[] = {
|
||||
INTEL_CPU_FAM6(ATOM_SALTWELL_MID, freq_desc_pnw),
|
||||
INTEL_CPU_FAM6(ATOM_SALTWELL_TABLET, freq_desc_clv),
|
||||
|
@ -65,6 +69,7 @@ static const struct x86_cpu_id tsc_msr_cpu_ids[] = {
|
|||
INTEL_CPU_FAM6(ATOM_SILVERMONT_MID, freq_desc_tng),
|
||||
INTEL_CPU_FAM6(ATOM_AIRMONT, freq_desc_cht),
|
||||
INTEL_CPU_FAM6(ATOM_AIRMONT_MID, freq_desc_ann),
|
||||
INTEL_CPU_FAM6(ATOM_AIRMONT_NP, freq_desc_lgm),
|
||||
{}
|
||||
};
|
||||
|
||||
|
|
|
@ -19,7 +19,6 @@ GLOBAL(real_mode_header)
|
|||
.long pa_ro_end
|
||||
/* SMP trampoline */
|
||||
.long pa_trampoline_start
|
||||
.long pa_trampoline_status
|
||||
.long pa_trampoline_header
|
||||
#ifdef CONFIG_X86_64
|
||||
.long pa_trampoline_pgd;
|
||||
|
|
|
@ -41,9 +41,6 @@ ENTRY(trampoline_start)
|
|||
|
||||
movl tr_start, %eax # where we need to go
|
||||
|
||||
movl $0xA5A5A5A5, trampoline_status
|
||||
# write marker for master knows we're running
|
||||
|
||||
/*
|
||||
* GDT tables in non default location kernel can be beyond 16MB and
|
||||
* lgdt will not be able to load the address as in real mode default
|
||||
|
|
|
@ -49,9 +49,6 @@ ENTRY(trampoline_start)
|
|||
mov %ax, %es
|
||||
mov %ax, %ss
|
||||
|
||||
movl $0xA5A5A5A5, trampoline_status
|
||||
# write marker for master knows we're running
|
||||
|
||||
# Setup stack
|
||||
movl $rm_stack_end, %esp
|
||||
|
||||
|
|
|
@ -2,7 +2,3 @@
|
|||
.section ".rodata","a"
|
||||
.balign 16
|
||||
tr_idt: .fill 1, 6, 0
|
||||
|
||||
.bss
|
||||
.balign 4
|
||||
GLOBAL(trampoline_status) .space 4
|
||||
|
|
|
@ -69,11 +69,11 @@ static const struct always_present_id always_present_ids[] = {
|
|||
* after _SB.PCI0.GFX0.LCD.LCD1._ON gets called has passed
|
||||
* *and* _STA has been called at least 3 times since.
|
||||
*/
|
||||
ENTRY("SYNA7500", "1", ICPU(INTEL_FAM6_HASWELL_ULT), {
|
||||
ENTRY("SYNA7500", "1", ICPU(INTEL_FAM6_HASWELL_L), {
|
||||
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
|
||||
DMI_MATCH(DMI_PRODUCT_NAME, "Venue 11 Pro 7130"),
|
||||
}),
|
||||
ENTRY("SYNA7500", "1", ICPU(INTEL_FAM6_HASWELL_ULT), {
|
||||
ENTRY("SYNA7500", "1", ICPU(INTEL_FAM6_HASWELL_L), {
|
||||
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
|
||||
DMI_MATCH(DMI_PRODUCT_NAME, "Venue 11 Pro 7139"),
|
||||
}),
|
||||
|
|
|
@ -1871,18 +1871,18 @@ static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
|
|||
ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_funcs),
|
||||
ICPU(INTEL_FAM6_ATOM_SILVERMONT, silvermont_funcs),
|
||||
ICPU(INTEL_FAM6_IVYBRIDGE, core_funcs),
|
||||
ICPU(INTEL_FAM6_HASWELL_CORE, core_funcs),
|
||||
ICPU(INTEL_FAM6_BROADWELL_CORE, core_funcs),
|
||||
ICPU(INTEL_FAM6_HASWELL, core_funcs),
|
||||
ICPU(INTEL_FAM6_BROADWELL, core_funcs),
|
||||
ICPU(INTEL_FAM6_IVYBRIDGE_X, core_funcs),
|
||||
ICPU(INTEL_FAM6_HASWELL_X, core_funcs),
|
||||
ICPU(INTEL_FAM6_HASWELL_ULT, core_funcs),
|
||||
ICPU(INTEL_FAM6_HASWELL_GT3E, core_funcs),
|
||||
ICPU(INTEL_FAM6_BROADWELL_GT3E, core_funcs),
|
||||
ICPU(INTEL_FAM6_HASWELL_L, core_funcs),
|
||||
ICPU(INTEL_FAM6_HASWELL_G, core_funcs),
|
||||
ICPU(INTEL_FAM6_BROADWELL_G, core_funcs),
|
||||
ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_funcs),
|
||||
ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_funcs),
|
||||
ICPU(INTEL_FAM6_SKYLAKE_L, core_funcs),
|
||||
ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
|
||||
ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs),
|
||||
ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
|
||||
ICPU(INTEL_FAM6_SKYLAKE, core_funcs),
|
||||
ICPU(INTEL_FAM6_BROADWELL_D, core_funcs),
|
||||
ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_funcs),
|
||||
ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_funcs),
|
||||
ICPU(INTEL_FAM6_ATOM_GOLDMONT, core_funcs),
|
||||
|
@ -1893,20 +1893,20 @@ static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
|
|||
MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
|
||||
|
||||
static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
|
||||
ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
|
||||
ICPU(INTEL_FAM6_BROADWELL_D, core_funcs),
|
||||
ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
|
||||
ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
|
||||
{}
|
||||
};
|
||||
|
||||
static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
|
||||
ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_funcs),
|
||||
ICPU(INTEL_FAM6_KABYLAKE, core_funcs),
|
||||
{}
|
||||
};
|
||||
|
||||
static const struct x86_cpu_id intel_pstate_hwp_boost_ids[] = {
|
||||
ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
|
||||
ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs),
|
||||
ICPU(INTEL_FAM6_SKYLAKE, core_funcs),
|
||||
{}
|
||||
};
|
||||
|
||||
|
@ -2624,7 +2624,7 @@ static inline void intel_pstate_request_control_from_smm(void) {}
|
|||
|
||||
static const struct x86_cpu_id hwp_support_ids[] __initconst = {
|
||||
ICPU_HWP(INTEL_FAM6_BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL),
|
||||
ICPU_HWP(INTEL_FAM6_BROADWELL_XEON_D, INTEL_PSTATE_HWP_BROADWELL),
|
||||
ICPU_HWP(INTEL_FAM6_BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL),
|
||||
ICPU_HWP(X86_MODEL_ANY, 0),
|
||||
{}
|
||||
};
|
||||
|
|
|
@ -123,9 +123,9 @@ static int i10nm_get_all_munits(void)
|
|||
}
|
||||
|
||||
static const struct x86_cpu_id i10nm_cpuids[] = {
|
||||
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_TREMONT_X, 0, 0 },
|
||||
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_TREMONT_D, 0, 0 },
|
||||
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ICELAKE_X, 0, 0 },
|
||||
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ICELAKE_XEON_D, 0, 0 },
|
||||
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ICELAKE_D, 0, 0 },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(x86cpu, i10nm_cpuids);
|
||||
|
|
|
@ -1538,7 +1538,7 @@ static struct dunit_ops dnv_ops = {
|
|||
|
||||
static const struct x86_cpu_id pnd2_cpuids[] = {
|
||||
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT, 0, (kernel_ulong_t)&apl_ops },
|
||||
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT_X, 0, (kernel_ulong_t)&dnv_ops },
|
||||
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT_D, 0, (kernel_ulong_t)&dnv_ops },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(x86cpu, pnd2_cpuids);
|
||||
|
|
|
@ -3429,7 +3429,7 @@ static const struct x86_cpu_id sbridge_cpuids[] = {
|
|||
INTEL_CPU_FAM6(IVYBRIDGE_X, pci_dev_descr_ibridge_table),
|
||||
INTEL_CPU_FAM6(HASWELL_X, pci_dev_descr_haswell_table),
|
||||
INTEL_CPU_FAM6(BROADWELL_X, pci_dev_descr_broadwell_table),
|
||||
INTEL_CPU_FAM6(BROADWELL_XEON_D, pci_dev_descr_broadwell_table),
|
||||
INTEL_CPU_FAM6(BROADWELL_D, pci_dev_descr_broadwell_table),
|
||||
INTEL_CPU_FAM6(XEON_PHI_KNL, pci_dev_descr_knl_table),
|
||||
INTEL_CPU_FAM6(XEON_PHI_KNM, pci_dev_descr_knl_table),
|
||||
{ }
|
||||
|
|
|
@ -1072,26 +1072,26 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = {
|
|||
INTEL_CPU_FAM6(ATOM_AIRMONT, idle_cpu_cht),
|
||||
INTEL_CPU_FAM6(IVYBRIDGE, idle_cpu_ivb),
|
||||
INTEL_CPU_FAM6(IVYBRIDGE_X, idle_cpu_ivt),
|
||||
INTEL_CPU_FAM6(HASWELL_CORE, idle_cpu_hsw),
|
||||
INTEL_CPU_FAM6(HASWELL, idle_cpu_hsw),
|
||||
INTEL_CPU_FAM6(HASWELL_X, idle_cpu_hsw),
|
||||
INTEL_CPU_FAM6(HASWELL_ULT, idle_cpu_hsw),
|
||||
INTEL_CPU_FAM6(HASWELL_GT3E, idle_cpu_hsw),
|
||||
INTEL_CPU_FAM6(ATOM_SILVERMONT_X, idle_cpu_avn),
|
||||
INTEL_CPU_FAM6(BROADWELL_CORE, idle_cpu_bdw),
|
||||
INTEL_CPU_FAM6(BROADWELL_GT3E, idle_cpu_bdw),
|
||||
INTEL_CPU_FAM6(HASWELL_L, idle_cpu_hsw),
|
||||
INTEL_CPU_FAM6(HASWELL_G, idle_cpu_hsw),
|
||||
INTEL_CPU_FAM6(ATOM_SILVERMONT_D, idle_cpu_avn),
|
||||
INTEL_CPU_FAM6(BROADWELL, idle_cpu_bdw),
|
||||
INTEL_CPU_FAM6(BROADWELL_G, idle_cpu_bdw),
|
||||
INTEL_CPU_FAM6(BROADWELL_X, idle_cpu_bdw),
|
||||
INTEL_CPU_FAM6(BROADWELL_XEON_D, idle_cpu_bdw),
|
||||
INTEL_CPU_FAM6(SKYLAKE_MOBILE, idle_cpu_skl),
|
||||
INTEL_CPU_FAM6(SKYLAKE_DESKTOP, idle_cpu_skl),
|
||||
INTEL_CPU_FAM6(KABYLAKE_MOBILE, idle_cpu_skl),
|
||||
INTEL_CPU_FAM6(KABYLAKE_DESKTOP, idle_cpu_skl),
|
||||
INTEL_CPU_FAM6(BROADWELL_D, idle_cpu_bdw),
|
||||
INTEL_CPU_FAM6(SKYLAKE_L, idle_cpu_skl),
|
||||
INTEL_CPU_FAM6(SKYLAKE, idle_cpu_skl),
|
||||
INTEL_CPU_FAM6(KABYLAKE_L, idle_cpu_skl),
|
||||
INTEL_CPU_FAM6(KABYLAKE, idle_cpu_skl),
|
||||
INTEL_CPU_FAM6(SKYLAKE_X, idle_cpu_skx),
|
||||
INTEL_CPU_FAM6(XEON_PHI_KNL, idle_cpu_knl),
|
||||
INTEL_CPU_FAM6(XEON_PHI_KNM, idle_cpu_knl),
|
||||
INTEL_CPU_FAM6(ATOM_GOLDMONT, idle_cpu_bxt),
|
||||
INTEL_CPU_FAM6(ATOM_GOLDMONT_PLUS, idle_cpu_bxt),
|
||||
INTEL_CPU_FAM6(ATOM_GOLDMONT_X, idle_cpu_dnv),
|
||||
INTEL_CPU_FAM6(ATOM_TREMONT_X, idle_cpu_dnv),
|
||||
INTEL_CPU_FAM6(ATOM_GOLDMONT_D, idle_cpu_dnv),
|
||||
INTEL_CPU_FAM6(ATOM_TREMONT_D, idle_cpu_dnv),
|
||||
{}
|
||||
};
|
||||
|
||||
|
@ -1311,7 +1311,7 @@ static void intel_idle_state_table_update(void)
|
|||
case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
|
||||
bxt_idle_state_table_update();
|
||||
break;
|
||||
case INTEL_FAM6_SKYLAKE_DESKTOP:
|
||||
case INTEL_FAM6_SKYLAKE:
|
||||
sklh_idle_state_table_update();
|
||||
break;
|
||||
}
|
||||
|
|
|
@ -806,12 +806,12 @@ static inline void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
|
|||
#endif /* CONFIG_DEBUG_FS */
|
||||
|
||||
static const struct x86_cpu_id intel_pmc_core_ids[] = {
|
||||
INTEL_CPU_FAM6(SKYLAKE_MOBILE, spt_reg_map),
|
||||
INTEL_CPU_FAM6(SKYLAKE_DESKTOP, spt_reg_map),
|
||||
INTEL_CPU_FAM6(KABYLAKE_MOBILE, spt_reg_map),
|
||||
INTEL_CPU_FAM6(KABYLAKE_DESKTOP, spt_reg_map),
|
||||
INTEL_CPU_FAM6(CANNONLAKE_MOBILE, cnp_reg_map),
|
||||
INTEL_CPU_FAM6(ICELAKE_MOBILE, icl_reg_map),
|
||||
INTEL_CPU_FAM6(SKYLAKE_L, spt_reg_map),
|
||||
INTEL_CPU_FAM6(SKYLAKE, spt_reg_map),
|
||||
INTEL_CPU_FAM6(KABYLAKE_L, spt_reg_map),
|
||||
INTEL_CPU_FAM6(KABYLAKE, spt_reg_map),
|
||||
INTEL_CPU_FAM6(CANNONLAKE_L, cnp_reg_map),
|
||||
INTEL_CPU_FAM6(ICELAKE_L, icl_reg_map),
|
||||
INTEL_CPU_FAM6(ICELAKE_NNPI, icl_reg_map),
|
||||
{}
|
||||
};
|
||||
|
|
|
@ -30,12 +30,12 @@ static struct platform_device pmc_core_device = {
|
|||
* other list may grow, but this list should not.
|
||||
*/
|
||||
static const struct x86_cpu_id intel_pmc_core_platform_ids[] = {
|
||||
INTEL_CPU_FAM6(SKYLAKE_MOBILE, pmc_core_device),
|
||||
INTEL_CPU_FAM6(SKYLAKE_DESKTOP, pmc_core_device),
|
||||
INTEL_CPU_FAM6(KABYLAKE_MOBILE, pmc_core_device),
|
||||
INTEL_CPU_FAM6(KABYLAKE_DESKTOP, pmc_core_device),
|
||||
INTEL_CPU_FAM6(CANNONLAKE_MOBILE, pmc_core_device),
|
||||
INTEL_CPU_FAM6(ICELAKE_MOBILE, pmc_core_device),
|
||||
INTEL_CPU_FAM6(SKYLAKE_L, pmc_core_device),
|
||||
INTEL_CPU_FAM6(SKYLAKE, pmc_core_device),
|
||||
INTEL_CPU_FAM6(KABYLAKE_L, pmc_core_device),
|
||||
INTEL_CPU_FAM6(KABYLAKE, pmc_core_device),
|
||||
INTEL_CPU_FAM6(CANNONLAKE_L, pmc_core_device),
|
||||
INTEL_CPU_FAM6(ICELAKE_L, pmc_core_device),
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(x86cpu, intel_pmc_core_platform_ids);
|
||||
|
|
|
@ -957,27 +957,27 @@ static const struct x86_cpu_id rapl_ids[] __initconst = {
|
|||
INTEL_CPU_FAM6(IVYBRIDGE, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(IVYBRIDGE_X, rapl_defaults_core),
|
||||
|
||||
INTEL_CPU_FAM6(HASWELL_CORE, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(HASWELL_ULT, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(HASWELL_GT3E, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(HASWELL, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(HASWELL_L, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(HASWELL_G, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(HASWELL_X, rapl_defaults_hsw_server),
|
||||
|
||||
INTEL_CPU_FAM6(BROADWELL_CORE, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(BROADWELL_GT3E, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(BROADWELL_XEON_D, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(BROADWELL, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(BROADWELL_G, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(BROADWELL_D, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(BROADWELL_X, rapl_defaults_hsw_server),
|
||||
|
||||
INTEL_CPU_FAM6(SKYLAKE_DESKTOP, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(SKYLAKE_MOBILE, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(SKYLAKE, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(SKYLAKE_L, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(SKYLAKE_X, rapl_defaults_hsw_server),
|
||||
INTEL_CPU_FAM6(KABYLAKE_MOBILE, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(KABYLAKE_DESKTOP, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(CANNONLAKE_MOBILE, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(ICELAKE_MOBILE, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(ICELAKE_DESKTOP, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(KABYLAKE_L, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(KABYLAKE, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(CANNONLAKE_L, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(ICELAKE_L, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(ICELAKE, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(ICELAKE_NNPI, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(ICELAKE_X, rapl_defaults_hsw_server),
|
||||
INTEL_CPU_FAM6(ICELAKE_XEON_D, rapl_defaults_hsw_server),
|
||||
INTEL_CPU_FAM6(ICELAKE_D, rapl_defaults_hsw_server),
|
||||
|
||||
INTEL_CPU_FAM6(ATOM_SILVERMONT, rapl_defaults_byt),
|
||||
INTEL_CPU_FAM6(ATOM_AIRMONT, rapl_defaults_cht),
|
||||
|
@ -985,8 +985,8 @@ static const struct x86_cpu_id rapl_ids[] __initconst = {
|
|||
INTEL_CPU_FAM6(ATOM_AIRMONT_MID, rapl_defaults_ann),
|
||||
INTEL_CPU_FAM6(ATOM_GOLDMONT, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(ATOM_GOLDMONT_PLUS, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(ATOM_GOLDMONT_X, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(ATOM_TREMONT_X, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(ATOM_GOLDMONT_D, rapl_defaults_core),
|
||||
INTEL_CPU_FAM6(ATOM_TREMONT_D, rapl_defaults_core),
|
||||
|
||||
INTEL_CPU_FAM6(XEON_PHI_KNL, rapl_defaults_hsw_server),
|
||||
INTEL_CPU_FAM6(XEON_PHI_KNM, rapl_defaults_hsw_server),
|
||||
|
|
|
@ -181,7 +181,7 @@ struct prctl_mm_map {
|
|||
#define PR_GET_THP_DISABLE 42
|
||||
|
||||
/*
|
||||
* Tell the kernel to start/stop helping userspace manage bounds tables.
|
||||
* No longer implemented, but left here to ensure the numbers stay reserved:
|
||||
*/
|
||||
#define PR_MPX_ENABLE_MANAGEMENT 43
|
||||
#define PR_MPX_DISABLE_MANAGEMENT 44
|
||||
|
|
14
kernel/sys.c
14
kernel/sys.c
|
@ -103,12 +103,6 @@
|
|||
#ifndef SET_TSC_CTL
|
||||
# define SET_TSC_CTL(a) (-EINVAL)
|
||||
#endif
|
||||
#ifndef MPX_ENABLE_MANAGEMENT
|
||||
# define MPX_ENABLE_MANAGEMENT() (-EINVAL)
|
||||
#endif
|
||||
#ifndef MPX_DISABLE_MANAGEMENT
|
||||
# define MPX_DISABLE_MANAGEMENT() (-EINVAL)
|
||||
#endif
|
||||
#ifndef GET_FP_MODE
|
||||
# define GET_FP_MODE(a) (-EINVAL)
|
||||
#endif
|
||||
|
@ -2462,15 +2456,9 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long, arg2, unsigned long, arg3,
|
|||
up_write(&me->mm->mmap_sem);
|
||||
break;
|
||||
case PR_MPX_ENABLE_MANAGEMENT:
|
||||
if (arg2 || arg3 || arg4 || arg5)
|
||||
return -EINVAL;
|
||||
error = MPX_ENABLE_MANAGEMENT();
|
||||
break;
|
||||
case PR_MPX_DISABLE_MANAGEMENT:
|
||||
if (arg2 || arg3 || arg4 || arg5)
|
||||
/* No longer implemented: */
|
||||
return -EINVAL;
|
||||
error = MPX_DISABLE_MANAGEMENT();
|
||||
break;
|
||||
case PR_SET_FP_MODE:
|
||||
error = SET_FP_MODE(me, arg2);
|
||||
break;
|
||||
|
|
|
@ -21,10 +21,6 @@ KCOV_INSTRUMENT_dynamic_debug.o := n
|
|||
ifdef CONFIG_AMD_MEM_ENCRYPT
|
||||
KASAN_SANITIZE_string.o := n
|
||||
|
||||
ifdef CONFIG_FUNCTION_TRACER
|
||||
CFLAGS_REMOVE_string.o = -pg
|
||||
endif
|
||||
|
||||
CFLAGS_string.o := $(call cc-option, -fno-stack-protector)
|
||||
endif
|
||||
|
||||
|
|
|
@ -96,7 +96,6 @@
|
|||
#define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in IA32 userspace */
|
||||
#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */
|
||||
#define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */
|
||||
#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" MFENCE synchronizes RDTSC */
|
||||
#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */
|
||||
#define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */
|
||||
#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */
|
||||
|
|
|
@ -2168,7 +2168,7 @@ int has_turbo_ratio_group_limits(int family, int model)
|
|||
switch (model) {
|
||||
case INTEL_FAM6_ATOM_GOLDMONT:
|
||||
case INTEL_FAM6_SKYLAKE_X:
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_X:
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_D:
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
|
@ -3234,15 +3234,15 @@ int probe_nhm_msrs(unsigned int family, unsigned int model)
|
|||
pkg_cstate_limits = snb_pkg_cstate_limits;
|
||||
has_misc_feature_control = 1;
|
||||
break;
|
||||
case INTEL_FAM6_HASWELL_CORE: /* HSW */
|
||||
case INTEL_FAM6_HASWELL: /* HSW */
|
||||
case INTEL_FAM6_HASWELL_G: /* HSW */
|
||||
case INTEL_FAM6_HASWELL_X: /* HSX */
|
||||
case INTEL_FAM6_HASWELL_ULT: /* HSW */
|
||||
case INTEL_FAM6_HASWELL_GT3E: /* HSW */
|
||||
case INTEL_FAM6_BROADWELL_CORE: /* BDW */
|
||||
case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
|
||||
case INTEL_FAM6_HASWELL_L: /* HSW */
|
||||
case INTEL_FAM6_BROADWELL: /* BDW */
|
||||
case INTEL_FAM6_BROADWELL_G: /* BDW */
|
||||
case INTEL_FAM6_BROADWELL_X: /* BDX */
|
||||
case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
|
||||
case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */
|
||||
case INTEL_FAM6_SKYLAKE_L: /* SKL */
|
||||
case INTEL_FAM6_CANNONLAKE_L: /* CNL */
|
||||
pkg_cstate_limits = hsw_pkg_cstate_limits;
|
||||
has_misc_feature_control = 1;
|
||||
break;
|
||||
|
@ -3252,7 +3252,7 @@ int probe_nhm_msrs(unsigned int family, unsigned int model)
|
|||
break;
|
||||
case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
|
||||
no_MSR_MISC_PWR_MGMT = 1;
|
||||
case INTEL_FAM6_ATOM_SILVERMONT_X: /* AVN */
|
||||
case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */
|
||||
pkg_cstate_limits = slv_pkg_cstate_limits;
|
||||
break;
|
||||
case INTEL_FAM6_ATOM_AIRMONT: /* AMT */
|
||||
|
@ -3264,7 +3264,7 @@ int probe_nhm_msrs(unsigned int family, unsigned int model)
|
|||
break;
|
||||
case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_X: /* DNV */
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
|
||||
pkg_cstate_limits = glm_pkg_cstate_limits;
|
||||
break;
|
||||
default:
|
||||
|
@ -3307,7 +3307,7 @@ int is_dnv(unsigned int family, unsigned int model)
|
|||
return 0;
|
||||
|
||||
switch (model) {
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_X:
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_D:
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
|
@ -3431,15 +3431,15 @@ int has_config_tdp(unsigned int family, unsigned int model)
|
|||
|
||||
switch (model) {
|
||||
case INTEL_FAM6_IVYBRIDGE: /* IVB */
|
||||
case INTEL_FAM6_HASWELL_CORE: /* HSW */
|
||||
case INTEL_FAM6_HASWELL: /* HSW */
|
||||
case INTEL_FAM6_HASWELL_X: /* HSX */
|
||||
case INTEL_FAM6_HASWELL_ULT: /* HSW */
|
||||
case INTEL_FAM6_HASWELL_GT3E: /* HSW */
|
||||
case INTEL_FAM6_BROADWELL_CORE: /* BDW */
|
||||
case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
|
||||
case INTEL_FAM6_HASWELL_L: /* HSW */
|
||||
case INTEL_FAM6_HASWELL_G: /* HSW */
|
||||
case INTEL_FAM6_BROADWELL: /* BDW */
|
||||
case INTEL_FAM6_BROADWELL_G: /* BDW */
|
||||
case INTEL_FAM6_BROADWELL_X: /* BDX */
|
||||
case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
|
||||
case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */
|
||||
case INTEL_FAM6_SKYLAKE_L: /* SKL */
|
||||
case INTEL_FAM6_CANNONLAKE_L: /* CNL */
|
||||
case INTEL_FAM6_SKYLAKE_X: /* SKX */
|
||||
|
||||
case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */
|
||||
|
@ -3821,7 +3821,7 @@ double get_tdp_intel(unsigned int model)
|
|||
|
||||
switch (model) {
|
||||
case INTEL_FAM6_ATOM_SILVERMONT:
|
||||
case INTEL_FAM6_ATOM_SILVERMONT_X:
|
||||
case INTEL_FAM6_ATOM_SILVERMONT_D:
|
||||
return 30.0;
|
||||
default:
|
||||
return 135.0;
|
||||
|
@ -3870,11 +3870,11 @@ void rapl_probe_intel(unsigned int family, unsigned int model)
|
|||
switch (model) {
|
||||
case INTEL_FAM6_SANDYBRIDGE:
|
||||
case INTEL_FAM6_IVYBRIDGE:
|
||||
case INTEL_FAM6_HASWELL_CORE: /* HSW */
|
||||
case INTEL_FAM6_HASWELL_ULT: /* HSW */
|
||||
case INTEL_FAM6_HASWELL_GT3E: /* HSW */
|
||||
case INTEL_FAM6_BROADWELL_CORE: /* BDW */
|
||||
case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
|
||||
case INTEL_FAM6_HASWELL: /* HSW */
|
||||
case INTEL_FAM6_HASWELL_L: /* HSW */
|
||||
case INTEL_FAM6_HASWELL_G: /* HSW */
|
||||
case INTEL_FAM6_BROADWELL: /* BDW */
|
||||
case INTEL_FAM6_BROADWELL_G: /* BDW */
|
||||
do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO;
|
||||
if (rapl_joules) {
|
||||
BIC_PRESENT(BIC_Pkg_J);
|
||||
|
@ -3894,8 +3894,8 @@ void rapl_probe_intel(unsigned int family, unsigned int model)
|
|||
else
|
||||
BIC_PRESENT(BIC_PkgWatt);
|
||||
break;
|
||||
case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
|
||||
case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */
|
||||
case INTEL_FAM6_SKYLAKE_L: /* SKL */
|
||||
case INTEL_FAM6_CANNONLAKE_L: /* CNL */
|
||||
do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_GFX | RAPL_PKG_POWER_INFO;
|
||||
BIC_PRESENT(BIC_PKG__);
|
||||
BIC_PRESENT(BIC_RAM__);
|
||||
|
@ -3942,7 +3942,7 @@ void rapl_probe_intel(unsigned int family, unsigned int model)
|
|||
}
|
||||
break;
|
||||
case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
|
||||
case INTEL_FAM6_ATOM_SILVERMONT_X: /* AVN */
|
||||
case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */
|
||||
do_rapl = RAPL_PKG | RAPL_CORES;
|
||||
if (rapl_joules) {
|
||||
BIC_PRESENT(BIC_Pkg_J);
|
||||
|
@ -3952,7 +3952,7 @@ void rapl_probe_intel(unsigned int family, unsigned int model)
|
|||
BIC_PRESENT(BIC_CorWatt);
|
||||
}
|
||||
break;
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_X: /* DNV */
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
|
||||
do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS;
|
||||
BIC_PRESENT(BIC_PKG__);
|
||||
BIC_PRESENT(BIC_RAM__);
|
||||
|
@ -4063,9 +4063,9 @@ void perf_limit_reasons_probe(unsigned int family, unsigned int model)
|
|||
return;
|
||||
|
||||
switch (model) {
|
||||
case INTEL_FAM6_HASWELL_CORE: /* HSW */
|
||||
case INTEL_FAM6_HASWELL_ULT: /* HSW */
|
||||
case INTEL_FAM6_HASWELL_GT3E: /* HSW */
|
||||
case INTEL_FAM6_HASWELL: /* HSW */
|
||||
case INTEL_FAM6_HASWELL_L: /* HSW */
|
||||
case INTEL_FAM6_HASWELL_G: /* HSW */
|
||||
do_gfx_perf_limit_reasons = 1;
|
||||
case INTEL_FAM6_HASWELL_X: /* HSX */
|
||||
do_core_perf_limit_reasons = 1;
|
||||
|
@ -4282,19 +4282,19 @@ int has_snb_msrs(unsigned int family, unsigned int model)
|
|||
case INTEL_FAM6_SANDYBRIDGE_X:
|
||||
case INTEL_FAM6_IVYBRIDGE: /* IVB */
|
||||
case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
|
||||
case INTEL_FAM6_HASWELL_CORE: /* HSW */
|
||||
case INTEL_FAM6_HASWELL: /* HSW */
|
||||
case INTEL_FAM6_HASWELL_X: /* HSW */
|
||||
case INTEL_FAM6_HASWELL_ULT: /* HSW */
|
||||
case INTEL_FAM6_HASWELL_GT3E: /* HSW */
|
||||
case INTEL_FAM6_BROADWELL_CORE: /* BDW */
|
||||
case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
|
||||
case INTEL_FAM6_HASWELL_L: /* HSW */
|
||||
case INTEL_FAM6_HASWELL_G: /* HSW */
|
||||
case INTEL_FAM6_BROADWELL: /* BDW */
|
||||
case INTEL_FAM6_BROADWELL_G: /* BDW */
|
||||
case INTEL_FAM6_BROADWELL_X: /* BDX */
|
||||
case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
|
||||
case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */
|
||||
case INTEL_FAM6_SKYLAKE_L: /* SKL */
|
||||
case INTEL_FAM6_CANNONLAKE_L: /* CNL */
|
||||
case INTEL_FAM6_SKYLAKE_X: /* SKX */
|
||||
case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_X: /* DNV */
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
|
@ -4318,10 +4318,10 @@ int has_c8910_msrs(unsigned int family, unsigned int model)
|
|||
return 0;
|
||||
|
||||
switch (model) {
|
||||
case INTEL_FAM6_HASWELL_ULT: /* HSW */
|
||||
case INTEL_FAM6_BROADWELL_CORE: /* BDW */
|
||||
case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
|
||||
case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */
|
||||
case INTEL_FAM6_HASWELL_L: /* HSW */
|
||||
case INTEL_FAM6_BROADWELL: /* BDW */
|
||||
case INTEL_FAM6_SKYLAKE_L: /* SKL */
|
||||
case INTEL_FAM6_CANNONLAKE_L: /* CNL */
|
||||
case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
|
||||
return 1;
|
||||
|
@ -4343,8 +4343,8 @@ int has_skl_msrs(unsigned int family, unsigned int model)
|
|||
return 0;
|
||||
|
||||
switch (model) {
|
||||
case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
|
||||
case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */
|
||||
case INTEL_FAM6_SKYLAKE_L: /* SKL */
|
||||
case INTEL_FAM6_CANNONLAKE_L: /* CNL */
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
|
@ -4356,7 +4356,7 @@ int is_slm(unsigned int family, unsigned int model)
|
|||
return 0;
|
||||
switch (model) {
|
||||
case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
|
||||
case INTEL_FAM6_ATOM_SILVERMONT_X: /* AVN */
|
||||
case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
|
@ -4379,7 +4379,7 @@ int is_cnl(unsigned int family, unsigned int model)
|
|||
return 0;
|
||||
|
||||
switch (model) {
|
||||
case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */
|
||||
case INTEL_FAM6_CANNONLAKE_L: /* CNL */
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
@ -4603,21 +4603,21 @@ unsigned int intel_model_duplicates(unsigned int model)
|
|||
return INTEL_FAM6_XEON_PHI_KNL;
|
||||
|
||||
case INTEL_FAM6_BROADWELL_X:
|
||||
case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
|
||||
case INTEL_FAM6_BROADWELL_D: /* BDX-DE */
|
||||
return INTEL_FAM6_BROADWELL_X;
|
||||
|
||||
case INTEL_FAM6_SKYLAKE_MOBILE:
|
||||
case INTEL_FAM6_SKYLAKE_DESKTOP:
|
||||
case INTEL_FAM6_KABYLAKE_MOBILE:
|
||||
case INTEL_FAM6_KABYLAKE_DESKTOP:
|
||||
return INTEL_FAM6_SKYLAKE_MOBILE;
|
||||
case INTEL_FAM6_SKYLAKE_L:
|
||||
case INTEL_FAM6_SKYLAKE:
|
||||
case INTEL_FAM6_KABYLAKE_L:
|
||||
case INTEL_FAM6_KABYLAKE:
|
||||
return INTEL_FAM6_SKYLAKE_L;
|
||||
|
||||
case INTEL_FAM6_ICELAKE_MOBILE:
|
||||
case INTEL_FAM6_ICELAKE_L:
|
||||
case INTEL_FAM6_ICELAKE_NNPI:
|
||||
return INTEL_FAM6_CANNONLAKE_MOBILE;
|
||||
return INTEL_FAM6_CANNONLAKE_L;
|
||||
|
||||
case INTEL_FAM6_ATOM_TREMONT_X:
|
||||
return INTEL_FAM6_ATOM_GOLDMONT_X;
|
||||
case INTEL_FAM6_ATOM_TREMONT_D:
|
||||
return INTEL_FAM6_ATOM_GOLDMONT_D;
|
||||
}
|
||||
return model;
|
||||
}
|
||||
|
@ -4768,10 +4768,10 @@ void process_cpuid()
|
|||
|
||||
if (crystal_hz == 0)
|
||||
switch(model) {
|
||||
case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
|
||||
case INTEL_FAM6_SKYLAKE_L: /* SKL */
|
||||
crystal_hz = 24000000; /* 24.0 MHz */
|
||||
break;
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_X: /* DNV */
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
|
||||
crystal_hz = 25000000; /* 25.0 MHz */
|
||||
break;
|
||||
case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
|
||||
|
|
|
@ -11,7 +11,7 @@ CAN_BUILD_X86_64 := $(shell ./check_cc.sh $(CC) trivial_64bit_program.c)
|
|||
CAN_BUILD_WITH_NOPIE := $(shell ./check_cc.sh $(CC) trivial_program.c -no-pie)
|
||||
|
||||
TARGETS_C_BOTHBITS := single_step_syscall sysret_ss_attrs syscall_nt test_mremap_vdso \
|
||||
check_initial_reg_state sigreturn iopl mpx-mini-test ioperm \
|
||||
check_initial_reg_state sigreturn iopl ioperm \
|
||||
protection_keys test_vdso test_vsyscall mov_ss_trap \
|
||||
syscall_arg_fault
|
||||
TARGETS_C_32BIT_ONLY := entry_from_vm86 test_syscall_vdso unwind_vdso \
|
||||
|
|
|
@ -1,15 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef _MPX_DEBUG_H
|
||||
#define _MPX_DEBUG_H
|
||||
|
||||
#ifndef DEBUG_LEVEL
|
||||
#define DEBUG_LEVEL 0
|
||||
#endif
|
||||
#define dprintf_level(level, args...) do { if(level <= DEBUG_LEVEL) printf(args); } while(0)
|
||||
#define dprintf1(args...) dprintf_level(1, args)
|
||||
#define dprintf2(args...) dprintf_level(2, args)
|
||||
#define dprintf3(args...) dprintf_level(3, args)
|
||||
#define dprintf4(args...) dprintf_level(4, args)
|
||||
#define dprintf5(args...) dprintf_level(5, args)
|
||||
|
||||
#endif /* _MPX_DEBUG_H */
|
|
@ -1,497 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Written by Dave Hansen <dave.hansen@intel.com>
|
||||
*/
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <sys/types.h>
|
||||
#include <unistd.h>
|
||||
#include <stdio.h>
|
||||
#include <errno.h>
|
||||
#include <sys/stat.h>
|
||||
#include <sys/mman.h>
|
||||
#include <string.h>
|
||||
#include <fcntl.h>
|
||||
#include "mpx-debug.h"
|
||||
#include "mpx-mm.h"
|
||||
#include "mpx-hw.h"
|
||||
|
||||
unsigned long bounds_dir_global;
|
||||
|
||||
#define mpx_dig_abort() __mpx_dig_abort(__FILE__, __func__, __LINE__)
|
||||
static void inline __mpx_dig_abort(const char *file, const char *func, int line)
|
||||
{
|
||||
fprintf(stderr, "MPX dig abort @ %s::%d in %s()\n", file, line, func);
|
||||
printf("MPX dig abort @ %s::%d in %s()\n", file, line, func);
|
||||
abort();
|
||||
}
|
||||
|
||||
/*
|
||||
* run like this (BDIR finds the probably bounds directory):
|
||||
*
|
||||
* BDIR="$(cat /proc/$pid/smaps | grep -B1 2097152 \
|
||||
* | head -1 | awk -F- '{print $1}')";
|
||||
* ./mpx-dig $pid 0x$BDIR
|
||||
*
|
||||
* NOTE:
|
||||
* assumes that the only 2097152-kb VMA is the bounds dir
|
||||
*/
|
||||
|
||||
long nr_incore(void *ptr, unsigned long size_bytes)
|
||||
{
|
||||
int i;
|
||||
long ret = 0;
|
||||
long vec_len = size_bytes / PAGE_SIZE;
|
||||
unsigned char *vec = malloc(vec_len);
|
||||
int incore_ret;
|
||||
|
||||
if (!vec)
|
||||
mpx_dig_abort();
|
||||
|
||||
incore_ret = mincore(ptr, size_bytes, vec);
|
||||
if (incore_ret) {
|
||||
printf("mincore ret: %d\n", incore_ret);
|
||||
perror("mincore");
|
||||
mpx_dig_abort();
|
||||
}
|
||||
for (i = 0; i < vec_len; i++)
|
||||
ret += vec[i];
|
||||
free(vec);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int open_proc(int pid, char *file)
|
||||
{
|
||||
static char buf[100];
|
||||
int fd;
|
||||
|
||||
snprintf(&buf[0], sizeof(buf), "/proc/%d/%s", pid, file);
|
||||
fd = open(&buf[0], O_RDONLY);
|
||||
if (fd < 0)
|
||||
perror(buf);
|
||||
|
||||
return fd;
|
||||
}
|
||||
|
||||
struct vaddr_range {
|
||||
unsigned long start;
|
||||
unsigned long end;
|
||||
};
|
||||
struct vaddr_range *ranges;
|
||||
int nr_ranges_allocated;
|
||||
int nr_ranges_populated;
|
||||
int last_range = -1;
|
||||
|
||||
int __pid_load_vaddrs(int pid)
|
||||
{
|
||||
int ret = 0;
|
||||
int proc_maps_fd = open_proc(pid, "maps");
|
||||
char linebuf[10000];
|
||||
unsigned long start;
|
||||
unsigned long end;
|
||||
char rest[1000];
|
||||
FILE *f = fdopen(proc_maps_fd, "r");
|
||||
|
||||
if (!f)
|
||||
mpx_dig_abort();
|
||||
nr_ranges_populated = 0;
|
||||
while (!feof(f)) {
|
||||
char *readret = fgets(linebuf, sizeof(linebuf), f);
|
||||
int parsed;
|
||||
|
||||
if (readret == NULL) {
|
||||
if (feof(f))
|
||||
break;
|
||||
mpx_dig_abort();
|
||||
}
|
||||
|
||||
parsed = sscanf(linebuf, "%lx-%lx%s", &start, &end, rest);
|
||||
if (parsed != 3)
|
||||
mpx_dig_abort();
|
||||
|
||||
dprintf4("result[%d]: %lx-%lx<->%s\n", parsed, start, end, rest);
|
||||
if (nr_ranges_populated >= nr_ranges_allocated) {
|
||||
ret = -E2BIG;
|
||||
break;
|
||||
}
|
||||
ranges[nr_ranges_populated].start = start;
|
||||
ranges[nr_ranges_populated].end = end;
|
||||
nr_ranges_populated++;
|
||||
}
|
||||
last_range = -1;
|
||||
fclose(f);
|
||||
close(proc_maps_fd);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int pid_load_vaddrs(int pid)
|
||||
{
|
||||
int ret;
|
||||
|
||||
dprintf2("%s(%d)\n", __func__, pid);
|
||||
if (!ranges) {
|
||||
nr_ranges_allocated = 4;
|
||||
ranges = malloc(nr_ranges_allocated * sizeof(ranges[0]));
|
||||
dprintf2("%s(%d) allocated %d ranges @ %p\n", __func__, pid,
|
||||
nr_ranges_allocated, ranges);
|
||||
assert(ranges != NULL);
|
||||
}
|
||||
do {
|
||||
ret = __pid_load_vaddrs(pid);
|
||||
if (!ret)
|
||||
break;
|
||||
if (ret == -E2BIG) {
|
||||
dprintf2("%s(%d) need to realloc\n", __func__, pid);
|
||||
nr_ranges_allocated *= 2;
|
||||
ranges = realloc(ranges,
|
||||
nr_ranges_allocated * sizeof(ranges[0]));
|
||||
dprintf2("%s(%d) allocated %d ranges @ %p\n", __func__,
|
||||
pid, nr_ranges_allocated, ranges);
|
||||
assert(ranges != NULL);
|
||||
dprintf1("reallocating to hold %d ranges\n", nr_ranges_allocated);
|
||||
}
|
||||
} while (1);
|
||||
|
||||
dprintf2("%s(%d) done\n", __func__, pid);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline int vaddr_in_range(unsigned long vaddr, struct vaddr_range *r)
|
||||
{
|
||||
if (vaddr < r->start)
|
||||
return 0;
|
||||
if (vaddr >= r->end)
|
||||
return 0;
|
||||
return 1;
|
||||
}
|
||||
|
||||
static inline int vaddr_mapped_by_range(unsigned long vaddr)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (last_range > 0 && vaddr_in_range(vaddr, &ranges[last_range]))
|
||||
return 1;
|
||||
|
||||
for (i = 0; i < nr_ranges_populated; i++) {
|
||||
struct vaddr_range *r = &ranges[i];
|
||||
|
||||
if (vaddr_in_range(vaddr, r))
|
||||
continue;
|
||||
last_range = i;
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
const int bt_entry_size_bytes = sizeof(unsigned long) * 4;
|
||||
|
||||
void *read_bounds_table_into_buf(unsigned long table_vaddr)
|
||||
{
|
||||
#ifdef MPX_DIG_STANDALONE
|
||||
static char bt_buf[MPX_BOUNDS_TABLE_SIZE_BYTES];
|
||||
off_t seek_ret = lseek(fd, table_vaddr, SEEK_SET);
|
||||
if (seek_ret != table_vaddr)
|
||||
mpx_dig_abort();
|
||||
|
||||
int read_ret = read(fd, &bt_buf, sizeof(bt_buf));
|
||||
if (read_ret != sizeof(bt_buf))
|
||||
mpx_dig_abort();
|
||||
return &bt_buf;
|
||||
#else
|
||||
return (void *)table_vaddr;
|
||||
#endif
|
||||
}
|
||||
|
||||
int dump_table(unsigned long table_vaddr, unsigned long base_controlled_vaddr,
|
||||
unsigned long bde_vaddr)
|
||||
{
|
||||
unsigned long offset_inside_bt;
|
||||
int nr_entries = 0;
|
||||
int do_abort = 0;
|
||||
char *bt_buf;
|
||||
|
||||
dprintf3("%s() base_controlled_vaddr: 0x%012lx bde_vaddr: 0x%012lx\n",
|
||||
__func__, base_controlled_vaddr, bde_vaddr);
|
||||
|
||||
bt_buf = read_bounds_table_into_buf(table_vaddr);
|
||||
|
||||
dprintf4("%s() read done\n", __func__);
|
||||
|
||||
for (offset_inside_bt = 0;
|
||||
offset_inside_bt < MPX_BOUNDS_TABLE_SIZE_BYTES;
|
||||
offset_inside_bt += bt_entry_size_bytes) {
|
||||
unsigned long bt_entry_index;
|
||||
unsigned long bt_entry_controls;
|
||||
unsigned long this_bt_entry_for_vaddr;
|
||||
unsigned long *bt_entry_buf;
|
||||
int i;
|
||||
|
||||
dprintf4("%s() offset_inside_bt: 0x%lx of 0x%llx\n", __func__,
|
||||
offset_inside_bt, MPX_BOUNDS_TABLE_SIZE_BYTES);
|
||||
bt_entry_buf = (void *)&bt_buf[offset_inside_bt];
|
||||
if (!bt_buf) {
|
||||
printf("null bt_buf\n");
|
||||
mpx_dig_abort();
|
||||
}
|
||||
if (!bt_entry_buf) {
|
||||
printf("null bt_entry_buf\n");
|
||||
mpx_dig_abort();
|
||||
}
|
||||
dprintf4("%s() reading *bt_entry_buf @ %p\n", __func__,
|
||||
bt_entry_buf);
|
||||
if (!bt_entry_buf[0] &&
|
||||
!bt_entry_buf[1] &&
|
||||
!bt_entry_buf[2] &&
|
||||
!bt_entry_buf[3])
|
||||
continue;
|
||||
|
||||
nr_entries++;
|
||||
|
||||
bt_entry_index = offset_inside_bt/bt_entry_size_bytes;
|
||||
bt_entry_controls = sizeof(void *);
|
||||
this_bt_entry_for_vaddr =
|
||||
base_controlled_vaddr + bt_entry_index*bt_entry_controls;
|
||||
/*
|
||||
* We sign extend vaddr bits 48->63 which effectively
|
||||
* creates a hole in the virtual address space.
|
||||
* This calculation corrects for the hole.
|
||||
*/
|
||||
if (this_bt_entry_for_vaddr > 0x00007fffffffffffUL)
|
||||
this_bt_entry_for_vaddr |= 0xffff800000000000;
|
||||
|
||||
if (!vaddr_mapped_by_range(this_bt_entry_for_vaddr)) {
|
||||
printf("bt_entry_buf: %p\n", bt_entry_buf);
|
||||
printf("there is a bte for %lx but no mapping\n",
|
||||
this_bt_entry_for_vaddr);
|
||||
printf(" bde vaddr: %016lx\n", bde_vaddr);
|
||||
printf("base_controlled_vaddr: %016lx\n", base_controlled_vaddr);
|
||||
printf(" table_vaddr: %016lx\n", table_vaddr);
|
||||
printf(" entry vaddr: %016lx @ offset %lx\n",
|
||||
table_vaddr + offset_inside_bt, offset_inside_bt);
|
||||
do_abort = 1;
|
||||
mpx_dig_abort();
|
||||
}
|
||||
if (DEBUG_LEVEL < 4)
|
||||
continue;
|
||||
|
||||
printf("table entry[%lx]: ", offset_inside_bt);
|
||||
for (i = 0; i < bt_entry_size_bytes; i += sizeof(unsigned long))
|
||||
printf("0x%016lx ", bt_entry_buf[i]);
|
||||
printf("\n");
|
||||
}
|
||||
if (do_abort)
|
||||
mpx_dig_abort();
|
||||
dprintf4("%s() done\n", __func__);
|
||||
return nr_entries;
|
||||
}
|
||||
|
||||
int search_bd_buf(char *buf, int len_bytes, unsigned long bd_offset_bytes,
|
||||
int *nr_populated_bdes)
|
||||
{
|
||||
unsigned long i;
|
||||
int total_entries = 0;
|
||||
|
||||
dprintf3("%s(%p, %x, %lx, ...) buf end: %p\n", __func__, buf,
|
||||
len_bytes, bd_offset_bytes, buf + len_bytes);
|
||||
|
||||
for (i = 0; i < len_bytes; i += sizeof(unsigned long)) {
|
||||
unsigned long bd_index = (bd_offset_bytes + i) / sizeof(unsigned long);
|
||||
unsigned long *bounds_dir_entry_ptr = (unsigned long *)&buf[i];
|
||||
unsigned long bounds_dir_entry;
|
||||
unsigned long bd_for_vaddr;
|
||||
unsigned long bt_start;
|
||||
unsigned long bt_tail;
|
||||
int nr_entries;
|
||||
|
||||
dprintf4("%s() loop i: %ld bounds_dir_entry_ptr: %p\n", __func__, i,
|
||||
bounds_dir_entry_ptr);
|
||||
|
||||
bounds_dir_entry = *bounds_dir_entry_ptr;
|
||||
if (!bounds_dir_entry) {
|
||||
dprintf4("no bounds dir at index 0x%lx / 0x%lx "
|
||||
"start at offset:%lx %lx\n", bd_index, bd_index,
|
||||
bd_offset_bytes, i);
|
||||
continue;
|
||||
}
|
||||
dprintf3("found bounds_dir_entry: 0x%lx @ "
|
||||
"index 0x%lx buf ptr: %p\n", bounds_dir_entry, i,
|
||||
&buf[i]);
|
||||
/* mask off the enable bit: */
|
||||
bounds_dir_entry &= ~0x1;
|
||||
(*nr_populated_bdes)++;
|
||||
dprintf4("nr_populated_bdes: %p\n", nr_populated_bdes);
|
||||
dprintf4("*nr_populated_bdes: %d\n", *nr_populated_bdes);
|
||||
|
||||
bt_start = bounds_dir_entry;
|
||||
bt_tail = bounds_dir_entry + MPX_BOUNDS_TABLE_SIZE_BYTES - 1;
|
||||
if (!vaddr_mapped_by_range(bt_start)) {
|
||||
printf("bounds directory 0x%lx points to nowhere\n",
|
||||
bounds_dir_entry);
|
||||
mpx_dig_abort();
|
||||
}
|
||||
if (!vaddr_mapped_by_range(bt_tail)) {
|
||||
printf("bounds directory end 0x%lx points to nowhere\n",
|
||||
bt_tail);
|
||||
mpx_dig_abort();
|
||||
}
|
||||
/*
|
||||
* Each bounds directory entry controls 1MB of virtual address
|
||||
* space. This variable is the virtual address in the process
|
||||
* of the beginning of the area controlled by this bounds_dir.
|
||||
*/
|
||||
bd_for_vaddr = bd_index * (1UL<<20);
|
||||
|
||||
nr_entries = dump_table(bounds_dir_entry, bd_for_vaddr,
|
||||
bounds_dir_global+bd_offset_bytes+i);
|
||||
total_entries += nr_entries;
|
||||
dprintf5("dir entry[%4ld @ %p]: 0x%lx %6d entries "
|
||||
"total this buf: %7d bd_for_vaddrs: 0x%lx -> 0x%lx\n",
|
||||
bd_index, buf+i,
|
||||
bounds_dir_entry, nr_entries, total_entries,
|
||||
bd_for_vaddr, bd_for_vaddr + (1UL<<20));
|
||||
}
|
||||
dprintf3("%s(%p, %x, %lx, ...) done\n", __func__, buf, len_bytes,
|
||||
bd_offset_bytes);
|
||||
return total_entries;
|
||||
}
|
||||
|
||||
int proc_pid_mem_fd = -1;
|
||||
|
||||
void *fill_bounds_dir_buf_other(long byte_offset_inside_bounds_dir,
|
||||
long buffer_size_bytes, void *buffer)
|
||||
{
|
||||
unsigned long seekto = bounds_dir_global + byte_offset_inside_bounds_dir;
|
||||
int read_ret;
|
||||
off_t seek_ret = lseek(proc_pid_mem_fd, seekto, SEEK_SET);
|
||||
|
||||
if (seek_ret != seekto)
|
||||
mpx_dig_abort();
|
||||
|
||||
read_ret = read(proc_pid_mem_fd, buffer, buffer_size_bytes);
|
||||
/* there shouldn't practically be short reads of /proc/$pid/mem */
|
||||
if (read_ret != buffer_size_bytes)
|
||||
mpx_dig_abort();
|
||||
|
||||
return buffer;
|
||||
}
|
||||
void *fill_bounds_dir_buf_self(long byte_offset_inside_bounds_dir,
|
||||
long buffer_size_bytes, void *buffer)
|
||||
|
||||
{
|
||||
unsigned char vec[buffer_size_bytes / PAGE_SIZE];
|
||||
char *dig_bounds_dir_ptr =
|
||||
(void *)(bounds_dir_global + byte_offset_inside_bounds_dir);
|
||||
/*
|
||||
* use mincore() to quickly find the areas of the bounds directory
|
||||
* that have memory and thus will be worth scanning.
|
||||
*/
|
||||
int incore_ret;
|
||||
|
||||
int incore = 0;
|
||||
int i;
|
||||
|
||||
dprintf4("%s() dig_bounds_dir_ptr: %p\n", __func__, dig_bounds_dir_ptr);
|
||||
|
||||
incore_ret = mincore(dig_bounds_dir_ptr, buffer_size_bytes, &vec[0]);
|
||||
if (incore_ret) {
|
||||
printf("mincore ret: %d\n", incore_ret);
|
||||
perror("mincore");
|
||||
mpx_dig_abort();
|
||||
}
|
||||
for (i = 0; i < sizeof(vec); i++)
|
||||
incore += vec[i];
|
||||
dprintf4("%s() total incore: %d\n", __func__, incore);
|
||||
if (!incore)
|
||||
return NULL;
|
||||
dprintf3("%s() total incore: %d\n", __func__, incore);
|
||||
return dig_bounds_dir_ptr;
|
||||
}
|
||||
|
||||
int inspect_pid(int pid)
|
||||
{
|
||||
static int dig_nr;
|
||||
long offset_inside_bounds_dir;
|
||||
char bounds_dir_buf[sizeof(unsigned long) * (1UL << 15)];
|
||||
char *dig_bounds_dir_ptr;
|
||||
int total_entries = 0;
|
||||
int nr_populated_bdes = 0;
|
||||
int inspect_self;
|
||||
|
||||
if (getpid() == pid) {
|
||||
dprintf4("inspecting self\n");
|
||||
inspect_self = 1;
|
||||
} else {
|
||||
dprintf4("inspecting pid %d\n", pid);
|
||||
mpx_dig_abort();
|
||||
}
|
||||
|
||||
for (offset_inside_bounds_dir = 0;
|
||||
offset_inside_bounds_dir < MPX_BOUNDS_TABLE_SIZE_BYTES;
|
||||
offset_inside_bounds_dir += sizeof(bounds_dir_buf)) {
|
||||
static int bufs_skipped;
|
||||
int this_entries;
|
||||
|
||||
if (inspect_self) {
|
||||
dig_bounds_dir_ptr =
|
||||
fill_bounds_dir_buf_self(offset_inside_bounds_dir,
|
||||
sizeof(bounds_dir_buf),
|
||||
&bounds_dir_buf[0]);
|
||||
} else {
|
||||
dig_bounds_dir_ptr =
|
||||
fill_bounds_dir_buf_other(offset_inside_bounds_dir,
|
||||
sizeof(bounds_dir_buf),
|
||||
&bounds_dir_buf[0]);
|
||||
}
|
||||
if (!dig_bounds_dir_ptr) {
|
||||
bufs_skipped++;
|
||||
continue;
|
||||
}
|
||||
this_entries = search_bd_buf(dig_bounds_dir_ptr,
|
||||
sizeof(bounds_dir_buf),
|
||||
offset_inside_bounds_dir,
|
||||
&nr_populated_bdes);
|
||||
total_entries += this_entries;
|
||||
}
|
||||
printf("mpx dig (%3d) complete, SUCCESS (%8d / %4d)\n", ++dig_nr,
|
||||
total_entries, nr_populated_bdes);
|
||||
return total_entries + nr_populated_bdes;
|
||||
}
|
||||
|
||||
#ifdef MPX_DIG_REMOTE
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
int err;
|
||||
char *c;
|
||||
unsigned long bounds_dir_entry;
|
||||
int pid;
|
||||
|
||||
printf("mpx-dig starting...\n");
|
||||
err = sscanf(argv[1], "%d", &pid);
|
||||
printf("parsing: '%s', err: %d\n", argv[1], err);
|
||||
if (err != 1)
|
||||
mpx_dig_abort();
|
||||
|
||||
err = sscanf(argv[2], "%lx", &bounds_dir_global);
|
||||
printf("parsing: '%s': %d\n", argv[2], err);
|
||||
if (err != 1)
|
||||
mpx_dig_abort();
|
||||
|
||||
proc_pid_mem_fd = open_proc(pid, "mem");
|
||||
if (proc_pid_mem_fd < 0)
|
||||
mpx_dig_abort();
|
||||
|
||||
inspect_pid(pid);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
long inspect_me(struct mpx_bounds_dir *bounds_dir)
|
||||
{
|
||||
int pid = getpid();
|
||||
|
||||
pid_load_vaddrs(pid);
|
||||
bounds_dir_global = (unsigned long)bounds_dir;
|
||||
dprintf4("enter %s() bounds dir: %p\n", __func__, bounds_dir);
|
||||
return inspect_pid(pid);
|
||||
}
|
|
@ -1,124 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef _MPX_HW_H
|
||||
#define _MPX_HW_H
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
/* Describe the MPX Hardware Layout in here */
|
||||
|
||||
#define NR_MPX_BOUNDS_REGISTERS 4
|
||||
|
||||
#ifdef __i386__
|
||||
|
||||
#define MPX_BOUNDS_TABLE_ENTRY_SIZE_BYTES 16 /* 4 * 32-bits */
|
||||
#define MPX_BOUNDS_TABLE_SIZE_BYTES (1ULL << 14) /* 16k */
|
||||
#define MPX_BOUNDS_DIR_ENTRY_SIZE_BYTES 4
|
||||
#define MPX_BOUNDS_DIR_SIZE_BYTES (1ULL << 22) /* 4MB */
|
||||
|
||||
#define MPX_BOUNDS_TABLE_BOTTOM_BIT 2
|
||||
#define MPX_BOUNDS_TABLE_TOP_BIT 11
|
||||
#define MPX_BOUNDS_DIR_BOTTOM_BIT 12
|
||||
#define MPX_BOUNDS_DIR_TOP_BIT 31
|
||||
|
||||
#else
|
||||
|
||||
/*
|
||||
* Linear Address of "pointer" (LAp)
|
||||
* 0 -> 2: ignored
|
||||
* 3 -> 19: index in to bounds table
|
||||
* 20 -> 47: index in to bounds directory
|
||||
* 48 -> 63: ignored
|
||||
*/
|
||||
|
||||
#define MPX_BOUNDS_TABLE_ENTRY_SIZE_BYTES 32
|
||||
#define MPX_BOUNDS_TABLE_SIZE_BYTES (1ULL << 22) /* 4MB */
|
||||
#define MPX_BOUNDS_DIR_ENTRY_SIZE_BYTES 8
|
||||
#define MPX_BOUNDS_DIR_SIZE_BYTES (1ULL << 31) /* 2GB */
|
||||
|
||||
#define MPX_BOUNDS_TABLE_BOTTOM_BIT 3
|
||||
#define MPX_BOUNDS_TABLE_TOP_BIT 19
|
||||
#define MPX_BOUNDS_DIR_BOTTOM_BIT 20
|
||||
#define MPX_BOUNDS_DIR_TOP_BIT 47
|
||||
|
||||
#endif
|
||||
|
||||
#define MPX_BOUNDS_DIR_NR_ENTRIES \
|
||||
(MPX_BOUNDS_DIR_SIZE_BYTES/MPX_BOUNDS_DIR_ENTRY_SIZE_BYTES)
|
||||
#define MPX_BOUNDS_TABLE_NR_ENTRIES \
|
||||
(MPX_BOUNDS_TABLE_SIZE_BYTES/MPX_BOUNDS_TABLE_ENTRY_SIZE_BYTES)
|
||||
|
||||
#define MPX_BOUNDS_TABLE_ENTRY_VALID_BIT 0x1
|
||||
|
||||
struct mpx_bd_entry {
|
||||
union {
|
||||
char x[MPX_BOUNDS_DIR_ENTRY_SIZE_BYTES];
|
||||
void *contents[0];
|
||||
};
|
||||
} __attribute__((packed));
|
||||
|
||||
struct mpx_bt_entry {
|
||||
union {
|
||||
char x[MPX_BOUNDS_TABLE_ENTRY_SIZE_BYTES];
|
||||
unsigned long contents[0];
|
||||
};
|
||||
} __attribute__((packed));
|
||||
|
||||
struct mpx_bounds_dir {
|
||||
struct mpx_bd_entry entries[MPX_BOUNDS_DIR_NR_ENTRIES];
|
||||
} __attribute__((packed));
|
||||
|
||||
struct mpx_bounds_table {
|
||||
struct mpx_bt_entry entries[MPX_BOUNDS_TABLE_NR_ENTRIES];
|
||||
} __attribute__((packed));
|
||||
|
||||
static inline unsigned long GET_BITS(unsigned long val, int bottombit, int topbit)
|
||||
{
|
||||
int total_nr_bits = topbit - bottombit;
|
||||
unsigned long mask = (1UL << total_nr_bits)-1;
|
||||
return (val >> bottombit) & mask;
|
||||
}
|
||||
|
||||
static inline unsigned long __vaddr_bounds_table_index(void *vaddr)
|
||||
{
|
||||
return GET_BITS((unsigned long)vaddr, MPX_BOUNDS_TABLE_BOTTOM_BIT,
|
||||
MPX_BOUNDS_TABLE_TOP_BIT);
|
||||
}
|
||||
|
||||
static inline unsigned long __vaddr_bounds_directory_index(void *vaddr)
|
||||
{
|
||||
return GET_BITS((unsigned long)vaddr, MPX_BOUNDS_DIR_BOTTOM_BIT,
|
||||
MPX_BOUNDS_DIR_TOP_BIT);
|
||||
}
|
||||
|
||||
static inline struct mpx_bd_entry *mpx_vaddr_to_bd_entry(void *vaddr,
|
||||
struct mpx_bounds_dir *bounds_dir)
|
||||
{
|
||||
unsigned long index = __vaddr_bounds_directory_index(vaddr);
|
||||
return &bounds_dir->entries[index];
|
||||
}
|
||||
|
||||
static inline int bd_entry_valid(struct mpx_bd_entry *bounds_dir_entry)
|
||||
{
|
||||
unsigned long __bd_entry = (unsigned long)bounds_dir_entry->contents;
|
||||
return (__bd_entry & MPX_BOUNDS_TABLE_ENTRY_VALID_BIT);
|
||||
}
|
||||
|
||||
static inline struct mpx_bounds_table *
|
||||
__bd_entry_to_bounds_table(struct mpx_bd_entry *bounds_dir_entry)
|
||||
{
|
||||
unsigned long __bd_entry = (unsigned long)bounds_dir_entry->contents;
|
||||
assert(__bd_entry & MPX_BOUNDS_TABLE_ENTRY_VALID_BIT);
|
||||
__bd_entry &= ~MPX_BOUNDS_TABLE_ENTRY_VALID_BIT;
|
||||
return (struct mpx_bounds_table *)__bd_entry;
|
||||
}
|
||||
|
||||
static inline struct mpx_bt_entry *
|
||||
mpx_vaddr_to_bt_entry(void *vaddr, struct mpx_bounds_dir *bounds_dir)
|
||||
{
|
||||
struct mpx_bd_entry *bde = mpx_vaddr_to_bd_entry(vaddr, bounds_dir);
|
||||
struct mpx_bounds_table *bt = __bd_entry_to_bounds_table(bde);
|
||||
unsigned long index = __vaddr_bounds_table_index(vaddr);
|
||||
return &bt->entries[index];
|
||||
}
|
||||
|
||||
#endif /* _MPX_HW_H */
|
File diff suppressed because it is too large
Load diff
|
@ -1,10 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef _MPX_MM_H
|
||||
#define _MPX_MM_H
|
||||
|
||||
#define PAGE_SIZE 4096
|
||||
#define MB (1UL<<20)
|
||||
|
||||
extern long nr_incore(void *ptr, unsigned long size_bytes);
|
||||
|
||||
#endif /* _MPX_MM_H */
|
Loading…
Reference in a new issue