Documentation/atomic_ops.txt: convert to ReST markup
... and move to core-api folder. Signed-off-by: Silvio Fricke <silvio.fricke@gmail.com> Signed-off-by: Jonathan Corbet <corbet@lwn.net>
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@ -1,36 +1,42 @@
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Semantics and Behavior of Atomic and
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Bitmask Operations
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=======================================================
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Semantics and Behavior of Atomic and Bitmask Operations
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=======================================================
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David S. Miller
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:Author: David S. Miller
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This document is intended to serve as a guide to Linux port
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This document is intended to serve as a guide to Linux port
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maintainers on how to implement atomic counter, bitops, and spinlock
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interfaces properly.
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The atomic_t type should be defined as a signed integer and
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Atomic Type And Operations
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==========================
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The atomic_t type should be defined as a signed integer and
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the atomic_long_t type as a signed long integer. Also, they should
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be made opaque such that any kind of cast to a normal C integer type
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will fail. Something like the following should suffice:
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will fail. Something like the following should suffice::
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typedef struct { int counter; } atomic_t;
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typedef struct { long counter; } atomic_long_t;
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Historically, counter has been declared volatile. This is now discouraged.
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See Documentation/process/volatile-considered-harmful.rst for the complete rationale.
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See :ref:`Documentation/process/volatile-considered-harmful.rst
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<volatile_considered_harmful>` for the complete rationale.
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local_t is very similar to atomic_t. If the counter is per CPU and only
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updated by one CPU, local_t is probably more appropriate. Please see
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Documentation/local_ops.txt for the semantics of local_t.
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:ref:`Documentation/core-api/local_ops.rst <local_ops>` for the semantics of
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local_t.
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The first operations to implement for atomic_t's are the initializers and
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plain reads.
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plain reads. ::
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#define ATOMIC_INIT(i) { (i) }
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#define atomic_set(v, i) ((v)->counter = (i))
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The first macro is used in definitions, such as:
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The first macro is used in definitions, such as::
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static atomic_t my_counter = ATOMIC_INIT(1);
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static atomic_t my_counter = ATOMIC_INIT(1);
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The initializer is atomic in that the return values of the atomic operations
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are guaranteed to be correct reflecting the initialized value if the
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@ -38,10 +44,10 @@ initializer is used before runtime. If the initializer is used at runtime, a
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proper implicit or explicit read memory barrier is needed before reading the
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value with atomic_read from another thread.
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As with all of the atomic_ interfaces, replace the leading "atomic_"
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with "atomic_long_" to operate on atomic_long_t.
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As with all of the ``atomic_`` interfaces, replace the leading ``atomic_``
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with ``atomic_long_`` to operate on atomic_long_t.
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The second interface can be used at runtime, as in:
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The second interface can be used at runtime, as in::
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struct foo { atomic_t counter; };
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...
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@ -59,7 +65,7 @@ been set with this operation or set with another operation. A proper implicit
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or explicit memory barrier is needed before the value set with the operation
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is guaranteed to be readable with atomic_read from another thread.
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Next, we have:
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Next, we have::
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#define atomic_read(v) ((v)->counter)
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@ -73,20 +79,21 @@ initialization by any other thread is visible yet, so the user of the
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interface must take care of that with a proper implicit or explicit memory
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barrier.
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*** WARNING: atomic_read() and atomic_set() DO NOT IMPLY BARRIERS! ***
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.. warning::
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Some architectures may choose to use the volatile keyword, barriers, or inline
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assembly to guarantee some degree of immediacy for atomic_read() and
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atomic_set(). This is not uniformly guaranteed, and may change in the future,
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so all users of atomic_t should treat atomic_read() and atomic_set() as simple
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C statements that may be reordered or optimized away entirely by the compiler
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or processor, and explicitly invoke the appropriate compiler and/or memory
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barrier for each use case. Failure to do so will result in code that may
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suddenly break when used with different architectures or compiler
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optimizations, or even changes in unrelated code which changes how the
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compiler optimizes the section accessing atomic_t variables.
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``atomic_read()`` and ``atomic_set()`` DO NOT IMPLY BARRIERS!
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*** YOU HAVE BEEN WARNED! ***
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Some architectures may choose to use the volatile keyword, barriers, or
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inline assembly to guarantee some degree of immediacy for atomic_read()
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and atomic_set(). This is not uniformly guaranteed, and may change in
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the future, so all users of atomic_t should treat atomic_read() and
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atomic_set() as simple C statements that may be reordered or optimized
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away entirely by the compiler or processor, and explicitly invoke the
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appropriate compiler and/or memory barrier for each use case. Failure
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to do so will result in code that may suddenly break when used with
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different architectures or compiler optimizations, or even changes in
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unrelated code which changes how the compiler optimizes the section
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accessing atomic_t variables.
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Properly aligned pointers, longs, ints, and chars (and unsigned
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equivalents) may be atomically loaded from and stored to in the same
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@ -95,14 +102,14 @@ and WRITE_ONCE() macros should be used to prevent the compiler from using
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optimizations that might otherwise optimize accesses out of existence on
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the one hand, or that might create unsolicited accesses on the other.
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For example consider the following code:
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For example consider the following code::
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while (a > 0)
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do_something();
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If the compiler can prove that do_something() does not store to the
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variable a, then the compiler is within its rights transforming this to
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the following:
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the following::
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tmp = a;
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if (a > 0)
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@ -110,14 +117,14 @@ the following:
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do_something();
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If you don't want the compiler to do this (and you probably don't), then
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you should use something like the following:
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you should use something like the following::
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while (READ_ONCE(a) < 0)
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do_something();
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Alternatively, you could place a barrier() call in the loop.
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For another example, consider the following code:
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For another example, consider the following code::
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tmp_a = a;
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do_something_with(tmp_a);
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If the compiler can prove that do_something_with() does not store to the
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variable a, then the compiler is within its rights to manufacture an
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additional load as follows:
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additional load as follows::
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tmp_a = a;
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do_something_with(tmp_a);
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do_something_with() was an inline function that made very heavy use
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of registers: reloading from variable a could save a flush to the
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stack and later reload. To prevent the compiler from attacking your
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code in this manner, write the following:
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code in this manner, write the following::
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tmp_a = READ_ONCE(a);
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do_something_with(tmp_a);
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For a final example, consider the following code, assuming that the
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variable a is set at boot time before the second CPU is brought online
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and never changed later, so that memory barriers are not needed:
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and never changed later, so that memory barriers are not needed::
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if (a)
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b = 9;
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b = 42;
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The compiler is within its rights to manufacture an additional store
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by transforming the above code into the following:
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by transforming the above code into the following::
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b = 42;
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if (a)
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@ -163,7 +170,7 @@ by transforming the above code into the following:
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This could come as a fatal surprise to other code running concurrently
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that expected b to never have the value 42 if a was zero. To prevent
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the compiler from doing this, write something like:
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the compiler from doing this, write something like::
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if (a)
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WRITE_ONCE(b, 9);
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@ -173,10 +180,12 @@ the compiler from doing this, write something like:
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Don't even -think- about doing this without proper use of memory barriers,
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locks, or atomic operations if variable a can change at runtime!
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*** WARNING: READ_ONCE() OR WRITE_ONCE() DO NOT IMPLY A BARRIER! ***
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.. warning::
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``READ_ONCE()`` OR ``WRITE_ONCE()`` DO NOT IMPLY A BARRIER!
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Now, we move onto the atomic operation interfaces typically implemented with
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the help of assembly code.
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the help of assembly code. ::
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void atomic_add(int i, atomic_t *v);
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void atomic_sub(int i, atomic_t *v);
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require any explicit memory barriers. They need only perform the
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atomic_t counter update in an SMP safe manner.
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Next, we have:
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Next, we have::
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int atomic_inc_return(atomic_t *v);
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int atomic_dec_return(atomic_t *v);
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memory barrier semantics which satisfy the above requirements, that is
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fine as well.
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Let's move on:
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Let's move on::
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int atomic_add_return(int i, atomic_t *v);
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int atomic_sub_return(int i, atomic_t *v);
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This means that like atomic_{inc,dec}_return(), the memory barrier
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semantics are required.
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Next:
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Next::
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int atomic_inc_and_test(atomic_t *v);
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int atomic_dec_and_test(atomic_t *v);
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resulting counter value was zero or not.
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Again, these primitives provide explicit memory barrier semantics around
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the atomic operation.
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the atomic operation::
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int atomic_sub_and_test(int i, atomic_t *v);
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This is identical to atomic_dec_and_test() except that an explicit
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decrement is given instead of the implicit "1". This primitive must
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provide explicit memory barrier semantics around the operation.
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provide explicit memory barrier semantics around the operation::
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int atomic_add_negative(int i, atomic_t *v);
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This primitive must provide explicit memory barrier semantics around
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the operation.
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Then:
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Then::
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int atomic_xchg(atomic_t *v, int new);
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the given new value. It returns the old value that the atomic variable v had
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just before the operation.
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atomic_xchg must provide explicit memory barriers around the operation.
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atomic_xchg must provide explicit memory barriers around the operation. ::
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int atomic_cmpxchg(atomic_t *v, int old, int new);
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This performs an atomic compare exchange operation on the atomic value v,
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with the given old and new values. Like all atomic_xxx operations,
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atomic_cmpxchg will only satisfy its atomicity semantics as long as all
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other accesses of *v are performed through atomic_xxx operations.
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other accesses of \*v are performed through atomic_xxx operations.
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atomic_cmpxchg must provide explicit memory barriers around the operation,
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although if the comparison fails then no memory ordering guarantees are
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@ -273,7 +282,7 @@ required.
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The semantics for atomic_cmpxchg are the same as those defined for 'cas'
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below.
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Finally:
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Finally::
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int atomic_add_unless(atomic_t *v, int a, int u);
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If a caller requires memory barrier semantics around an atomic_t
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operation which does not return a value, a set of interfaces are
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defined which accomplish this:
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defined which accomplish this::
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void smp_mb__before_atomic(void);
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void smp_mb__after_atomic(void);
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For example, smp_mb__before_atomic() can be used like so:
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For example, smp_mb__before_atomic() can be used like so::
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obj->dead = 1;
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smp_mb__before_atomic();
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@ -315,67 +324,69 @@ atomic_t implementation above can have disastrous results. Here is
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an example, which follows a pattern occurring frequently in the Linux
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kernel. It is the use of atomic counters to implement reference
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counting, and it works such that once the counter falls to zero it can
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be guaranteed that no other entity can be accessing the object:
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be guaranteed that no other entity can be accessing the object::
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static void obj_list_add(struct obj *obj, struct list_head *head)
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{
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obj->active = 1;
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list_add(&obj->list, head);
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}
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static void obj_list_add(struct obj *obj, struct list_head *head)
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{
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obj->active = 1;
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list_add(&obj->list, head);
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}
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static void obj_list_del(struct obj *obj)
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{
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list_del(&obj->list);
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obj->active = 0;
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}
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static void obj_list_del(struct obj *obj)
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{
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list_del(&obj->list);
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obj->active = 0;
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}
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static void obj_destroy(struct obj *obj)
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{
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BUG_ON(obj->active);
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kfree(obj);
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}
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static void obj_destroy(struct obj *obj)
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{
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BUG_ON(obj->active);
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kfree(obj);
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}
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struct obj *obj_list_peek(struct list_head *head)
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{
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if (!list_empty(head)) {
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struct obj *obj_list_peek(struct list_head *head)
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{
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if (!list_empty(head)) {
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struct obj *obj;
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obj = list_entry(head->next, struct obj, list);
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atomic_inc(&obj->refcnt);
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return obj;
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}
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return NULL;
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}
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void obj_poke(void)
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{
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struct obj *obj;
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obj = list_entry(head->next, struct obj, list);
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atomic_inc(&obj->refcnt);
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return obj;
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spin_lock(&global_list_lock);
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obj = obj_list_peek(&global_list);
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spin_unlock(&global_list_lock);
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if (obj) {
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obj->ops->poke(obj);
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if (atomic_dec_and_test(&obj->refcnt))
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obj_destroy(obj);
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}
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}
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return NULL;
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}
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void obj_poke(void)
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{
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struct obj *obj;
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void obj_timeout(struct obj *obj)
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{
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spin_lock(&global_list_lock);
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obj_list_del(obj);
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spin_unlock(&global_list_lock);
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spin_lock(&global_list_lock);
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obj = obj_list_peek(&global_list);
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spin_unlock(&global_list_lock);
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if (obj) {
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obj->ops->poke(obj);
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if (atomic_dec_and_test(&obj->refcnt))
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obj_destroy(obj);
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}
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}
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void obj_timeout(struct obj *obj)
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{
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spin_lock(&global_list_lock);
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obj_list_del(obj);
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spin_unlock(&global_list_lock);
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.. note::
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if (atomic_dec_and_test(&obj->refcnt))
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obj_destroy(obj);
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}
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(This is a simplification of the ARP queue management in the
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generic neighbour discover code of the networking. Olaf Kirch
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found a bug wrt. memory barriers in kfree_skb() that exposed
|
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the atomic_t memory barrier requirements quite clearly.)
|
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This is a simplification of the ARP queue management in the generic
|
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neighbour discover code of the networking. Olaf Kirch found a bug wrt.
|
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memory barriers in kfree_skb() that exposed the atomic_t memory barrier
|
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requirements quite clearly.
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|
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Given the above scheme, it must be the case that the obj->active
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update done by the obj list deletion be visible to other processors
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|
@ -383,7 +394,7 @@ before the atomic counter decrement is performed.
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Otherwise, the counter could fall to zero, yet obj->active would still
|
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be set, thus triggering the assertion in obj_destroy(). The error
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sequence looks like this:
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sequence looks like this::
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|
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cpu 0 cpu 1
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obj_poke() obj_timeout()
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|
@ -420,6 +431,10 @@ same scheme.
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Another note is that the atomic_t operations returning values are
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extremely slow on an old 386.
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Atomic Bitmask
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==============
|
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|
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We will now cover the atomic bitmask operations. You will find that
|
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their SMP and memory barrier semantics are similar in shape and scope
|
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to the atomic_t ops above.
|
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|
@ -427,7 +442,7 @@ to the atomic_t ops above.
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|||
Native atomic bit operations are defined to operate on objects aligned
|
||||
to the size of an "unsigned long" C data type, and are least of that
|
||||
size. The endianness of the bits within each "unsigned long" are the
|
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native endianness of the cpu.
|
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native endianness of the cpu. ::
|
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|
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void set_bit(unsigned long nr, volatile unsigned long *addr);
|
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void clear_bit(unsigned long nr, volatile unsigned long *addr);
|
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|
@ -437,7 +452,7 @@ These routines set, clear, and change, respectively, the bit number
|
|||
indicated by "nr" on the bit mask pointed to by "ADDR".
|
||||
|
||||
They must execute atomically, yet there are no implicit memory barrier
|
||||
semantics required of these interfaces.
|
||||
semantics required of these interfaces. ::
|
||||
|
||||
int test_and_set_bit(unsigned long nr, volatile unsigned long *addr);
|
||||
int test_and_clear_bit(unsigned long nr, volatile unsigned long *addr);
|
||||
|
@ -466,7 +481,7 @@ must provide explicit memory barrier semantics around their execution.
|
|||
All memory operations before the atomic bit operation call must be
|
||||
made visible globally before the atomic bit operation is made visible.
|
||||
Likewise, the atomic bit operation must be visible globally before any
|
||||
subsequent memory operation is made visible. For example:
|
||||
subsequent memory operation is made visible. For example::
|
||||
|
||||
obj->dead = 1;
|
||||
if (test_and_set_bit(0, &obj->flags))
|
||||
|
@ -479,7 +494,7 @@ done by test_and_set_bit() becomes visible. Likewise, the atomic
|
|||
memory operation done by test_and_set_bit() must become visible before
|
||||
"obj->killed = 1;" is visible.
|
||||
|
||||
Finally there is the basic operation:
|
||||
Finally there is the basic operation::
|
||||
|
||||
int test_bit(unsigned long nr, __const__ volatile unsigned long *addr);
|
||||
|
||||
|
@ -488,13 +503,13 @@ pointed to by "addr".
|
|||
|
||||
If explicit memory barriers are required around {set,clear}_bit() (which do
|
||||
not return a value, and thus does not need to provide memory barrier
|
||||
semantics), two interfaces are provided:
|
||||
semantics), two interfaces are provided::
|
||||
|
||||
void smp_mb__before_atomic(void);
|
||||
void smp_mb__after_atomic(void);
|
||||
|
||||
They are used as follows, and are akin to their atomic_t operation
|
||||
brothers:
|
||||
brothers::
|
||||
|
||||
/* All memory operations before this call will
|
||||
* be globally visible before the clear_bit().
|
||||
|
@ -511,7 +526,7 @@ There are two special bitops with lock barrier semantics (acquire/release,
|
|||
same as spinlocks). These operate in the same way as their non-_lock/unlock
|
||||
postfixed variants, except that they are to provide acquire/release semantics,
|
||||
respectively. This means they can be used for bit_spin_trylock and
|
||||
bit_spin_unlock type operations without specifying any more barriers.
|
||||
bit_spin_unlock type operations without specifying any more barriers. ::
|
||||
|
||||
int test_and_set_bit_lock(unsigned long nr, unsigned long *addr);
|
||||
void clear_bit_unlock(unsigned long nr, unsigned long *addr);
|
||||
|
@ -526,7 +541,7 @@ provided. They are used in contexts where some other higher-level SMP
|
|||
locking scheme is being used to protect the bitmask, and thus less
|
||||
expensive non-atomic operations may be used in the implementation.
|
||||
They have names similar to the above bitmask operation interfaces,
|
||||
except that two underscores are prefixed to the interface name.
|
||||
except that two underscores are prefixed to the interface name. ::
|
||||
|
||||
void __set_bit(unsigned long nr, volatile unsigned long *addr);
|
||||
void __clear_bit(unsigned long nr, volatile unsigned long *addr);
|
||||
|
@ -542,9 +557,11 @@ The routines xchg() and cmpxchg() must provide the same exact
|
|||
memory-barrier semantics as the atomic and bit operations returning
|
||||
values.
|
||||
|
||||
Note: If someone wants to use xchg(), cmpxchg() and their variants,
|
||||
linux/atomic.h should be included rather than asm/cmpxchg.h, unless
|
||||
the code is in arch/* and can take care of itself.
|
||||
.. note::
|
||||
|
||||
If someone wants to use xchg(), cmpxchg() and their variants,
|
||||
linux/atomic.h should be included rather than asm/cmpxchg.h, unless the
|
||||
code is in arch/* and can take care of itself.
|
||||
|
||||
Spinlocks and rwlocks have memory barrier expectations as well.
|
||||
The rule to follow is simple:
|
||||
|
@ -558,7 +575,7 @@ The rule to follow is simple:
|
|||
|
||||
Which finally brings us to _atomic_dec_and_lock(). There is an
|
||||
architecture-neutral version implemented in lib/dec_and_lock.c,
|
||||
but most platforms will wish to optimize this in assembler.
|
||||
but most platforms will wish to optimize this in assembler. ::
|
||||
|
||||
int _atomic_dec_and_lock(atomic_t *atomic, spinlock_t *lock);
|
||||
|
||||
|
@ -573,7 +590,7 @@ sure the spinlock operation is globally visible before any
|
|||
subsequent memory operation.
|
||||
|
||||
We can demonstrate this operation more clearly if we define
|
||||
an abstract atomic operation:
|
||||
an abstract atomic operation::
|
||||
|
||||
long cas(long *mem, long old, long new);
|
||||
|
||||
|
@ -584,48 +601,48 @@ an abstract atomic operation:
|
|||
3) Regardless, the current value at "mem" is returned.
|
||||
|
||||
As an example usage, here is what an atomic counter update
|
||||
might look like:
|
||||
might look like::
|
||||
|
||||
void example_atomic_inc(long *counter)
|
||||
{
|
||||
long old, new, ret;
|
||||
void example_atomic_inc(long *counter)
|
||||
{
|
||||
long old, new, ret;
|
||||
|
||||
while (1) {
|
||||
old = *counter;
|
||||
new = old + 1;
|
||||
while (1) {
|
||||
old = *counter;
|
||||
new = old + 1;
|
||||
|
||||
ret = cas(counter, old, new);
|
||||
if (ret == old)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
Let's use cas() in order to build a pseudo-C atomic_dec_and_lock():
|
||||
|
||||
int _atomic_dec_and_lock(atomic_t *atomic, spinlock_t *lock)
|
||||
{
|
||||
long old, new, ret;
|
||||
int went_to_zero;
|
||||
|
||||
went_to_zero = 0;
|
||||
while (1) {
|
||||
old = atomic_read(atomic);
|
||||
new = old - 1;
|
||||
if (new == 0) {
|
||||
went_to_zero = 1;
|
||||
spin_lock(lock);
|
||||
}
|
||||
ret = cas(atomic, old, new);
|
||||
if (ret == old)
|
||||
break;
|
||||
if (went_to_zero) {
|
||||
spin_unlock(lock);
|
||||
went_to_zero = 0;
|
||||
ret = cas(counter, old, new);
|
||||
if (ret == old)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return went_to_zero;
|
||||
}
|
||||
Let's use cas() in order to build a pseudo-C atomic_dec_and_lock()::
|
||||
|
||||
int _atomic_dec_and_lock(atomic_t *atomic, spinlock_t *lock)
|
||||
{
|
||||
long old, new, ret;
|
||||
int went_to_zero;
|
||||
|
||||
went_to_zero = 0;
|
||||
while (1) {
|
||||
old = atomic_read(atomic);
|
||||
new = old - 1;
|
||||
if (new == 0) {
|
||||
went_to_zero = 1;
|
||||
spin_lock(lock);
|
||||
}
|
||||
ret = cas(atomic, old, new);
|
||||
if (ret == old)
|
||||
break;
|
||||
if (went_to_zero) {
|
||||
spin_unlock(lock);
|
||||
went_to_zero = 0;
|
||||
}
|
||||
}
|
||||
|
||||
return went_to_zero;
|
||||
}
|
||||
|
||||
Now, as far as memory barriers go, as long as spin_lock()
|
||||
strictly orders all subsequent memory operations (including
|
||||
|
@ -635,6 +652,7 @@ Said another way, _atomic_dec_and_lock() must guarantee that
|
|||
a counter dropping to zero is never made visible before the
|
||||
spinlock being acquired.
|
||||
|
||||
Note that this also means that for the case where the counter
|
||||
is not dropping to zero, there are no memory ordering
|
||||
requirements.
|
||||
.. note::
|
||||
|
||||
Note that this also means that for the case where the counter is not
|
||||
dropping to zero, there are no memory ordering requirements.
|
|
@ -8,6 +8,7 @@ Kernel and driver related documentation.
|
|||
:maxdepth: 1
|
||||
|
||||
assoc_array
|
||||
atomic_ops
|
||||
local_ops
|
||||
workqueue
|
||||
|
||||
|
|
|
@ -1,3 +1,6 @@
|
|||
|
||||
.. _volatile_considered_harmful:
|
||||
|
||||
Why the "volatile" type class should not be used
|
||||
------------------------------------------------
|
||||
|
||||
|
|
Loading…
Reference in a new issue