phy: qcom-ufs: add support for 20nm phy
This change adds a support for a 20nm qcom-ufs phy that is required in platforms that use ufs-qcom controller. Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> Reviewed-by: Dov Levenglick <dovl@codeaurora.org> Signed-off-by: Christoph Hellwig <hch@lst.de>
This commit is contained in:
Yaniv Gardi
Christoph Hellwig
parent
adaafaa393
commit
39e794bff7
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@ -35,3 +35,4 @@ obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
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obj-$(CONFIG_PHY_STIH407_USB) += phy-stih407-usb.o
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obj-$(CONFIG_PHY_STIH41X_USB) += phy-stih41x-usb.o
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obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs.o
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obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-20nm.o
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@ -15,15 +15,56 @@
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#ifndef UFS_QCOM_PHY_I_H_
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#define UFS_QCOM_PHY_I_H_
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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#include <linux/phy/phy.h>
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#include <linux/phy/phy-qcom-ufs.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#define readl_poll_timeout(addr, val, cond, sleep_us, timeout_us) \
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({ \
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ktime_t timeout = ktime_add_us(ktime_get(), timeout_us); \
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might_sleep_if(timeout_us); \
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for (;;) { \
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(val) = readl(addr); \
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if (cond) \
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break; \
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if (timeout_us && ktime_compare(ktime_get(), timeout) > 0) { \
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(val) = readl(addr); \
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break; \
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} \
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if (sleep_us) \
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usleep_range(DIV_ROUND_UP(sleep_us, 4), sleep_us); \
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} \
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(cond) ? 0 : -ETIMEDOUT; \
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})
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#define UFS_QCOM_PHY_CAL_ENTRY(reg, val) \
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{ \
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.reg_offset = reg, \
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.cfg_value = val, \
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}
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#define UFS_QCOM_PHY_NAME_LEN 30
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enum {
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MASK_SERDES_START = 0x1,
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MASK_PCS_READY = 0x1,
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};
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enum {
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OFFSET_SERDES_START = 0x0,
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};
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struct ufs_qcom_phy_stored_attributes {
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u32 att;
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u32 value;
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};
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struct ufs_qcom_phy_calibration {
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u32 reg_offset;
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u32 cfg_value;
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257
drivers/phy/phy-qcom-ufs-qmp-20nm.c
Normal file
257
drivers/phy/phy-qcom-ufs-qmp-20nm.c
Normal file
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@ -0,0 +1,257 @@
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/*
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* Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include "phy-qcom-ufs-qmp-20nm.h"
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#define UFS_PHY_NAME "ufs_phy_qmp_20nm"
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static
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int ufs_qcom_phy_qmp_20nm_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
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bool is_rate_B)
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{
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struct ufs_qcom_phy_calibration *tbl_A, *tbl_B;
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int tbl_size_A, tbl_size_B;
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u8 major = ufs_qcom_phy->host_ctrl_rev_major;
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u16 minor = ufs_qcom_phy->host_ctrl_rev_minor;
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u16 step = ufs_qcom_phy->host_ctrl_rev_step;
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int err;
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if ((major == 0x1) && (minor == 0x002) && (step == 0x0000)) {
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tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_1_2_0);
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tbl_A = phy_cal_table_rate_A_1_2_0;
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} else if ((major == 0x1) && (minor == 0x003) && (step == 0x0000)) {
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tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_1_3_0);
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tbl_A = phy_cal_table_rate_A_1_3_0;
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} else {
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dev_err(ufs_qcom_phy->dev, "%s: Unknown UFS-PHY version, no calibration values\n",
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__func__);
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err = -ENODEV;
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goto out;
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}
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tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);
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tbl_B = phy_cal_table_rate_B;
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err = ufs_qcom_phy_calibrate(ufs_qcom_phy, tbl_A, tbl_size_A,
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tbl_B, tbl_size_B, is_rate_B);
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if (err)
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dev_err(ufs_qcom_phy->dev, "%s: ufs_qcom_phy_calibrate() failed %d\n",
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__func__, err);
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out:
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return err;
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}
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static
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void ufs_qcom_phy_qmp_20nm_advertise_quirks(struct ufs_qcom_phy *phy_common)
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{
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phy_common->quirks =
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UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;
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}
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static int ufs_qcom_phy_qmp_20nm_init(struct phy *generic_phy)
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{
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struct ufs_qcom_phy_qmp_20nm *phy = phy_get_drvdata(generic_phy);
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struct ufs_qcom_phy *phy_common = &phy->common_cfg;
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int err = 0;
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err = ufs_qcom_phy_init_clks(generic_phy, phy_common);
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if (err) {
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dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_clks() failed %d\n",
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__func__, err);
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goto out;
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}
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err = ufs_qcom_phy_init_vregulators(generic_phy, phy_common);
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if (err) {
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dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_vregulators() failed %d\n",
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__func__, err);
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goto out;
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}
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ufs_qcom_phy_qmp_20nm_advertise_quirks(phy_common);
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out:
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return err;
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}
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static
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void ufs_qcom_phy_qmp_20nm_power_control(struct ufs_qcom_phy *phy, bool val)
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{
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bool hibern8_exit_after_pwr_collapse = phy->quirks &
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UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;
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if (val) {
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writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
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/*
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* Before any transactions involving PHY, ensure PHY knows
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* that it's analog rail is powered ON.
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*/
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mb();
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if (hibern8_exit_after_pwr_collapse) {
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/*
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* Give atleast 1us delay after restoring PHY analog
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* power.
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*/
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usleep_range(1, 2);
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writel_relaxed(0x0A, phy->mmio +
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QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
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writel_relaxed(0x08, phy->mmio +
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QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
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/*
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* Make sure workaround is deactivated before proceeding
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* with normal PHY operations.
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*/
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mb();
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}
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} else {
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if (hibern8_exit_after_pwr_collapse) {
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writel_relaxed(0x0A, phy->mmio +
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QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
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writel_relaxed(0x02, phy->mmio +
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QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
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/*
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* Make sure that above workaround is activated before
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* PHY analog power collapse.
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*/
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mb();
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}
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writel_relaxed(0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
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/*
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* ensure that PHY knows its PHY analog rail is going
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* to be powered down
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*/
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mb();
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}
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}
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static
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void ufs_qcom_phy_qmp_20nm_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val)
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{
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writel_relaxed(val & UFS_PHY_TX_LANE_ENABLE_MASK,
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phy->mmio + UFS_PHY_TX_LANE_ENABLE);
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mb();
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}
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static inline void ufs_qcom_phy_qmp_20nm_start_serdes(struct ufs_qcom_phy *phy)
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{
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u32 tmp;
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tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START);
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tmp &= ~MASK_SERDES_START;
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tmp |= (1 << OFFSET_SERDES_START);
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writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START);
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mb();
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}
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static int ufs_qcom_phy_qmp_20nm_is_pcs_ready(struct ufs_qcom_phy *phy_common)
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{
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int err = 0;
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u32 val;
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err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS,
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val, (val & MASK_PCS_READY), 10, 1000000);
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if (err)
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dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n",
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__func__, err);
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return err;
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}
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static struct phy_ops ufs_qcom_phy_qmp_20nm_phy_ops = {
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.init = ufs_qcom_phy_qmp_20nm_init,
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.exit = ufs_qcom_phy_exit,
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.power_on = ufs_qcom_phy_power_on,
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.power_off = ufs_qcom_phy_power_off,
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.owner = THIS_MODULE,
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};
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static struct ufs_qcom_phy_specific_ops phy_20nm_ops = {
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.calibrate_phy = ufs_qcom_phy_qmp_20nm_phy_calibrate,
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.start_serdes = ufs_qcom_phy_qmp_20nm_start_serdes,
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.is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_20nm_is_pcs_ready,
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.set_tx_lane_enable = ufs_qcom_phy_qmp_20nm_set_tx_lane_enable,
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.power_control = ufs_qcom_phy_qmp_20nm_power_control,
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};
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static int ufs_qcom_phy_qmp_20nm_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct phy *generic_phy;
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struct ufs_qcom_phy_qmp_20nm *phy;
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int err = 0;
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phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
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if (!phy) {
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dev_err(dev, "%s: failed to allocate phy\n", __func__);
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err = -ENOMEM;
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goto out;
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}
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generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg,
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&ufs_qcom_phy_qmp_20nm_phy_ops, &phy_20nm_ops);
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if (!generic_phy) {
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dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n",
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__func__);
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err = -EIO;
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goto out;
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}
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phy_set_drvdata(generic_phy, phy);
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strlcpy(phy->common_cfg.name, UFS_PHY_NAME,
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sizeof(phy->common_cfg.name));
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out:
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return err;
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}
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static int ufs_qcom_phy_qmp_20nm_remove(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct phy *generic_phy = to_phy(dev);
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struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
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int err = 0;
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err = ufs_qcom_phy_remove(generic_phy, ufs_qcom_phy);
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if (err)
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dev_err(dev, "%s: ufs_qcom_phy_remove failed = %d\n",
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__func__, err);
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return err;
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}
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static const struct of_device_id ufs_qcom_phy_qmp_20nm_of_match[] = {
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{.compatible = "qcom,ufs-phy-qmp-20nm"},
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{},
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};
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MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_20nm_of_match);
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static struct platform_driver ufs_qcom_phy_qmp_20nm_driver = {
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.probe = ufs_qcom_phy_qmp_20nm_probe,
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.remove = ufs_qcom_phy_qmp_20nm_remove,
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.driver = {
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.of_match_table = ufs_qcom_phy_qmp_20nm_of_match,
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.name = "ufs_qcom_phy_qmp_20nm",
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.owner = THIS_MODULE,
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},
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};
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module_platform_driver(ufs_qcom_phy_qmp_20nm_driver);
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MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP 20nm");
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MODULE_LICENSE("GPL v2");
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235
drivers/phy/phy-qcom-ufs-qmp-20nm.h
Normal file
235
drivers/phy/phy-qcom-ufs-qmp-20nm.h
Normal file
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@ -0,0 +1,235 @@
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/*
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* Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
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*
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*/
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#ifndef UFS_QCOM_PHY_QMP_20NM_H_
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#define UFS_QCOM_PHY_QMP_20NM_H_
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#include "phy-qcom-ufs-i.h"
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/* QCOM UFS PHY control registers */
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#define COM_OFF(x) (0x000 + x)
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#define PHY_OFF(x) (0xC00 + x)
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#define TX_OFF(n, x) (0x400 + (0x400 * n) + x)
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#define RX_OFF(n, x) (0x600 + (0x400 * n) + x)
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/* UFS PHY PLL block registers */
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#define QSERDES_COM_SYS_CLK_CTRL COM_OFF(0x0)
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#define QSERDES_COM_PLL_VCOTAIL_EN COM_OFF(0x04)
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#define QSERDES_COM_PLL_CNTRL COM_OFF(0x14)
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#define QSERDES_COM_PLL_IP_SETI COM_OFF(0x24)
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#define QSERDES_COM_CORE_CLK_IN_SYNC_SEL COM_OFF(0x28)
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#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN COM_OFF(0x30)
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#define QSERDES_COM_PLL_CP_SETI COM_OFF(0x34)
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#define QSERDES_COM_PLL_IP_SETP COM_OFF(0x38)
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#define QSERDES_COM_PLL_CP_SETP COM_OFF(0x3C)
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#define QSERDES_COM_SYSCLK_EN_SEL_TXBAND COM_OFF(0x48)
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#define QSERDES_COM_RESETSM_CNTRL COM_OFF(0x4C)
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#define QSERDES_COM_RESETSM_CNTRL2 COM_OFF(0x50)
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#define QSERDES_COM_PLLLOCK_CMP1 COM_OFF(0x90)
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#define QSERDES_COM_PLLLOCK_CMP2 COM_OFF(0x94)
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#define QSERDES_COM_PLLLOCK_CMP3 COM_OFF(0x98)
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#define QSERDES_COM_PLLLOCK_CMP_EN COM_OFF(0x9C)
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#define QSERDES_COM_BGTC COM_OFF(0xA0)
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#define QSERDES_COM_DEC_START1 COM_OFF(0xAC)
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#define QSERDES_COM_PLL_AMP_OS COM_OFF(0xB0)
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#define QSERDES_COM_RES_CODE_UP_OFFSET COM_OFF(0xD8)
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#define QSERDES_COM_RES_CODE_DN_OFFSET COM_OFF(0xDC)
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#define QSERDES_COM_DIV_FRAC_START1 COM_OFF(0x100)
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#define QSERDES_COM_DIV_FRAC_START2 COM_OFF(0x104)
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#define QSERDES_COM_DIV_FRAC_START3 COM_OFF(0x108)
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#define QSERDES_COM_DEC_START2 COM_OFF(0x10C)
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#define QSERDES_COM_PLL_RXTXEPCLK_EN COM_OFF(0x110)
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#define QSERDES_COM_PLL_CRCTRL COM_OFF(0x114)
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#define QSERDES_COM_PLL_CLKEPDIV COM_OFF(0x118)
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/* TX LANE n (0, 1) registers */
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#define QSERDES_TX_EMP_POST1_LVL(n) TX_OFF(n, 0x08)
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#define QSERDES_TX_DRV_LVL(n) TX_OFF(n, 0x0C)
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#define QSERDES_TX_LANE_MODE(n) TX_OFF(n, 0x54)
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/* RX LANE n (0, 1) registers */
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#define QSERDES_RX_CDR_CONTROL1(n) RX_OFF(n, 0x0)
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#define QSERDES_RX_CDR_CONTROL_HALF(n) RX_OFF(n, 0x8)
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#define QSERDES_RX_RX_EQ_GAIN1_LSB(n) RX_OFF(n, 0xA8)
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#define QSERDES_RX_RX_EQ_GAIN1_MSB(n) RX_OFF(n, 0xAC)
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#define QSERDES_RX_RX_EQ_GAIN2_LSB(n) RX_OFF(n, 0xB0)
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#define QSERDES_RX_RX_EQ_GAIN2_MSB(n) RX_OFF(n, 0xB4)
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#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(n) RX_OFF(n, 0xBC)
|
||||
#define QSERDES_RX_CDR_CONTROL_QUARTER(n) RX_OFF(n, 0xC)
|
||||
#define QSERDES_RX_SIGDET_CNTRL(n) RX_OFF(n, 0x100)
|
||||
|
||||
/* UFS PHY registers */
|
||||
#define UFS_PHY_PHY_START PHY_OFF(0x00)
|
||||
#define UFS_PHY_POWER_DOWN_CONTROL PHY_OFF(0x4)
|
||||
#define UFS_PHY_TX_LANE_ENABLE PHY_OFF(0x44)
|
||||
#define UFS_PHY_PWM_G1_CLK_DIVIDER PHY_OFF(0x08)
|
||||
#define UFS_PHY_PWM_G2_CLK_DIVIDER PHY_OFF(0x0C)
|
||||
#define UFS_PHY_PWM_G3_CLK_DIVIDER PHY_OFF(0x10)
|
||||
#define UFS_PHY_PWM_G4_CLK_DIVIDER PHY_OFF(0x14)
|
||||
#define UFS_PHY_CORECLK_PWM_G1_CLK_DIVIDER PHY_OFF(0x34)
|
||||
#define UFS_PHY_CORECLK_PWM_G2_CLK_DIVIDER PHY_OFF(0x38)
|
||||
#define UFS_PHY_CORECLK_PWM_G3_CLK_DIVIDER PHY_OFF(0x3C)
|
||||
#define UFS_PHY_CORECLK_PWM_G4_CLK_DIVIDER PHY_OFF(0x40)
|
||||
#define UFS_PHY_OMC_STATUS_RDVAL PHY_OFF(0x68)
|
||||
#define UFS_PHY_LINE_RESET_TIME PHY_OFF(0x28)
|
||||
#define UFS_PHY_LINE_RESET_GRANULARITY PHY_OFF(0x2C)
|
||||
#define UFS_PHY_TSYNC_RSYNC_CNTL PHY_OFF(0x48)
|
||||
#define UFS_PHY_PLL_CNTL PHY_OFF(0x50)
|
||||
#define UFS_PHY_TX_LARGE_AMP_DRV_LVL PHY_OFF(0x54)
|
||||
#define UFS_PHY_TX_SMALL_AMP_DRV_LVL PHY_OFF(0x5C)
|
||||
#define UFS_PHY_TX_LARGE_AMP_POST_EMP_LVL PHY_OFF(0x58)
|
||||
#define UFS_PHY_TX_SMALL_AMP_POST_EMP_LVL PHY_OFF(0x60)
|
||||
#define UFS_PHY_CFG_CHANGE_CNT_VAL PHY_OFF(0x64)
|
||||
#define UFS_PHY_RX_SYNC_WAIT_TIME PHY_OFF(0x6C)
|
||||
#define UFS_PHY_TX_MIN_SLEEP_NOCONFIG_TIME_CAPABILITY PHY_OFF(0xB4)
|
||||
#define UFS_PHY_RX_MIN_SLEEP_NOCONFIG_TIME_CAPABILITY PHY_OFF(0xE0)
|
||||
#define UFS_PHY_TX_MIN_STALL_NOCONFIG_TIME_CAPABILITY PHY_OFF(0xB8)
|
||||
#define UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAPABILITY PHY_OFF(0xE4)
|
||||
#define UFS_PHY_TX_MIN_SAVE_CONFIG_TIME_CAPABILITY PHY_OFF(0xBC)
|
||||
#define UFS_PHY_RX_MIN_SAVE_CONFIG_TIME_CAPABILITY PHY_OFF(0xE8)
|
||||
#define UFS_PHY_RX_PWM_BURST_CLOSURE_LENGTH_CAPABILITY PHY_OFF(0xFC)
|
||||
#define UFS_PHY_RX_MIN_ACTIVATETIME_CAPABILITY PHY_OFF(0x100)
|
||||
#define UFS_PHY_RX_SIGDET_CTRL3 PHY_OFF(0x14c)
|
||||
#define UFS_PHY_RMMI_ATTR_CTRL PHY_OFF(0x160)
|
||||
#define UFS_PHY_RMMI_RX_CFGUPDT_L1 (1 << 7)
|
||||
#define UFS_PHY_RMMI_TX_CFGUPDT_L1 (1 << 6)
|
||||
#define UFS_PHY_RMMI_CFGWR_L1 (1 << 5)
|
||||
#define UFS_PHY_RMMI_CFGRD_L1 (1 << 4)
|
||||
#define UFS_PHY_RMMI_RX_CFGUPDT_L0 (1 << 3)
|
||||
#define UFS_PHY_RMMI_TX_CFGUPDT_L0 (1 << 2)
|
||||
#define UFS_PHY_RMMI_CFGWR_L0 (1 << 1)
|
||||
#define UFS_PHY_RMMI_CFGRD_L0 (1 << 0)
|
||||
#define UFS_PHY_RMMI_ATTRID PHY_OFF(0x164)
|
||||
#define UFS_PHY_RMMI_ATTRWRVAL PHY_OFF(0x168)
|
||||
#define UFS_PHY_RMMI_ATTRRDVAL_L0_STATUS PHY_OFF(0x16C)
|
||||
#define UFS_PHY_RMMI_ATTRRDVAL_L1_STATUS PHY_OFF(0x170)
|
||||
#define UFS_PHY_PCS_READY_STATUS PHY_OFF(0x174)
|
||||
|
||||
#define UFS_PHY_TX_LANE_ENABLE_MASK 0x3
|
||||
|
||||
/*
|
||||
* This structure represents the 20nm specific phy.
|
||||
* common_cfg MUST remain the first field in this structure
|
||||
* in case extra fields are added. This way, when calling
|
||||
* get_ufs_qcom_phy() of generic phy, we can extract the
|
||||
* common phy structure (struct ufs_qcom_phy) out of it
|
||||
* regardless of the relevant specific phy.
|
||||
*/
|
||||
struct ufs_qcom_phy_qmp_20nm {
|
||||
struct ufs_qcom_phy common_cfg;
|
||||
};
|
||||
|
||||
static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_1_2_0[] = {
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL3, 0x0D),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_VCOTAIL_EN, 0xe1),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0xcc),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL_TXBAND, 0x08),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RXTXEPCLK_EN, 0x10),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x82),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x40),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0xff),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x19),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x90),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL2, 0x03),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(0), 0xf2),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(0), 0x0c),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(0), 0x12),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(1), 0xf2),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(1), 0x0c),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(1), 0x12),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(0), 0xff),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(0), 0xff),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(0), 0xff),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(0), 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(1), 0xff),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(1), 0xff),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(1), 0xff),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(1), 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x3f),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x1b),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x0f),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x01),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_EMP_POST1_LVL(0), 0x2F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_DRV_LVL(0), 0x20),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_EMP_POST1_LVL(1), 0x2F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_DRV_LVL(1), 0x20),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(0), 0x68),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(1), 0x68),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(1), 0xdc),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(0), 0xdc),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3),
|
||||
};
|
||||
|
||||
static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_1_3_0[] = {
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL3, 0x0D),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_VCOTAIL_EN, 0xe1),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0xcc),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL_TXBAND, 0x08),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RXTXEPCLK_EN, 0x10),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x82),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x40),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0xff),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x19),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x90),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL2, 0x03),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(0), 0xf2),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(0), 0x0c),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(0), 0x12),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(1), 0xf2),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(1), 0x0c),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(1), 0x12),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(0), 0xff),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(0), 0xff),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(0), 0xff),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(0), 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(1), 0xff),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(1), 0xff),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(1), 0xff),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(1), 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x2b),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x38),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x3c),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RES_CODE_UP_OFFSET, 0x02),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RES_CODE_DN_OFFSET, 0x02),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x01),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CNTRL, 0x40),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(0), 0x68),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(1), 0x68),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(1), 0xdc),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(0), 0xdc),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3),
|
||||
};
|
||||
|
||||
static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x98),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0x65),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x1e),
|
||||
};
|
||||
|
||||
#endif
|
||||
59
include/linux/phy/phy-qcom-ufs.h
Normal file
59
include/linux/phy/phy-qcom-ufs.h
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PHY_QCOM_UFS_H_
|
||||
#define PHY_QCOM_UFS_H_
|
||||
|
||||
#include "phy.h"
|
||||
|
||||
/**
|
||||
* ufs_qcom_phy_enable_ref_clk() - Enable the phy
|
||||
* ref clock.
|
||||
* @phy: reference to a generic phy
|
||||
*
|
||||
* returns 0 for success, and non-zero for error.
|
||||
*/
|
||||
int ufs_qcom_phy_enable_ref_clk(struct phy *phy);
|
||||
|
||||
/**
|
||||
* ufs_qcom_phy_disable_ref_clk() - Disable the phy
|
||||
* ref clock.
|
||||
* @phy: reference to a generic phy.
|
||||
*/
|
||||
void ufs_qcom_phy_disable_ref_clk(struct phy *phy);
|
||||
|
||||
/**
|
||||
* ufs_qcom_phy_enable_dev_ref_clk() - Enable the device
|
||||
* ref clock.
|
||||
* @phy: reference to a generic phy.
|
||||
*/
|
||||
void ufs_qcom_phy_enable_dev_ref_clk(struct phy *phy);
|
||||
|
||||
/**
|
||||
* ufs_qcom_phy_disable_dev_ref_clk() - Disable the device
|
||||
* ref clock.
|
||||
* @phy: reference to a generic phy.
|
||||
*/
|
||||
void ufs_qcom_phy_disable_dev_ref_clk(struct phy *phy);
|
||||
|
||||
int ufs_qcom_phy_enable_iface_clk(struct phy *phy);
|
||||
void ufs_qcom_phy_disable_iface_clk(struct phy *phy);
|
||||
int ufs_qcom_phy_start_serdes(struct phy *phy);
|
||||
int ufs_qcom_phy_set_tx_lane_enable(struct phy *phy, u32 tx_lanes);
|
||||
int ufs_qcom_phy_calibrate_phy(struct phy *phy, bool is_rate_B);
|
||||
int ufs_qcom_phy_is_pcs_ready(struct phy *phy);
|
||||
void ufs_qcom_phy_save_controller_version(struct phy *phy,
|
||||
u8 major, u16 minor, u16 step);
|
||||
|
||||
#endif /* PHY_QCOM_UFS_H_ */
|
||||
Loading…
Reference in a new issue