irqchip: Prepare for local stub header removal
The IRQCHIP_DECLARE macro moved to to 'include/linux/irqchip.h', so the local irqchip.h became an empty shell, which solely includes include/linux/irqchip.h Include the global header in all irqchip drivers instead of the local header, so we can remove it. Signed-off-by: Joel Porquet <joel@porquet.org> Cc: vgupta@synopsys.com Cc: monstr@monstr.eu Cc: ralf@linux-mips.org Cc: jason@lakedaemon.net Link: http://lkml.kernel.org/r/1882096.X39jVG8e0D@joel-zenbook Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
parent
d452bca82d
commit
41a83e06e2
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@ -15,13 +15,12 @@
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#include <linux/slab.h>
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#include <linux/syscore_ops.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/interrupt.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include "irqchip.h"
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#define COMBINER_ENABLE_SET 0x0
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#define COMBINER_ENABLE_CLEAR 0x4
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#define COMBINER_INT_STATUS 0xC
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@ -18,6 +18,7 @@
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/cpu.h>
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#include <linux/io.h>
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@ -33,8 +34,6 @@
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#include <asm/smp_plat.h>
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#include <asm/mach/irq.h>
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#include "irqchip.h"
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/* Interrupt Controller Registers Map */
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#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
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#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
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@ -19,6 +19,7 @@
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#include <linux/bitmap.h>
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#include <linux/types.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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@ -31,7 +32,6 @@
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#include <asm/mach/irq.h>
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#include "irq-atmel-aic-common.h"
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#include "irqchip.h"
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/* Number of irq lines managed by AIC */
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#define NR_AIC_IRQS 32
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@ -19,6 +19,7 @@
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#include <linux/bitmap.h>
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#include <linux/types.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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@ -31,7 +32,6 @@
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#include <asm/mach/irq.h>
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#include "irq-atmel-aic-common.h"
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#include "irqchip.h"
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/* Number of irq lines managed by AIC */
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#define NR_AIC5_IRQS 128
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@ -48,13 +48,12 @@
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#include <linux/slab.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <asm/exception.h>
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#include <asm/mach/irq.h>
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#include "irqchip.h"
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/* Put the bank and irq (32 bits) into the hwirq */
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#define MAKE_HWIRQ(b, n) ((b << 5) | (n))
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#define HWIRQ_BANK(i) (i >> 5)
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@ -29,10 +29,9 @@
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#include <linux/slab.h>
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#include <linux/smp.h>
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#include <linux/types.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include "irqchip.h"
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#define IRQS_PER_WORD 32
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#define REG_BYTES_PER_IRQ_WORD (sizeof(u32) * 4)
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#define MAX_WORDS 8
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@ -26,10 +26,9 @@
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#include <linux/irqdomain.h>
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#include <linux/reboot.h>
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#include <linux/bitops.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include "irqchip.h"
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/* Register offset in the L2 interrupt controller */
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#define IRQEN 0x00
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#define IRQSTAT 0x04
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include "irqchip.h"
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/* Register offsets in the L2 interrupt controller */
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#define CPU_STATUS 0x00
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#define CPU_SET 0x04
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@ -11,6 +11,7 @@
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/exception.h>
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#include <asm/mach/irq.h>
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#include "irqchip.h"
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#define CLPS711X_INTSR1 (0x0240)
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#define CLPS711X_INTMR1 (0x0280)
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#define CLPS711X_BLEOI (0x0600)
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@ -11,13 +11,12 @@
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/slab.h>
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#include "irqchip.h"
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#define IRQ_FREE -1
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#define IRQ_RESERVED -2
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#define IRQ_SKIP -3
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@ -12,6 +12,7 @@
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/exception.h>
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#include "irqchip.h"
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#define UC_IRQ_CONTROL 0x04
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#define IC_FLAG_CLEAR_LO 0x00
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include "irqchip.h"
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#define APB_INT_ENABLE_L 0x00
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#define APB_INT_ENABLE_H 0x04
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#define APB_INT_MASK_L 0x08
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#include <linux/percpu.h>
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#include <linux/slab.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/arm-gic-v3.h>
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#include <asm/cacheflush.h>
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#include <asm/cputype.h>
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#include <asm/exception.h>
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#include "irqchip.h"
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#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1 << 0)
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#define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
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#include <linux/percpu.h>
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#include <linux/slab.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/arm-gic-v3.h>
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#include <asm/cputype.h>
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#include <asm/smp_plat.h>
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#include "irq-gic-common.h"
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#include "irqchip.h"
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struct redist_region {
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void __iomem *redist_base;
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#include <linux/interrupt.h>
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#include <linux/percpu.h>
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#include <linux/slab.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/irqchip/arm-gic-acpi.h>
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#include <asm/smp_plat.h>
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#include "irq-gic-common.h"
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#include "irqchip.h"
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union gic_base {
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void __iomem *common_base;
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#include <linux/irqdomain.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/irq.h>
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#include <asm/smp_plat.h>
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#include "irq-gic-common.h"
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#include "irqchip.h"
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#define HIP04_MAX_IRQS 510
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/ingenic.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/io.h>
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#include <asm/mach-jz4740/irq.h>
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#include "irqchip.h"
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struct ingenic_intc_data {
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void __iomem *base;
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unsigned num_chips;
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include "irqchip.h"
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/* The source ID bits start from 4 to 31 (total 28 bits)*/
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#define BIT_OFS 4
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsmtregs.h>
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#include <asm/setup.h>
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#include "irqchip.h"
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static inline void unmask_mips_irq(struct irq_data *d)
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{
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set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/mips-gic.h>
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#include <linux/of_address.h>
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#include <linux/sched.h>
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#include <dt-bindings/interrupt-controller/mips-gic.h>
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#include "irqchip.h"
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unsigned int gic_present;
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struct gic_pcpu_mask {
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <asm/exception.h>
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#include <asm/hardirq.h>
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#include "irqchip.h"
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#define MAX_ICU_NR 16
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#define PJ1_INT_SEL 0x10c
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/exception.h>
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#include "irqchip.h"
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#define IRQ_SOURCE_REG 0
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#define IRQ_MASK_REG 0x04
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#define IRQ_CLEAR_REG 0x08
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*/
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include "irqchip.h"
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struct mtk_sysirq_chip_data {
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spinlock_t lock;
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void __iomem *intpol_base;
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/stmp_device.h>
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#include <asm/exception.h>
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#include "irqchip.h"
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#define HW_ICOLL_VECTOR 0x0000
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#define HW_ICOLL_LEVELACK 0x0010
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#define HW_ICOLL_CTRL 0x0020
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <asm/v7m.h>
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#include <asm/exception.h>
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#include "irqchip.h"
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#define NVIC_ISER 0x000
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#define NVIC_ICER 0x080
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#define NVIC_IPR 0x300
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#include <linux/io.h>
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#include <asm/exception.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include "irqchip.h"
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/* Define these here for now until we drop all board-files */
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#define OMAP24XX_IC_BASE 0x480fe000
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#define OMAP34XX_IC_BASE 0x48200000
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*/
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include "irqchip.h"
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/* OR1K PIC implementation */
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struct or1k_pic_dev {
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/exception.h>
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#include <asm/mach/irq.h>
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#include "irqchip.h"
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/*
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* Orion SoC main interrupt controller
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*/
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#include <linux/of_irq.h>
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#include <asm/io.h>
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#include "irqchip.h"
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static const char ipr_bit[] = {
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7, 6, 5, 5,
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4, 4, 4, 4, 3, 3, 3, 3,
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*/
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/io.h>
|
||||
#include "irqchip.h"
|
||||
|
||||
static void *intc_baseaddr;
|
||||
#define IPRA ((unsigned long)intc_baseaddr)
|
||||
|
|
|
@ -25,6 +25,7 @@
|
|||
#include <linux/ioport.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_irq.h>
|
||||
|
@ -40,8 +41,6 @@
|
|||
#include <plat/regs-irqtype.h>
|
||||
#include <plat/pm.h>
|
||||
|
||||
#include "irqchip.h"
|
||||
|
||||
#define S3C_IRQTYPE_NONE 0
|
||||
#define S3C_IRQTYPE_EINT 1
|
||||
#define S3C_IRQTYPE_EDGE 2
|
||||
|
|
|
@ -11,11 +11,11 @@
|
|||
#include <linux/irq.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/exception.h>
|
||||
#include "irqchip.h"
|
||||
|
||||
#define SIRFSOC_INT_RISC_MASK0 0x0018
|
||||
#define SIRFSOC_INT_RISC_MASK1 0x001C
|
||||
|
|
|
@ -16,6 +16,7 @@
|
|||
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
|
@ -23,8 +24,6 @@
|
|||
#include <asm/exception.h>
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#include "irqchip.h"
|
||||
|
||||
#define SUN4I_IRQ_VECTOR_REG 0x00
|
||||
#define SUN4I_IRQ_PROTECTION_REG 0x08
|
||||
#define SUN4I_IRQ_NMI_CTRL_REG 0x0c
|
||||
|
|
|
@ -17,8 +17,8 @@
|
|||
#include <linux/of_irq.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
#include "irqchip.h"
|
||||
|
||||
#define SUNXI_NMI_SRC_TYPE_MASK 0x00000003
|
||||
|
||||
|
|
|
@ -22,13 +22,13 @@
|
|||
#include <linux/interrupt.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/bitops.h>
|
||||
#include "irqchip.h"
|
||||
|
||||
#define AB_IRQCTL_INT_ENABLE 0x00
|
||||
#define AB_IRQCTL_INT_STATUS 0x04
|
||||
|
|
|
@ -24,6 +24,7 @@
|
|||
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/slab.h>
|
||||
|
@ -31,8 +32,6 @@
|
|||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "irqchip.h"
|
||||
|
||||
#define ICTLR_CPU_IEP_VFIQ 0x08
|
||||
#define ICTLR_CPU_IEP_FIR 0x14
|
||||
#define ICTLR_CPU_IEP_FIR_SET 0x18
|
||||
|
|
|
@ -4,6 +4,7 @@
|
|||
#include <linux/bitops.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/irqchip/versatile-fpga.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/module.h>
|
||||
|
@ -14,8 +15,6 @@
|
|||
#include <asm/exception.h>
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#include "irqchip.h"
|
||||
|
||||
#define IRQ_STATUS 0x00
|
||||
#define IRQ_RAW_STATUS 0x04
|
||||
#define IRQ_ENABLE_SET 0x08
|
||||
|
|
|
@ -26,6 +26,7 @@
|
|||
#include <linux/cpu_pm.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
@ -34,8 +35,6 @@
|
|||
#include <linux/slab.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include "irqchip.h"
|
||||
|
||||
#define MSCM_CPxNUM 0x4
|
||||
|
||||
#define MSCM_IRSPRC(n) (0x80 + 2 * (n))
|
||||
|
|
|
@ -24,6 +24,7 @@
|
|||
#include <linux/list.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/of.h>
|
||||
|
@ -37,8 +38,6 @@
|
|||
#include <asm/exception.h>
|
||||
#include <asm/irq.h>
|
||||
|
||||
#include "irqchip.h"
|
||||
|
||||
#define VIC_IRQ_STATUS 0x00
|
||||
#define VIC_FIQ_STATUS 0x04
|
||||
#define VIC_INT_SELECT 0x0c /* 1 = FIQ, 0 = IRQ */
|
||||
|
|
|
@ -27,6 +27,7 @@
|
|||
#include <linux/slab.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/bitops.h>
|
||||
|
@ -39,8 +40,6 @@
|
|||
#include <asm/exception.h>
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#include "irqchip.h"
|
||||
|
||||
#define VT8500_ICPC_IRQ 0x20
|
||||
#define VT8500_ICPC_FIQ 0x24
|
||||
#define VT8500_ICDC 0x40 /* Destination Control 64*u32 */
|
||||
|
|
|
@ -11,12 +11,11 @@
|
|||
#include <linux/interrupt.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#include <asm/mxregs.h>
|
||||
|
||||
#include "irqchip.h"
|
||||
|
||||
#define HW_IRQ_IPI_COUNT 2
|
||||
#define HW_IRQ_MX_BASE 2
|
||||
#define HW_IRQ_EXTERN_BASE 3
|
||||
|
|
|
@ -15,10 +15,9 @@
|
|||
#include <linux/interrupt.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#include "irqchip.h"
|
||||
|
||||
unsigned int cached_irq_mask;
|
||||
|
||||
/*
|
||||
|
|
|
@ -11,6 +11,7 @@
|
|||
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
|
@ -18,8 +19,6 @@
|
|||
#include <asm/mach/irq.h>
|
||||
#include <asm/exception.h>
|
||||
|
||||
#include "irqchip.h"
|
||||
|
||||
#define IO_STATUS 0x000
|
||||
#define IO_RAW_STATUS 0x004
|
||||
#define IO_ENABLE 0x008
|
||||
|
|
|
@ -18,14 +18,13 @@
|
|||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#include "irqchip.h"
|
||||
|
||||
/*
|
||||
* struct spear_shirq: shared irq structure
|
||||
*
|
||||
|
|
Loading…
Reference in a new issue