pci-v4.19-fixes-1
-----BEGIN PGP SIGNATURE----- iQJIBAABCgAyFiEEgMe7l+5h9hnxdsnuWYigwDrT+vwFAluZ1pkUHGJoZWxnYWFz QGdvb2dsZS5jb20ACgkQWYigwDrT+vxllw//R9UVckBvd7AUseb/8EMUt3GIqvhy xy9thJy9cygQF+6Ti9K9TA4aTTriyW7Ur4/lvlSnciffYiZhydaR6MJEgO9+C3wa v/Ev9dUHYANVT8z3Q7KVwu1KaNXcb3RBIs0rg0BAqJUzhMNZo4i5NJzxTC5DvnzB P8brxz8Oa+IiAdBkJyDDuJ7QK+yIiApcbYWdcnAEwuSxTh3vBSEFjr9hks6TPZUd Vp5k2kYOdaslBBKg2yRqK3NcUaWNVpoqXJkVnFpfd6OA3aDPQ79t20se5lkMbpK+ CbbXWgE2LXnh0wfTDx1nexD9/PbkGHO+NxKX0LRHnedBbWGlOoQVoaXIe/7x79cX EWyDG+r0SC5QD5Paj/OtD+Is98PsP5AUiddxnZRUnyIZlJHe9Ja8vV0SuAus8Pjt E5AarnLVLrCZGU3XIqj4vy1Kh12TZp2ZaBdFnNkdW+cL7XcRHm9wTEtn4COJKKy5 MvW2VnEMbIy+JmXZ16R67Ggc9/yU6W/qjzauw0+BkdJSHnrKWRDkfVcuSYf7LquD INcTpRekBEPyrgsc5IRvJc+UE7AXUYPpkJ6VkNNwXuB+AVB/3s7LjTEoboWYEp1Y QSC4BYClEaUVStgQQ7mTRzvIacIIoYQcEhTJOLVZ2R2o4bWJxZ8Aio2sT2MssZfL S6/6csccKXNLS+E= =oXm8 -----END PGP SIGNATURE----- Merge tag 'pci-v4.19-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI fixes from Bjorn Helgaas: - Add Tyrel Datwyler as maintainer for PPC64 RPA hotplug (Tyrel Datwyler) - Add Gustavo Pimentel as DesignWare PCI maintainer (Joao Pinto) - Fix a Switchtec Spectre v1 vulnerability (Gustavo A. R. Silva) - Revert an unnecessary Intel 300 ACS quirk (Mika Westerberg) - Fix pciehp hot-add/powerfault detection that left indicators in wrong state (Keith Busch) - Fix pci_reset_bus() logic error (Dennis Dalessandro) - Revert IB/hfi1 PCI reset change that caused a deadlock (Dennis Dalessandro) - Allow enabling PASID on Root Complex Integrated Endpoints (Felix Kuehling) * tag 'pci-v4.19-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: PCI: Fix enabling of PASID on RC integrated endpoints IB/hfi1,PCI: Allow bus reset while probing PCI: Fix faulty logic in pci_reset_bus() PCI: pciehp: Fix hot-add vs powerfault detection order switchtec: Fix Spectre v1 vulnerability Revert "PCI: Add ACS quirk for Intel 300 series" MAINTAINERS: Add Gustavo Pimentel as DesignWare PCI maintainer MAINTAINERS: Add entries for PPC64 RPA PCI hotplug drivers
This commit is contained in:
commit
54eda9df17
16
MAINTAINERS
16
MAINTAINERS
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@ -7016,6 +7016,20 @@ F: drivers/crypto/vmx/aes*
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F: drivers/crypto/vmx/ghash*
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F: drivers/crypto/vmx/ppc-xlate.pl
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IBM Power PCI Hotplug Driver for RPA-compliant PPC64 platform
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M: Tyrel Datwyler <tyreld@linux.vnet.ibm.com>
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L: linux-pci@vger.kernel.org
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L: linuxppc-dev@lists.ozlabs.org
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S: Supported
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F: drivers/pci/hotplug/rpaphp*
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IBM Power IO DLPAR Driver for RPA-compliant PPC64 platform
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M: Tyrel Datwyler <tyreld@linux.vnet.ibm.com>
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L: linux-pci@vger.kernel.org
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L: linuxppc-dev@lists.ozlabs.org
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S: Supported
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F: drivers/pci/hotplug/rpadlpar*
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IBM ServeRAID RAID DRIVER
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S: Orphan
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F: drivers/scsi/ips.*
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@ -11154,7 +11168,7 @@ F: drivers/pci/controller/dwc/pci-exynos.c
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PCI DRIVER FOR SYNOPSYS DESIGNWARE
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M: Jingoo Han <jingoohan1@gmail.com>
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M: Joao Pinto <Joao.Pinto@synopsys.com>
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M: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
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L: linux-pci@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/pci/designware-pcie.txt
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@ -893,14 +893,11 @@ static int trigger_sbr(struct hfi1_devdata *dd)
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}
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/*
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* A secondary bus reset (SBR) issues a hot reset to our device.
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* The following routine does a 1s wait after the reset is dropped
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* per PCI Trhfa (recovery time). PCIe 3.0 section 6.6.1 -
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* Conventional Reset, paragraph 3, line 35 also says that a 1s
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* delay after a reset is required. Per spec requirements,
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* the link is either working or not after that point.
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* This is an end around to do an SBR during probe time. A new API needs
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* to be implemented to have cleaner interface but this fixes the
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* current brokenness
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*/
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return pci_reset_bus(dev);
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return pci_bridge_secondary_bus_reset(dev->bus->self);
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}
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/*
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@ -496,7 +496,7 @@ int pciehp_power_on_slot(struct slot *slot)
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u16 slot_status;
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int retval;
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/* Clear sticky power-fault bit from previous power failures */
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/* Clear power-fault bit from previous power failures */
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pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
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if (slot_status & PCI_EXP_SLTSTA_PFD)
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pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
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@ -646,6 +646,14 @@ static irqreturn_t pciehp_ist(int irq, void *dev_id)
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pciehp_handle_button_press(slot);
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}
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/* Check Power Fault Detected */
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if ((events & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
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ctrl->power_fault_detected = 1;
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ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(slot));
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pciehp_set_attention_status(slot, 1);
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pciehp_green_led_off(slot);
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}
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/*
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* Disable requests have higher priority than Presence Detect Changed
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* or Data Link Layer State Changed events.
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@ -657,14 +665,6 @@ static irqreturn_t pciehp_ist(int irq, void *dev_id)
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pciehp_handle_presence_or_link_change(slot, events);
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up_read(&ctrl->reset_lock);
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/* Check Power Fault Detected */
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if ((events & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
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ctrl->power_fault_detected = 1;
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ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(slot));
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pciehp_set_attention_status(slot, 1);
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pciehp_green_led_off(slot);
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}
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pci_config_pm_runtime_put(pdev);
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wake_up(&ctrl->requester);
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return IRQ_HANDLED;
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@ -4547,6 +4547,7 @@ int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
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return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);
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}
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EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);
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static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
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{
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@ -5200,7 +5201,7 @@ static int __pci_reset_bus(struct pci_bus *bus)
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*/
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int pci_reset_bus(struct pci_dev *pdev)
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{
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return pci_probe_reset_slot(pdev->slot) ?
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return (!pci_probe_reset_slot(pdev->slot)) ?
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__pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus);
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}
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EXPORT_SYMBOL_GPL(pci_reset_bus);
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@ -2074,6 +2074,7 @@ static void pci_configure_eetlp_prefix(struct pci_dev *dev)
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{
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#ifdef CONFIG_PCI_PASID
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struct pci_dev *bridge;
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int pcie_type;
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u32 cap;
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if (!pci_is_pcie(dev))
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@ -2083,7 +2084,9 @@ static void pci_configure_eetlp_prefix(struct pci_dev *dev)
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if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))
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return;
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if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
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pcie_type = pci_pcie_type(dev);
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if (pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
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pcie_type == PCI_EXP_TYPE_RC_END)
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dev->eetlp_prefix_path = 1;
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else {
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bridge = pci_upstream_bridge(dev);
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@ -4355,11 +4355,6 @@ static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
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*
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* 0x9d10-0x9d1b PCI Express Root port #{1-12}
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*
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* The 300 series chipset suffers from the same bug so include those root
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* ports here as well.
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*
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* 0xa32c-0xa343 PCI Express Root port #{0-24}
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*
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* [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
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* [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
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* [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
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@ -4377,7 +4372,6 @@ static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
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case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
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case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
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case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
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case 0xa32c ... 0xa343: /* 300 series */
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return true;
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}
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@ -14,6 +14,8 @@
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#include <linux/poll.h>
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#include <linux/wait.h>
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#include <linux/nospec.h>
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MODULE_DESCRIPTION("Microsemi Switchtec(tm) PCIe Management Driver");
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MODULE_VERSION("0.1");
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MODULE_LICENSE("GPL");
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default:
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if (p.port > ARRAY_SIZE(pcfg->dsp_pff_inst_id))
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return -EINVAL;
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p.port = array_index_nospec(p.port,
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ARRAY_SIZE(pcfg->dsp_pff_inst_id) + 1);
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p.pff = ioread32(&pcfg->dsp_pff_inst_id[p.port - 1]);
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break;
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}
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int devm_request_pci_bus_resources(struct device *dev,
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struct list_head *resources);
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/* Temporary until new and working PCI SBR API in place */
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int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
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#define pci_bus_for_each_resource(bus, res, i) \
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for (i = 0; \
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(res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
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