SOC: TI Keystone Ring Accelerator driver
The Ring Accelerator (RINGACC or RA) provides hardware acceleration to enable straightforward passing of work between a producer and a consumer. There is one RINGACC module per NAVSS on TI AM65x SoCs. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJeH1VYAAoJEHJsHOdBp5c/k4cP/RHrk67mB8L6JC7G9H1XWedM w4aG80q7u8dAydk9k3wJM1Y4ChXfflR3JYc5KBghrsQiRPF8myh4JEwi3+8jpTT5 LUOJifaEtR79VuNCHyG9Wgni3LWYnp7HmG4jM1bzcDwLgpf4I8cBwXkCfW0kmyPq HAaFLWo1net3TkhSnUkbFUn54vESl569/D6FIfFFK2DPJH/gLUKQ6W8Xnd1uKBaI 9RpnN6eGA0ZWZkZG+Xu7XA/VfC/AR+wxbCr0l1jHB9+4CrngOEwsTnP1SFxFsD1v L7zAT5JguNg13jbELVgTpUX8X5/XBfbOzIrNZpeXnl0fl8p2SU25n8hw8KdYjKCP 5puO6wye5NnliQs5hLlMTydF77VazAqdBhLz5i1OMa+cuA1zVzm7dyIZBAWbI8IC TY86h9eGyGKELjljrYhW8ijARbzu/J3SpO3cSklvL/BfXtlVYen5d0mZxsKBDWOi bni1yV37b65IWjkimwzkaVq/sN9jWTAF2a192SkKeEBqnms5jxKDeCRq9qSxpCWv ONFROd6WXImDTk/MLgo4EdAq+ProoBFR+YDLModSAv3fZaBFUgi5mU5Xnx1+cAFq SL9TguzvXhUv6o6ywNZSsSM/7I2iB5uOMRKjCeGg2x1JN9lyOMzrVlJ8JzzUyKV3 iiKDJjNdZD0/Rn2fl5a1 =m1rI -----END PGP SIGNATURE----- Merge TI ringacc driver from Santosh This is for dependency of new TI ringacc dmaengine drivers Merge tag 'drivers_soc_for_5.6' into topic/ti SOC: TI Keystone Ring Accelerator driver The Ring Accelerator (RINGACC or RA) provides hardware acceleration to enable straightforward passing of work between a producer and a consumer. There is one RINGACC module per NAVSS on TI AM65x SoCs. Signed-off-by: Vinod Koul <vkoul@kernel.org>5.9.x+fslc
Vinod Koul
commit
5fe4beaac2
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@ -0,0 +1,59 @@
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* Texas Instruments K3 NavigatorSS Ring Accelerator
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The Ring Accelerator (RA) is a machine which converts read/write accesses
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from/to a constant address into corresponding read/write accesses from/to a
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circular data structure in memory. The RA eliminates the need for each DMA
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controller which needs to access ring elements from having to know the current
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state of the ring (base address, current offset). The DMA controller
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performs a read or write access to a specific address range (which maps to the
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source interface on the RA) and the RA replaces the address for the transaction
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with a new address which corresponds to the head or tail element of the ring
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(head for reads, tail for writes).
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The Ring Accelerator is a hardware module that is responsible for accelerating
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management of the packet queues. The K3 SoCs can have more than one RA instances
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Required properties:
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- compatible : Must be "ti,am654-navss-ringacc";
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- reg : Should contain register location and length of the following
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named register regions.
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- reg-names : should be
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"rt" - The RA Ring Real-time Control/Status Registers
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"fifos" - The RA Queues Registers
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"proxy_gcfg" - The RA Proxy Global Config Registers
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"proxy_target" - The RA Proxy Datapath Registers
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- ti,num-rings : Number of rings supported by RA
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- ti,sci-rm-range-gp-rings : TI-SCI RM subtype for GP ring range
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- ti,sci : phandle on TI-SCI compatible System controller node
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- ti,sci-dev-id : TI-SCI device id of the ring accelerator
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- msi-parent : phandle for "ti,sci-inta" interrupt controller
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Optional properties:
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-- ti,dma-ring-reset-quirk : enable ringacc / udma ring state interoperability
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issue software w/a
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Example:
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ringacc: ringacc@3c000000 {
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compatible = "ti,am654-navss-ringacc";
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reg = <0x0 0x3c000000 0x0 0x400000>,
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<0x0 0x38000000 0x0 0x400000>,
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<0x0 0x31120000 0x0 0x100>,
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<0x0 0x33000000 0x0 0x40000>;
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reg-names = "rt", "fifos",
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"proxy_gcfg", "proxy_target";
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ti,num-rings = <818>;
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ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
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ti,dma-ring-reset-quirk;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <187>;
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msi-parent = <&inta_main_udmass>;
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};
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client:
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dma_ipx: dma_ipx@<addr> {
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...
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ti,ringacc = <&ringacc>;
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...
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}
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@ -80,6 +80,17 @@ config TI_SCI_PM_DOMAINS
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called ti_sci_pm_domains. Note this is needed early in boot before
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rootfs may be available.
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config TI_K3_RINGACC
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bool "K3 Ring accelerator Sub System"
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depends on ARCH_K3 || COMPILE_TEST
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depends on TI_SCI_INTA_IRQCHIP
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help
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Say y here to support the K3 Ring accelerator module.
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The Ring Accelerator (RINGACC or RA) provides hardware acceleration
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to enable straightforward passing of work between a producer
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and a consumer. There is one RINGACC module per NAVSS on TI AM65x SoCs
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If unsure, say N.
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endif # SOC_TI
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config TI_SCI_INTA_MSI_DOMAIN
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@ -10,3 +10,4 @@ obj-$(CONFIG_ARCH_OMAP2PLUS) += omap_prm.o
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obj-$(CONFIG_WKUP_M3_IPC) += wkup_m3_ipc.o
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obj-$(CONFIG_TI_SCI_PM_DOMAINS) += ti_sci_pm_domains.o
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obj-$(CONFIG_TI_SCI_INTA_MSI_DOMAIN) += ti_sci_inta_msi.o
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obj-$(CONFIG_TI_K3_RINGACC) += k3-ringacc.o
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File diff suppressed because it is too large
Load Diff
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* K3 Ring Accelerator (RA) subsystem interface
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*
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* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
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*/
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#ifndef __SOC_TI_K3_RINGACC_API_H_
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#define __SOC_TI_K3_RINGACC_API_H_
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#include <linux/types.h>
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struct device_node;
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/**
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* enum k3_ring_mode - &struct k3_ring_cfg mode
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*
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* RA ring operational modes
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*
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* @K3_RINGACC_RING_MODE_RING: Exposed Ring mode for SW direct access
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* @K3_RINGACC_RING_MODE_MESSAGE: Messaging mode. Messaging mode requires
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* that all accesses to the queue must go through this IP so that all
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* accesses to the memory are controlled and ordered. This IP then
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* controls the entire state of the queue, and SW has no directly control,
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* such as through doorbells and cannot access the storage memory directly.
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* This is particularly useful when more than one SW or HW entity can be
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* the producer and/or consumer at the same time
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* @K3_RINGACC_RING_MODE_CREDENTIALS: Credentials mode is message mode plus
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* stores credentials with each message, requiring the element size to be
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* doubled to fit the credentials. Any exposed memory should be protected
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* by a firewall from unwanted access
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*/
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enum k3_ring_mode {
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K3_RINGACC_RING_MODE_RING = 0,
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K3_RINGACC_RING_MODE_MESSAGE,
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K3_RINGACC_RING_MODE_CREDENTIALS,
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K3_RINGACC_RING_MODE_INVALID
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};
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/**
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* enum k3_ring_size - &struct k3_ring_cfg elm_size
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*
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* RA ring element's sizes in bytes.
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*/
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enum k3_ring_size {
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K3_RINGACC_RING_ELSIZE_4 = 0,
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K3_RINGACC_RING_ELSIZE_8,
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K3_RINGACC_RING_ELSIZE_16,
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K3_RINGACC_RING_ELSIZE_32,
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K3_RINGACC_RING_ELSIZE_64,
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K3_RINGACC_RING_ELSIZE_128,
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K3_RINGACC_RING_ELSIZE_256,
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K3_RINGACC_RING_ELSIZE_INVALID
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};
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struct k3_ringacc;
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struct k3_ring;
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/**
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* enum k3_ring_cfg - RA ring configuration structure
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*
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* @size: Ring size, number of elements
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* @elm_size: Ring element size
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* @mode: Ring operational mode
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* @flags: Ring configuration flags. Possible values:
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* @K3_RINGACC_RING_SHARED: when set allows to request the same ring
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* few times. It's usable when the same ring is used as Free Host PD ring
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* for different flows, for example.
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* Note: Locking should be done by consumer if required
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*/
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struct k3_ring_cfg {
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u32 size;
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enum k3_ring_size elm_size;
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enum k3_ring_mode mode;
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#define K3_RINGACC_RING_SHARED BIT(1)
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u32 flags;
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};
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#define K3_RINGACC_RING_ID_ANY (-1)
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/**
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* of_k3_ringacc_get_by_phandle - find a RA by phandle property
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* @np: device node
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* @propname: property name containing phandle on RA node
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*
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* Returns pointer on the RA - struct k3_ringacc
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* or -ENODEV if not found,
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* or -EPROBE_DEFER if not yet registered
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*/
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struct k3_ringacc *of_k3_ringacc_get_by_phandle(struct device_node *np,
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const char *property);
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#define K3_RINGACC_RING_USE_PROXY BIT(1)
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/**
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* k3_ringacc_request_ring - request ring from ringacc
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* @ringacc: pointer on ringacc
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* @id: ring id or K3_RINGACC_RING_ID_ANY for any general purpose ring
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* @flags:
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* @K3_RINGACC_RING_USE_PROXY: if set - proxy will be allocated and
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* used to access ring memory. Sopported only for rings in
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* Message/Credentials/Queue mode.
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*
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* Returns pointer on the Ring - struct k3_ring
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* or NULL in case of failure.
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*/
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struct k3_ring *k3_ringacc_request_ring(struct k3_ringacc *ringacc,
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int id, u32 flags);
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/**
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* k3_ringacc_ring_reset - ring reset
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* @ring: pointer on Ring
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*
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* Resets ring internal state ((hw)occ, (hw)idx).
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*/
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void k3_ringacc_ring_reset(struct k3_ring *ring);
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/**
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* k3_ringacc_ring_reset - ring reset for DMA rings
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* @ring: pointer on Ring
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*
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* Resets ring internal state ((hw)occ, (hw)idx). Should be used for rings
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* which are read by K3 UDMA, like TX or Free Host PD rings.
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*/
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void k3_ringacc_ring_reset_dma(struct k3_ring *ring, u32 occ);
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/**
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* k3_ringacc_ring_free - ring free
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* @ring: pointer on Ring
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*
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* Resets ring and free all alocated resources.
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*/
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int k3_ringacc_ring_free(struct k3_ring *ring);
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/**
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* k3_ringacc_get_ring_id - Get the Ring ID
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* @ring: pointer on ring
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*
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* Returns the Ring ID
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*/
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u32 k3_ringacc_get_ring_id(struct k3_ring *ring);
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/**
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* k3_ringacc_get_ring_irq_num - Get the irq number for the ring
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* @ring: pointer on ring
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*
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* Returns the interrupt number which can be used to request the interrupt
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*/
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int k3_ringacc_get_ring_irq_num(struct k3_ring *ring);
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/**
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* k3_ringacc_ring_cfg - ring configure
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* @ring: pointer on ring
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* @cfg: Ring configuration parameters (see &struct k3_ring_cfg)
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*
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* Configures ring, including ring memory allocation.
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* Returns 0 on success, errno otherwise.
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*/
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int k3_ringacc_ring_cfg(struct k3_ring *ring, struct k3_ring_cfg *cfg);
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/**
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* k3_ringacc_ring_get_size - get ring size
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* @ring: pointer on ring
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*
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* Returns ring size in number of elements.
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*/
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u32 k3_ringacc_ring_get_size(struct k3_ring *ring);
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/**
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* k3_ringacc_ring_get_free - get free elements
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* @ring: pointer on ring
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*
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* Returns number of free elements in the ring.
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*/
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u32 k3_ringacc_ring_get_free(struct k3_ring *ring);
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/**
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* k3_ringacc_ring_get_occ - get ring occupancy
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* @ring: pointer on ring
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*
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* Returns total number of valid entries on the ring
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*/
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u32 k3_ringacc_ring_get_occ(struct k3_ring *ring);
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/**
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* k3_ringacc_ring_is_full - checks if ring is full
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* @ring: pointer on ring
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*
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* Returns true if the ring is full
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*/
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u32 k3_ringacc_ring_is_full(struct k3_ring *ring);
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/**
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* k3_ringacc_ring_push - push element to the ring tail
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* @ring: pointer on ring
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* @elem: pointer on ring element buffer
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*
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* Push one ring element to the ring tail. Size of the ring element is
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* determined by ring configuration &struct k3_ring_cfg elm_size.
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*
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* Returns 0 on success, errno otherwise.
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*/
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int k3_ringacc_ring_push(struct k3_ring *ring, void *elem);
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/**
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* k3_ringacc_ring_pop - pop element from the ring head
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* @ring: pointer on ring
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* @elem: pointer on ring element buffer
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*
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* Push one ring element from the ring head. Size of the ring element is
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* determined by ring configuration &struct k3_ring_cfg elm_size..
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*
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* Returns 0 on success, errno otherwise.
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*/
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int k3_ringacc_ring_pop(struct k3_ring *ring, void *elem);
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/**
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* k3_ringacc_ring_push_head - push element to the ring head
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* @ring: pointer on ring
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* @elem: pointer on ring element buffer
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*
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* Push one ring element to the ring head. Size of the ring element is
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* determined by ring configuration &struct k3_ring_cfg elm_size.
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*
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* Returns 0 on success, errno otherwise.
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* Not Supported by ring modes: K3_RINGACC_RING_MODE_RING
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*/
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int k3_ringacc_ring_push_head(struct k3_ring *ring, void *elem);
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/**
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* k3_ringacc_ring_pop_tail - pop element from the ring tail
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* @ring: pointer on ring
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* @elem: pointer on ring element buffer
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*
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* Push one ring element from the ring tail. Size of the ring element is
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* determined by ring configuration &struct k3_ring_cfg elm_size.
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*
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* Returns 0 on success, errno otherwise.
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* Not Supported by ring modes: K3_RINGACC_RING_MODE_RING
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*/
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int k3_ringacc_ring_pop_tail(struct k3_ring *ring, void *elem);
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u32 k3_ringacc_get_tisci_dev_id(struct k3_ring *ring);
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#endif /* __SOC_TI_K3_RINGACC_API_H_ */
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