Merge branch 'irq-irqdomain-arm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq domain ARM updates from Thomas Gleixner: "This set of changes make use of hierarchical irqdomains to provide: - MSI/ITS support for GICv3 - MSI support for GICv2m - Interrupt polarity extender for GICv1 Marc has come more cleanups for the existing extension hooks of GIC in the pipeline, but they are going to be 3.20 material" * 'irq-irqdomain-arm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (22 commits) irqchip: gicv3-its: Fix ITT allocation irqchip: gicv3-its: Move some alloc/free code to activate/deactivate irqchip: gicv3-its: Fix domain free in multi-MSI case irqchip: gic: Remove warning by including linux/irqdomain.h irqchip: gic-v2m: Add DT bindings for GICv2m irqchip: gic-v2m: Add support for ARM GICv2m MSI(-X) doorbell irqchip: mtk-sysirq: dt-bindings: Add bindings for mediatek sysirq irqchip: mtk-sysirq: Add sysirq interrupt polarity support irqchip: gic: Support hierarchy irq domain. irqchip: GICv3: Binding updates for ITS irqchip: GICv3: ITS: enable compilation of the ITS driver irqchip: GICv3: ITS: plug ITS init into main GICv3 code irqchip: GICv3: ITS: DT probing and initialization irqchip: GICv3: ITS: MSI support irqchip: GICv3: ITS: device allocation and configuration irqchip: GICv3: ITS: tables allocators irqchip: GICv3: ITS: LPI allocator irqchip: GICv3: ITS: irqchip implementation irqchip: GICv3: ITS command queue irqchip: GICv3: rework redistributor structure ...
This commit is contained in:
Linus Torvalds
commit
60d7ef3fd3
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@ -49,11 +49,29 @@ Optional
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|||
occupied by the redistributors. Required if more than one such
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region is present.
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Sub-nodes:
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GICv3 has one or more Interrupt Translation Services (ITS) that are
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used to route Message Signalled Interrupts (MSI) to the CPUs.
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These nodes must have the following properties:
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- compatible : Should at least contain "arm,gic-v3-its".
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- msi-controller : Boolean property. Identifies the node as an MSI controller
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- reg: Specifies the base physical address and size of the ITS
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registers.
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The main GIC node must contain the appropriate #address-cells,
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#size-cells and ranges properties for the reg property of all ITS
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nodes.
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Examples:
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gic: interrupt-controller@2cf00000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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reg = <0x0 0x2f000000 0 0x10000>, // GICD
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<0x0 0x2f100000 0 0x200000>, // GICR
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@ -61,11 +79,20 @@ Examples:
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<0x0 0x2c010000 0 0x2000>, // GICH
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<0x0 0x2c020000 0 0x2000>; // GICV
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interrupts = <1 9 4>;
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gic-its@2c200000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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reg = <0x0 0x2c200000 0 0x200000>;
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};
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};
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gic: interrupt-controller@2c010000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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redistributor-stride = <0x0 0x40000>; // 256kB stride
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#redistributor-regions = <2>;
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@ -76,4 +103,16 @@ Examples:
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<0x0 0x2c060000 0 0x2000>, // GICH
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<0x0 0x2c080000 0 0x2000>; // GICV
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interrupts = <1 9 4>;
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gic-its@2c200000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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reg = <0x0 0x2c200000 0 0x200000>;
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};
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gic-its@2c400000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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reg = <0x0 0x2c400000 0 0x200000>;
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};
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};
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|
|
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@ -97,3 +97,56 @@ Example:
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<0x2c006000 0x2000>;
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interrupts = <1 9 0xf04>;
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};
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* GICv2m extension for MSI/MSI-x support (Optional)
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Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
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This is enabled by specifying v2m sub-node(s).
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Required properties:
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- compatible : The value here should contain "arm,gic-v2m-frame".
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- msi-controller : Identifies the node as an MSI controller.
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- reg : GICv2m MSI interface register base and size
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Optional properties:
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- arm,msi-base-spi : When the MSI_TYPER register contains an incorrect
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value, this property should contain the SPI base of
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the MSI frame, overriding the HW value.
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- arm,msi-num-spis : When the MSI_TYPER register contains an incorrect
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value, this property should contain the number of
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SPIs assigned to the frame, overriding the HW value.
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Example:
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interrupt-controller@e1101000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-controller;
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interrupts = <1 8 0xf04>;
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ranges = <0 0 0 0xe1100000 0 0x100000>;
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reg = <0x0 0xe1110000 0 0x01000>,
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<0x0 0xe112f000 0 0x02000>,
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<0x0 0xe1140000 0 0x10000>,
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<0x0 0xe1160000 0 0x10000>;
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v2m0: v2m@0x8000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x0 0x80000 0 0x1000>;
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};
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....
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v2mN: v2m@0x9000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x0 0x90000 0 0x1000>;
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};
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};
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|
|
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@ -0,0 +1,28 @@
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Mediatek 65xx/81xx sysirq
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Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI
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interrupt.
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Required properties:
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- compatible: should be one of:
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"mediatek,mt8135-sysirq"
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"mediatek,mt8127-sysirq"
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"mediatek,mt6589-sysirq"
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"mediatek,mt6582-sysirq"
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"mediatek,mt6577-sysirq"
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Use the same format as specified by GIC in
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Documentation/devicetree/bindings/arm/gic.txt
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- interrupt-parent: phandle of irq parent for sysirq. The parent must
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use the same interrupt-cells format as GIC.
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- reg: Physical base address of the intpol registers and length of memory
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mapped region.
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Example:
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sysirq: interrupt-controller@10200100 {
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compatible = "mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x10200100 0 0x1c>;
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};
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@ -14,7 +14,9 @@ config ARM64
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select ARM_ARCH_TIMER
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select ARM_GIC
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select AUDIT_ARCH_COMPAT_GENERIC
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select ARM_GIC_V2M if PCI_MSI
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select ARM_GIC_V3
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select ARM_GIC_V3_ITS if PCI_MSI
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select BUILDTIME_EXTABLE_SORT
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select CLONE_BACKWARDS
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select COMMON_CLK
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|
|
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@ -27,6 +27,7 @@ generic-y += local64.h
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generic-y += mcs_spinlock.h
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generic-y += mman.h
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generic-y += msgbuf.h
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generic-y += msi.h
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generic-y += mutex.h
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generic-y += pci.h
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generic-y += pci-bridge.h
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|
|
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@ -5,8 +5,15 @@ config IRQCHIP
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config ARM_GIC
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bool
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select IRQ_DOMAIN
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select IRQ_DOMAIN_HIERARCHY
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select MULTI_IRQ_HANDLER
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config ARM_GIC_V2M
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bool
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depends on ARM_GIC
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depends on PCI && PCI_MSI
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select PCI_MSI_IRQ_DOMAIN
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config GIC_NON_BANKED
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bool
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|
@ -14,6 +21,11 @@ config ARM_GIC_V3
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bool
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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select IRQ_DOMAIN_HIERARCHY
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config ARM_GIC_V3_ITS
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bool
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select PCI_MSI_IRQ_DOMAIN
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config ARM_NVIC
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bool
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|
|
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@ -19,7 +19,9 @@ obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o
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obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi-nmi.o
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obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
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obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o
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obj-$(CONFIG_ARM_GIC_V2M) += irq-gic-v2m.o
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obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-common.o
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obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o
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obj-$(CONFIG_ARM_NVIC) += irq-nvic.o
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obj-$(CONFIG_ARM_VIC) += irq-vic.o
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obj-$(CONFIG_ATMEL_AIC_IRQ) += irq-atmel-aic-common.o irq-atmel-aic.o
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@ -39,3 +41,4 @@ obj-$(CONFIG_BCM7120_L2_IRQ) += irq-bcm7120-l2.o
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obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o
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obj-$(CONFIG_KEYSTONE_IRQ) += irq-keystone.o
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obj-$(CONFIG_MIPS_GIC) += irq-mips-gic.o
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obj-$(CONFIG_ARCH_MEDIATEK) += irq-mtk-sysirq.o
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|
|
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333
drivers/irqchip/irq-gic-v2m.c
Normal file
333
drivers/irqchip/irq-gic-v2m.c
Normal file
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@ -0,0 +1,333 @@
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/*
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* ARM GIC v2m MSI(-X) support
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* Support for Message Signaled Interrupts for systems that
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* implement ARM Generic Interrupt Controller: GICv2m.
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*
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* Copyright (C) 2014 Advanced Micro Devices, Inc.
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* Authors: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
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* Harish Kasiviswanathan <harish.kasiviswanathan@amd.com>
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* Brandon Anderson <brandon.anderson@amd.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#define pr_fmt(fmt) "GICv2m: " fmt
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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/*
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* MSI_TYPER:
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* [31:26] Reserved
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* [25:16] lowest SPI assigned to MSI
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* [15:10] Reserved
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* [9:0] Numer of SPIs assigned to MSI
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*/
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#define V2M_MSI_TYPER 0x008
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#define V2M_MSI_TYPER_BASE_SHIFT 16
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#define V2M_MSI_TYPER_BASE_MASK 0x3FF
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#define V2M_MSI_TYPER_NUM_MASK 0x3FF
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#define V2M_MSI_SETSPI_NS 0x040
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#define V2M_MIN_SPI 32
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#define V2M_MAX_SPI 1019
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#define V2M_MSI_TYPER_BASE_SPI(x) \
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(((x) >> V2M_MSI_TYPER_BASE_SHIFT) & V2M_MSI_TYPER_BASE_MASK)
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|
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#define V2M_MSI_TYPER_NUM_SPI(x) ((x) & V2M_MSI_TYPER_NUM_MASK)
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struct v2m_data {
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spinlock_t msi_cnt_lock;
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struct msi_controller mchip;
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struct resource res; /* GICv2m resource */
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void __iomem *base; /* GICv2m virt address */
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u32 spi_start; /* The SPI number that MSIs start */
|
||||
u32 nr_spis; /* The number of SPIs for MSIs */
|
||||
unsigned long *bm; /* MSI vector bitmap */
|
||||
struct irq_domain *domain;
|
||||
};
|
||||
|
||||
static void gicv2m_mask_msi_irq(struct irq_data *d)
|
||||
{
|
||||
pci_msi_mask_irq(d);
|
||||
irq_chip_mask_parent(d);
|
||||
}
|
||||
|
||||
static void gicv2m_unmask_msi_irq(struct irq_data *d)
|
||||
{
|
||||
pci_msi_unmask_irq(d);
|
||||
irq_chip_unmask_parent(d);
|
||||
}
|
||||
|
||||
static struct irq_chip gicv2m_msi_irq_chip = {
|
||||
.name = "MSI",
|
||||
.irq_mask = gicv2m_mask_msi_irq,
|
||||
.irq_unmask = gicv2m_unmask_msi_irq,
|
||||
.irq_eoi = irq_chip_eoi_parent,
|
||||
.irq_write_msi_msg = pci_msi_domain_write_msg,
|
||||
};
|
||||
|
||||
static struct msi_domain_info gicv2m_msi_domain_info = {
|
||||
.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
|
||||
MSI_FLAG_PCI_MSIX),
|
||||
.chip = &gicv2m_msi_irq_chip,
|
||||
};
|
||||
|
||||
static int gicv2m_set_affinity(struct irq_data *irq_data,
|
||||
const struct cpumask *mask, bool force)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = irq_chip_set_affinity_parent(irq_data, mask, force);
|
||||
if (ret == IRQ_SET_MASK_OK)
|
||||
ret = IRQ_SET_MASK_OK_DONE;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
|
||||
{
|
||||
struct v2m_data *v2m = irq_data_get_irq_chip_data(data);
|
||||
phys_addr_t addr = v2m->res.start + V2M_MSI_SETSPI_NS;
|
||||
|
||||
msg->address_hi = (u32) (addr >> 32);
|
||||
msg->address_lo = (u32) (addr);
|
||||
msg->data = data->hwirq;
|
||||
}
|
||||
|
||||
static struct irq_chip gicv2m_irq_chip = {
|
||||
.name = "GICv2m",
|
||||
.irq_mask = irq_chip_mask_parent,
|
||||
.irq_unmask = irq_chip_unmask_parent,
|
||||
.irq_eoi = irq_chip_eoi_parent,
|
||||
.irq_set_affinity = gicv2m_set_affinity,
|
||||
.irq_compose_msi_msg = gicv2m_compose_msi_msg,
|
||||
};
|
||||
|
||||
static int gicv2m_irq_gic_domain_alloc(struct irq_domain *domain,
|
||||
unsigned int virq,
|
||||
irq_hw_number_t hwirq)
|
||||
{
|
||||
struct of_phandle_args args;
|
||||
struct irq_data *d;
|
||||
int err;
|
||||
|
||||
args.np = domain->parent->of_node;
|
||||
args.args_count = 3;
|
||||
args.args[0] = 0;
|
||||
args.args[1] = hwirq - 32;
|
||||
args.args[2] = IRQ_TYPE_EDGE_RISING;
|
||||
|
||||
err = irq_domain_alloc_irqs_parent(domain, virq, 1, &args);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
/* Configure the interrupt line to be edge */
|
||||
d = irq_domain_get_irq_data(domain->parent, virq);
|
||||
d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void gicv2m_unalloc_msi(struct v2m_data *v2m, unsigned int hwirq)
|
||||
{
|
||||
int pos;
|
||||
|
||||
pos = hwirq - v2m->spi_start;
|
||||
if (pos < 0 || pos >= v2m->nr_spis) {
|
||||
pr_err("Failed to teardown msi. Invalid hwirq %d\n", hwirq);
|
||||
return;
|
||||
}
|
||||
|
||||
spin_lock(&v2m->msi_cnt_lock);
|
||||
__clear_bit(pos, v2m->bm);
|
||||
spin_unlock(&v2m->msi_cnt_lock);
|
||||
}
|
||||
|
||||
static int gicv2m_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
|
||||
unsigned int nr_irqs, void *args)
|
||||
{
|
||||
struct v2m_data *v2m = domain->host_data;
|
||||
int hwirq, offset, err = 0;
|
||||
|
||||
spin_lock(&v2m->msi_cnt_lock);
|
||||
offset = find_first_zero_bit(v2m->bm, v2m->nr_spis);
|
||||
if (offset < v2m->nr_spis)
|
||||
__set_bit(offset, v2m->bm);
|
||||
else
|
||||
err = -ENOSPC;
|
||||
spin_unlock(&v2m->msi_cnt_lock);
|
||||
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
hwirq = v2m->spi_start + offset;
|
||||
|
||||
err = gicv2m_irq_gic_domain_alloc(domain, virq, hwirq);
|
||||
if (err) {
|
||||
gicv2m_unalloc_msi(v2m, hwirq);
|
||||
return err;
|
||||
}
|
||||
|
||||
irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
|
||||
&gicv2m_irq_chip, v2m);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void gicv2m_irq_domain_free(struct irq_domain *domain,
|
||||
unsigned int virq, unsigned int nr_irqs)
|
||||
{
|
||||
struct irq_data *d = irq_domain_get_irq_data(domain, virq);
|
||||
struct v2m_data *v2m = irq_data_get_irq_chip_data(d);
|
||||
|
||||
BUG_ON(nr_irqs != 1);
|
||||
gicv2m_unalloc_msi(v2m, d->hwirq);
|
||||
irq_domain_free_irqs_parent(domain, virq, nr_irqs);
|
||||
}
|
||||
|
||||
static const struct irq_domain_ops gicv2m_domain_ops = {
|
||||
.alloc = gicv2m_irq_domain_alloc,
|
||||
.free = gicv2m_irq_domain_free,
|
||||
};
|
||||
|
||||
static bool is_msi_spi_valid(u32 base, u32 num)
|
||||
{
|
||||
if (base < V2M_MIN_SPI) {
|
||||
pr_err("Invalid MSI base SPI (base:%u)\n", base);
|
||||
return false;
|
||||
}
|
||||
|
||||
if ((num == 0) || (base + num > V2M_MAX_SPI)) {
|
||||
pr_err("Number of SPIs (%u) exceed maximum (%u)\n",
|
||||
num, V2M_MAX_SPI - V2M_MIN_SPI + 1);
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static int __init gicv2m_init_one(struct device_node *node,
|
||||
struct irq_domain *parent)
|
||||
{
|
||||
int ret;
|
||||
struct v2m_data *v2m;
|
||||
|
||||
v2m = kzalloc(sizeof(struct v2m_data), GFP_KERNEL);
|
||||
if (!v2m) {
|
||||
pr_err("Failed to allocate struct v2m_data.\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ret = of_address_to_resource(node, 0, &v2m->res);
|
||||
if (ret) {
|
||||
pr_err("Failed to allocate v2m resource.\n");
|
||||
goto err_free_v2m;
|
||||
}
|
||||
|
||||
v2m->base = ioremap(v2m->res.start, resource_size(&v2m->res));
|
||||
if (!v2m->base) {
|
||||
pr_err("Failed to map GICv2m resource\n");
|
||||
ret = -ENOMEM;
|
||||
goto err_free_v2m;
|
||||
}
|
||||
|
||||
if (!of_property_read_u32(node, "arm,msi-base-spi", &v2m->spi_start) &&
|
||||
!of_property_read_u32(node, "arm,msi-num-spis", &v2m->nr_spis)) {
|
||||
pr_info("Overriding V2M MSI_TYPER (base:%u, num:%u)\n",
|
||||
v2m->spi_start, v2m->nr_spis);
|
||||
} else {
|
||||
u32 typer = readl_relaxed(v2m->base + V2M_MSI_TYPER);
|
||||
|
||||
v2m->spi_start = V2M_MSI_TYPER_BASE_SPI(typer);
|
||||
v2m->nr_spis = V2M_MSI_TYPER_NUM_SPI(typer);
|
||||
}
|
||||
|
||||
if (!is_msi_spi_valid(v2m->spi_start, v2m->nr_spis)) {
|
||||
ret = -EINVAL;
|
||||
goto err_iounmap;
|
||||
}
|
||||
|
||||
v2m->bm = kzalloc(sizeof(long) * BITS_TO_LONGS(v2m->nr_spis),
|
||||
GFP_KERNEL);
|
||||
if (!v2m->bm) {
|
||||
ret = -ENOMEM;
|
||||
goto err_iounmap;
|
||||
}
|
||||
|
||||
v2m->domain = irq_domain_add_tree(NULL, &gicv2m_domain_ops, v2m);
|
||||
if (!v2m->domain) {
|
||||
pr_err("Failed to create GICv2m domain\n");
|
||||
ret = -ENOMEM;
|
||||
goto err_free_bm;
|
||||
}
|
||||
|
||||
v2m->domain->parent = parent;
|
||||
v2m->mchip.of_node = node;
|
||||
v2m->mchip.domain = pci_msi_create_irq_domain(node,
|
||||
&gicv2m_msi_domain_info,
|
||||
v2m->domain);
|
||||
if (!v2m->mchip.domain) {
|
||||
pr_err("Failed to create MSI domain\n");
|
||||
ret = -ENOMEM;
|
||||
goto err_free_domains;
|
||||
}
|
||||
|
||||
spin_lock_init(&v2m->msi_cnt_lock);
|
||||
|
||||
ret = of_pci_msi_chip_add(&v2m->mchip);
|
||||
if (ret) {
|
||||
pr_err("Failed to add msi_chip.\n");
|
||||
goto err_free_domains;
|
||||
}
|
||||
|
||||
pr_info("Node %s: range[%#lx:%#lx], SPI[%d:%d]\n", node->name,
|
||||
(unsigned long)v2m->res.start, (unsigned long)v2m->res.end,
|
||||
v2m->spi_start, (v2m->spi_start + v2m->nr_spis));
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_domains:
|
||||
if (v2m->mchip.domain)
|
||||
irq_domain_remove(v2m->mchip.domain);
|
||||
if (v2m->domain)
|
||||
irq_domain_remove(v2m->domain);
|
||||
err_free_bm:
|
||||
kfree(v2m->bm);
|
||||
err_iounmap:
|
||||
iounmap(v2m->base);
|
||||
err_free_v2m:
|
||||
kfree(v2m);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct of_device_id gicv2m_device_id[] = {
|
||||
{ .compatible = "arm,gic-v2m-frame", },
|
||||
{},
|
||||
};
|
||||
|
||||
int __init gicv2m_of_init(struct device_node *node, struct irq_domain *parent)
|
||||
{
|
||||
int ret = 0;
|
||||
struct device_node *child;
|
||||
|
||||
for (child = of_find_matching_node(node, gicv2m_device_id); child;
|
||||
child = of_find_matching_node(child, gicv2m_device_id)) {
|
||||
if (!of_find_property(child, "msi-controller", NULL))
|
||||
continue;
|
||||
|
||||
ret = gicv2m_init_one(child, parent);
|
||||
if (ret) {
|
||||
of_node_put(node);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
1425
drivers/irqchip/irq-gic-v3-its.c
Normal file
1425
drivers/irqchip/irq-gic-v3-its.c
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -34,20 +34,25 @@
|
|||
#include "irq-gic-common.h"
|
||||
#include "irqchip.h"
|
||||
|
||||
struct redist_region {
|
||||
void __iomem *redist_base;
|
||||
phys_addr_t phys_base;
|
||||
};
|
||||
|
||||
struct gic_chip_data {
|
||||
void __iomem *dist_base;
|
||||
void __iomem **redist_base;
|
||||
void __iomem * __percpu *rdist;
|
||||
struct redist_region *redist_regions;
|
||||
struct rdists rdists;
|
||||
struct irq_domain *domain;
|
||||
u64 redist_stride;
|
||||
u32 redist_regions;
|
||||
u32 nr_redist_regions;
|
||||
unsigned int irq_nr;
|
||||
};
|
||||
|
||||
static struct gic_chip_data gic_data __read_mostly;
|
||||
|
||||
#define gic_data_rdist() (this_cpu_ptr(gic_data.rdist))
|
||||
#define gic_data_rdist_rd_base() (*gic_data_rdist())
|
||||
#define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist))
|
||||
#define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
|
||||
#define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K)
|
||||
|
||||
/* Our default, arbitrary priority value. Linux only uses one anyway. */
|
||||
|
|
@ -71,9 +76,6 @@ static inline void __iomem *gic_dist_base(struct irq_data *d)
|
|||
if (d->hwirq <= 1023) /* SPI -> dist_base */
|
||||
return gic_data.dist_base;
|
||||
|
||||
if (d->hwirq >= 8192)
|
||||
BUG(); /* LPI Detected!!! */
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
|
@ -271,11 +273,11 @@ static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs
|
|||
do {
|
||||
irqnr = gic_read_iar();
|
||||
|
||||
if (likely(irqnr > 15 && irqnr < 1020)) {
|
||||
if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) {
|
||||
int err;
|
||||
err = handle_domain_irq(gic_data.domain, irqnr, regs);
|
||||
if (err) {
|
||||
WARN_ONCE(true, "Unexpected SPI received!\n");
|
||||
WARN_ONCE(true, "Unexpected interrupt received!\n");
|
||||
gic_write_eoir(irqnr);
|
||||
}
|
||||
continue;
|
||||
|
|
@ -333,8 +335,8 @@ static int gic_populate_rdist(void)
|
|||
MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
|
||||
MPIDR_AFFINITY_LEVEL(mpidr, 0));
|
||||
|
||||
for (i = 0; i < gic_data.redist_regions; i++) {
|
||||
void __iomem *ptr = gic_data.redist_base[i];
|
||||
for (i = 0; i < gic_data.nr_redist_regions; i++) {
|
||||
void __iomem *ptr = gic_data.redist_regions[i].redist_base;
|
||||
u32 reg;
|
||||
|
||||
reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
|
||||
|
|
@ -347,10 +349,13 @@ static int gic_populate_rdist(void)
|
|||
do {
|
||||
typer = readq_relaxed(ptr + GICR_TYPER);
|
||||
if ((typer >> 32) == aff) {
|
||||
u64 offset = ptr - gic_data.redist_regions[i].redist_base;
|
||||
gic_data_rdist_rd_base() = ptr;
|
||||
pr_info("CPU%d: found redistributor %llx @%p\n",
|
||||
gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset;
|
||||
pr_info("CPU%d: found redistributor %llx region %d:%pa\n",
|
||||
smp_processor_id(),
|
||||
(unsigned long long)mpidr, ptr);
|
||||
(unsigned long long)mpidr,
|
||||
i, &gic_data_rdist()->phys_base);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -385,6 +390,11 @@ static void gic_cpu_sys_reg_init(void)
|
|||
gic_write_grpen1(1);
|
||||
}
|
||||
|
||||
static int gic_dist_supports_lpis(void)
|
||||
{
|
||||
return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS);
|
||||
}
|
||||
|
||||
static void gic_cpu_init(void)
|
||||
{
|
||||
void __iomem *rbase;
|
||||
|
|
@ -399,6 +409,10 @@ static void gic_cpu_init(void)
|
|||
|
||||
gic_cpu_config(rbase, gic_redist_wait_for_rwp);
|
||||
|
||||
/* Give LPIs a spin */
|
||||
if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
|
||||
its_cpu_init();
|
||||
|
||||
/* initialise system registers */
|
||||
gic_cpu_sys_reg_init();
|
||||
}
|
||||
|
|
@ -585,26 +599,43 @@ static struct irq_chip gic_chip = {
|
|||
.irq_set_affinity = gic_set_affinity,
|
||||
};
|
||||
|
||||
#define GIC_ID_NR (1U << gic_data.rdists.id_bits)
|
||||
|
||||
static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
|
||||
irq_hw_number_t hw)
|
||||
{
|
||||
/* SGIs are private to the core kernel */
|
||||
if (hw < 16)
|
||||
return -EPERM;
|
||||
/* Nothing here */
|
||||
if (hw >= gic_data.irq_nr && hw < 8192)
|
||||
return -EPERM;
|
||||
/* Off limits */
|
||||
if (hw >= GIC_ID_NR)
|
||||
return -EPERM;
|
||||
|
||||
/* PPIs */
|
||||
if (hw < 32) {
|
||||
irq_set_percpu_devid(irq);
|
||||
irq_set_chip_and_handler(irq, &gic_chip,
|
||||
handle_percpu_devid_irq);
|
||||
irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data,
|
||||
handle_percpu_devid_irq, NULL, NULL);
|
||||
set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
|
||||
}
|
||||
/* SPIs */
|
||||
if (hw >= 32 && hw < gic_data.irq_nr) {
|
||||
irq_set_chip_and_handler(irq, &gic_chip,
|
||||
handle_fasteoi_irq);
|
||||
irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data,
|
||||
handle_fasteoi_irq, NULL, NULL);
|
||||
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
irq_set_chip_data(irq, d->host_data);
|
||||
/* LPIs */
|
||||
if (hw >= 8192 && hw < GIC_ID_NR) {
|
||||
if (!gic_dist_supports_lpis())
|
||||
return -EPERM;
|
||||
irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data,
|
||||
handle_fasteoi_irq, NULL, NULL);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -625,6 +656,9 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
|
|||
case 1: /* PPI */
|
||||
*out_hwirq = intspec[1] + 16;
|
||||
break;
|
||||
case GIC_IRQ_TYPE_LPI: /* LPI */
|
||||
*out_hwirq = intspec[1];
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
@ -633,17 +667,50 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
|
||||
unsigned int nr_irqs, void *arg)
|
||||
{
|
||||
int i, ret;
|
||||
irq_hw_number_t hwirq;
|
||||
unsigned int type = IRQ_TYPE_NONE;
|
||||
struct of_phandle_args *irq_data = arg;
|
||||
|
||||
ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args,
|
||||
irq_data->args_count, &hwirq, &type);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
for (i = 0; i < nr_irqs; i++)
|
||||
gic_irq_domain_map(domain, virq + i, hwirq + i);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq,
|
||||
unsigned int nr_irqs)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nr_irqs; i++) {
|
||||
struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
|
||||
irq_set_handler(virq + i, NULL);
|
||||
irq_domain_reset_irq_data(d);
|
||||
}
|
||||
}
|
||||
|
||||
static const struct irq_domain_ops gic_irq_domain_ops = {
|
||||
.map = gic_irq_domain_map,
|
||||
.xlate = gic_irq_domain_xlate,
|
||||
.alloc = gic_irq_domain_alloc,
|
||||
.free = gic_irq_domain_free,
|
||||
};
|
||||
|
||||
static int __init gic_of_init(struct device_node *node, struct device_node *parent)
|
||||
{
|
||||
void __iomem *dist_base;
|
||||
void __iomem **redist_base;
|
||||
struct redist_region *rdist_regs;
|
||||
u64 redist_stride;
|
||||
u32 redist_regions;
|
||||
u32 nr_redist_regions;
|
||||
u32 typer;
|
||||
u32 reg;
|
||||
int gic_irqs;
|
||||
int err;
|
||||
|
|
@ -664,54 +731,63 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
|
|||
goto out_unmap_dist;
|
||||
}
|
||||
|
||||
if (of_property_read_u32(node, "#redistributor-regions", &redist_regions))
|
||||
redist_regions = 1;
|
||||
if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions))
|
||||
nr_redist_regions = 1;
|
||||
|
||||
redist_base = kzalloc(sizeof(*redist_base) * redist_regions, GFP_KERNEL);
|
||||
if (!redist_base) {
|
||||
rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL);
|
||||
if (!rdist_regs) {
|
||||
err = -ENOMEM;
|
||||
goto out_unmap_dist;
|
||||
}
|
||||
|
||||
for (i = 0; i < redist_regions; i++) {
|
||||
redist_base[i] = of_iomap(node, 1 + i);
|
||||
if (!redist_base[i]) {
|
||||
for (i = 0; i < nr_redist_regions; i++) {
|
||||
struct resource res;
|
||||
int ret;
|
||||
|
||||
ret = of_address_to_resource(node, 1 + i, &res);
|
||||
rdist_regs[i].redist_base = of_iomap(node, 1 + i);
|
||||
if (ret || !rdist_regs[i].redist_base) {
|
||||
pr_err("%s: couldn't map region %d\n",
|
||||
node->full_name, i);
|
||||
err = -ENODEV;
|
||||
goto out_unmap_rdist;
|
||||
}
|
||||
rdist_regs[i].phys_base = res.start;
|
||||
}
|
||||
|
||||
if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
|
||||
redist_stride = 0;
|
||||
|
||||
gic_data.dist_base = dist_base;
|
||||
gic_data.redist_base = redist_base;
|
||||
gic_data.redist_regions = redist_regions;
|
||||
gic_data.redist_regions = rdist_regs;
|
||||
gic_data.nr_redist_regions = nr_redist_regions;
|
||||
gic_data.redist_stride = redist_stride;
|
||||
|
||||
/*
|
||||
* Find out how many interrupts are supported.
|
||||
* The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
|
||||
*/
|
||||
gic_irqs = readl_relaxed(gic_data.dist_base + GICD_TYPER) & 0x1f;
|
||||
gic_irqs = (gic_irqs + 1) * 32;
|
||||
typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
|
||||
gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer);
|
||||
gic_irqs = GICD_TYPER_IRQS(typer);
|
||||
if (gic_irqs > 1020)
|
||||
gic_irqs = 1020;
|
||||
gic_data.irq_nr = gic_irqs;
|
||||
|
||||
gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops,
|
||||
&gic_data);
|
||||
gic_data.rdist = alloc_percpu(typeof(*gic_data.rdist));
|
||||
gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
|
||||
|
||||
if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdist)) {
|
||||
if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
|
||||
err = -ENOMEM;
|
||||
goto out_free;
|
||||
}
|
||||
|
||||
set_handle_irq(gic_handle_irq);
|
||||
|
||||
if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
|
||||
its_init(node, &gic_data.rdists, gic_data.domain);
|
||||
|
||||
gic_smp_init();
|
||||
gic_dist_init();
|
||||
gic_cpu_init();
|
||||
|
|
@ -722,12 +798,12 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
|
|||
out_free:
|
||||
if (gic_data.domain)
|
||||
irq_domain_remove(gic_data.domain);
|
||||
free_percpu(gic_data.rdist);
|
||||
free_percpu(gic_data.rdists.rdist);
|
||||
out_unmap_rdist:
|
||||
for (i = 0; i < redist_regions; i++)
|
||||
if (redist_base[i])
|
||||
iounmap(redist_base[i]);
|
||||
kfree(redist_base);
|
||||
for (i = 0; i < nr_redist_regions; i++)
|
||||
if (rdist_regs[i].redist_base)
|
||||
iounmap(rdist_regs[i].redist_base);
|
||||
kfree(rdist_regs);
|
||||
out_unmap_dist:
|
||||
iounmap(dist_base);
|
||||
return err;
|
||||
|
|
|
|||
|
|
@ -788,17 +788,16 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
|
|||
{
|
||||
if (hw < 32) {
|
||||
irq_set_percpu_devid(irq);
|
||||
irq_set_chip_and_handler(irq, &gic_chip,
|
||||
handle_percpu_devid_irq);
|
||||
irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data,
|
||||
handle_percpu_devid_irq, NULL, NULL);
|
||||
set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
|
||||
} else {
|
||||
irq_set_chip_and_handler(irq, &gic_chip,
|
||||
handle_fasteoi_irq);
|
||||
irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data,
|
||||
handle_fasteoi_irq, NULL, NULL);
|
||||
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
||||
|
||||
gic_routable_irq_domain_ops->map(d, irq, hw);
|
||||
}
|
||||
irq_set_chip_data(irq, d->host_data);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -858,6 +857,31 @@ static struct notifier_block gic_cpu_notifier = {
|
|||
};
|
||||
#endif
|
||||
|
||||
static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
|
||||
unsigned int nr_irqs, void *arg)
|
||||
{
|
||||
int i, ret;
|
||||
irq_hw_number_t hwirq;
|
||||
unsigned int type = IRQ_TYPE_NONE;
|
||||
struct of_phandle_args *irq_data = arg;
|
||||
|
||||
ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args,
|
||||
irq_data->args_count, &hwirq, &type);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
for (i = 0; i < nr_irqs; i++)
|
||||
gic_irq_domain_map(domain, virq + i, hwirq + i);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
|
||||
.xlate = gic_irq_domain_xlate,
|
||||
.alloc = gic_irq_domain_alloc,
|
||||
.free = irq_domain_free_irqs_top,
|
||||
};
|
||||
|
||||
static const struct irq_domain_ops gic_irq_domain_ops = {
|
||||
.map = gic_irq_domain_map,
|
||||
.unmap = gic_irq_domain_unmap,
|
||||
|
|
@ -947,18 +971,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
|
|||
for (i = 0; i < NR_GIC_CPU_IF; i++)
|
||||
gic_cpu_map[i] = 0xff;
|
||||
|
||||
/*
|
||||
* For primary GICs, skip over SGIs.
|
||||
* For secondary GICs, skip over PPIs, too.
|
||||
*/
|
||||
if (gic_nr == 0 && (irq_start & 31) > 0) {
|
||||
hwirq_base = 16;
|
||||
if (irq_start != -1)
|
||||
irq_start = (irq_start & ~31) + 16;
|
||||
} else {
|
||||
hwirq_base = 32;
|
||||
}
|
||||
|
||||
/*
|
||||
* Find out how many interrupts are supported.
|
||||
* The GIC only supports up to 1020 interrupt sources.
|
||||
|
|
@ -969,10 +981,31 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
|
|||
gic_irqs = 1020;
|
||||
gic->gic_irqs = gic_irqs;
|
||||
|
||||
gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
|
||||
if (node) { /* DT case */
|
||||
const struct irq_domain_ops *ops = &gic_irq_domain_hierarchy_ops;
|
||||
|
||||
if (!of_property_read_u32(node, "arm,routable-irqs",
|
||||
&nr_routable_irqs)) {
|
||||
ops = &gic_irq_domain_ops;
|
||||
gic_irqs = nr_routable_irqs;
|
||||
}
|
||||
|
||||
gic->domain = irq_domain_add_linear(node, gic_irqs, ops, gic);
|
||||
} else { /* Non-DT case */
|
||||
/*
|
||||
* For primary GICs, skip over SGIs.
|
||||
* For secondary GICs, skip over PPIs, too.
|
||||
*/
|
||||
if (gic_nr == 0 && (irq_start & 31) > 0) {
|
||||
hwirq_base = 16;
|
||||
if (irq_start != -1)
|
||||
irq_start = (irq_start & ~31) + 16;
|
||||
} else {
|
||||
hwirq_base = 32;
|
||||
}
|
||||
|
||||
gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
|
||||
|
||||
if (of_property_read_u32(node, "arm,routable-irqs",
|
||||
&nr_routable_irqs)) {
|
||||
irq_base = irq_alloc_descs(irq_start, 16, gic_irqs,
|
||||
numa_node_id());
|
||||
if (IS_ERR_VALUE(irq_base)) {
|
||||
|
|
@ -983,10 +1016,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
|
|||
|
||||
gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
|
||||
hwirq_base, &gic_irq_domain_ops, gic);
|
||||
} else {
|
||||
gic->domain = irq_domain_add_linear(node, nr_routable_irqs,
|
||||
&gic_irq_domain_ops,
|
||||
gic);
|
||||
}
|
||||
|
||||
if (WARN_ON(!gic->domain))
|
||||
|
|
@ -1037,6 +1066,10 @@ gic_of_init(struct device_node *node, struct device_node *parent)
|
|||
irq = irq_of_parse_and_map(node, 0);
|
||||
gic_cascade_irq(gic_cnt, irq);
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
|
||||
gicv2m_of_init(node, gic_data[gic_cnt].domain);
|
||||
|
||||
gic_cnt++;
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
163
drivers/irqchip/irq-mtk-sysirq.c
Normal file
163
drivers/irqchip/irq-mtk-sysirq.c
Normal file
|
|
@ -0,0 +1,163 @@
|
|||
/*
|
||||
* Copyright (c) 2014 MediaTek Inc.
|
||||
* Author: Joe.C <yingjoe.chen@mediatek.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#include "irqchip.h"
|
||||
|
||||
#define MT6577_SYS_INTPOL_NUM (224)
|
||||
|
||||
struct mtk_sysirq_chip_data {
|
||||
spinlock_t lock;
|
||||
void __iomem *intpol_base;
|
||||
};
|
||||
|
||||
static int mtk_sysirq_set_type(struct irq_data *data, unsigned int type)
|
||||
{
|
||||
irq_hw_number_t hwirq = data->hwirq;
|
||||
struct mtk_sysirq_chip_data *chip_data = data->chip_data;
|
||||
u32 offset, reg_index, value;
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
offset = hwirq & 0x1f;
|
||||
reg_index = hwirq >> 5;
|
||||
|
||||
spin_lock_irqsave(&chip_data->lock, flags);
|
||||
value = readl_relaxed(chip_data->intpol_base + reg_index * 4);
|
||||
if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_EDGE_FALLING) {
|
||||
if (type == IRQ_TYPE_LEVEL_LOW)
|
||||
type = IRQ_TYPE_LEVEL_HIGH;
|
||||
else
|
||||
type = IRQ_TYPE_EDGE_RISING;
|
||||
value |= (1 << offset);
|
||||
} else {
|
||||
value &= ~(1 << offset);
|
||||
}
|
||||
writel(value, chip_data->intpol_base + reg_index * 4);
|
||||
|
||||
data = data->parent_data;
|
||||
ret = data->chip->irq_set_type(data, type);
|
||||
spin_unlock_irqrestore(&chip_data->lock, flags);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct irq_chip mtk_sysirq_chip = {
|
||||
.name = "MT_SYSIRQ",
|
||||
.irq_mask = irq_chip_mask_parent,
|
||||
.irq_unmask = irq_chip_unmask_parent,
|
||||
.irq_eoi = irq_chip_eoi_parent,
|
||||
.irq_set_type = mtk_sysirq_set_type,
|
||||
.irq_retrigger = irq_chip_retrigger_hierarchy,
|
||||
.irq_set_affinity = irq_chip_set_affinity_parent,
|
||||
};
|
||||
|
||||
static int mtk_sysirq_domain_xlate(struct irq_domain *d,
|
||||
struct device_node *controller,
|
||||
const u32 *intspec, unsigned int intsize,
|
||||
unsigned long *out_hwirq,
|
||||
unsigned int *out_type)
|
||||
{
|
||||
if (intsize != 3)
|
||||
return -EINVAL;
|
||||
|
||||
/* sysirq doesn't support PPI */
|
||||
if (intspec[0])
|
||||
return -EINVAL;
|
||||
|
||||
*out_hwirq = intspec[1];
|
||||
*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_sysirq_domain_alloc(struct irq_domain *domain, unsigned int virq,
|
||||
unsigned int nr_irqs, void *arg)
|
||||
{
|
||||
int i;
|
||||
irq_hw_number_t hwirq;
|
||||
struct of_phandle_args *irq_data = arg;
|
||||
struct of_phandle_args gic_data = *irq_data;
|
||||
|
||||
if (irq_data->args_count != 3)
|
||||
return -EINVAL;
|
||||
|
||||
/* sysirq doesn't support PPI */
|
||||
if (irq_data->args[0])
|
||||
return -EINVAL;
|
||||
|
||||
hwirq = irq_data->args[1];
|
||||
for (i = 0; i < nr_irqs; i++)
|
||||
irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
|
||||
&mtk_sysirq_chip,
|
||||
domain->host_data);
|
||||
|
||||
gic_data.np = domain->parent->of_node;
|
||||
return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_data);
|
||||
}
|
||||
|
||||
static struct irq_domain_ops sysirq_domain_ops = {
|
||||
.xlate = mtk_sysirq_domain_xlate,
|
||||
.alloc = mtk_sysirq_domain_alloc,
|
||||
.free = irq_domain_free_irqs_common,
|
||||
};
|
||||
|
||||
static int __init mtk_sysirq_of_init(struct device_node *node,
|
||||
struct device_node *parent)
|
||||
{
|
||||
struct irq_domain *domain, *domain_parent;
|
||||
struct mtk_sysirq_chip_data *chip_data;
|
||||
int ret = 0;
|
||||
|
||||
domain_parent = irq_find_host(parent);
|
||||
if (!domain_parent) {
|
||||
pr_err("mtk_sysirq: interrupt-parent not found\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
chip_data = kzalloc(sizeof(*chip_data), GFP_KERNEL);
|
||||
if (!chip_data)
|
||||
return -ENOMEM;
|
||||
|
||||
chip_data->intpol_base = of_io_request_and_map(node, 0, "intpol");
|
||||
if (!chip_data->intpol_base) {
|
||||
pr_err("mtk_sysirq: unable to map sysirq register\n");
|
||||
ret = -ENOMEM;
|
||||
goto out_free;
|
||||
}
|
||||
|
||||
domain = irq_domain_add_hierarchy(domain_parent, 0,
|
||||
MT6577_SYS_INTPOL_NUM, node,
|
||||
&sysirq_domain_ops, chip_data);
|
||||
if (!domain) {
|
||||
ret = -ENOMEM;
|
||||
goto out_unmap;
|
||||
}
|
||||
spin_lock_init(&chip_data->lock);
|
||||
|
||||
return 0;
|
||||
|
||||
out_unmap:
|
||||
iounmap(chip_data->intpol_base);
|
||||
out_free:
|
||||
kfree(chip_data);
|
||||
return ret;
|
||||
}
|
||||
IRQCHIP_DECLARE(mtk_sysirq, "mediatek,mt6577-sysirq", mtk_sysirq_of_init);
|
||||
|
|
@ -49,6 +49,10 @@
|
|||
#define GICD_CTLR_ENABLE_G1A (1U << 1)
|
||||
#define GICD_CTLR_ENABLE_G1 (1U << 0)
|
||||
|
||||
#define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1)
|
||||
#define GICD_TYPER_IRQS(typer) ((((typer) & 0x1f) + 1) * 32)
|
||||
#define GICD_TYPER_LPIS (1U << 17)
|
||||
|
||||
#define GICD_IROUTER_SPI_MODE_ONE (0U << 31)
|
||||
#define GICD_IROUTER_SPI_MODE_ANY (1U << 31)
|
||||
|
||||
|
|
@ -76,9 +80,27 @@
|
|||
#define GICR_MOVALLR 0x0110
|
||||
#define GICR_PIDR2 GICD_PIDR2
|
||||
|
||||
#define GICR_CTLR_ENABLE_LPIS (1UL << 0)
|
||||
|
||||
#define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff)
|
||||
|
||||
#define GICR_WAKER_ProcessorSleep (1U << 1)
|
||||
#define GICR_WAKER_ChildrenAsleep (1U << 2)
|
||||
|
||||
#define GICR_PROPBASER_NonShareable (0U << 10)
|
||||
#define GICR_PROPBASER_InnerShareable (1U << 10)
|
||||
#define GICR_PROPBASER_OuterShareable (2U << 10)
|
||||
#define GICR_PROPBASER_SHAREABILITY_MASK (3UL << 10)
|
||||
#define GICR_PROPBASER_nCnB (0U << 7)
|
||||
#define GICR_PROPBASER_nC (1U << 7)
|
||||
#define GICR_PROPBASER_RaWt (2U << 7)
|
||||
#define GICR_PROPBASER_RaWb (3U << 7)
|
||||
#define GICR_PROPBASER_WaWt (4U << 7)
|
||||
#define GICR_PROPBASER_WaWb (5U << 7)
|
||||
#define GICR_PROPBASER_RaWaWt (6U << 7)
|
||||
#define GICR_PROPBASER_RaWaWb (7U << 7)
|
||||
#define GICR_PROPBASER_IDBITS_MASK (0x1f)
|
||||
|
||||
/*
|
||||
* Re-Distributor registers, offsets from SGI_base
|
||||
*/
|
||||
|
|
@ -91,9 +113,93 @@
|
|||
#define GICR_IPRIORITYR0 GICD_IPRIORITYR
|
||||
#define GICR_ICFGR0 GICD_ICFGR
|
||||
|
||||
#define GICR_TYPER_PLPIS (1U << 0)
|
||||
#define GICR_TYPER_VLPIS (1U << 1)
|
||||
#define GICR_TYPER_LAST (1U << 4)
|
||||
|
||||
#define LPI_PROP_GROUP1 (1 << 1)
|
||||
#define LPI_PROP_ENABLED (1 << 0)
|
||||
|
||||
/*
|
||||
* ITS registers, offsets from ITS_base
|
||||
*/
|
||||
#define GITS_CTLR 0x0000
|
||||
#define GITS_IIDR 0x0004
|
||||
#define GITS_TYPER 0x0008
|
||||
#define GITS_CBASER 0x0080
|
||||
#define GITS_CWRITER 0x0088
|
||||
#define GITS_CREADR 0x0090
|
||||
#define GITS_BASER 0x0100
|
||||
#define GITS_PIDR2 GICR_PIDR2
|
||||
|
||||
#define GITS_TRANSLATER 0x10040
|
||||
|
||||
#define GITS_TYPER_PTA (1UL << 19)
|
||||
|
||||
#define GITS_CBASER_VALID (1UL << 63)
|
||||
#define GITS_CBASER_nCnB (0UL << 59)
|
||||
#define GITS_CBASER_nC (1UL << 59)
|
||||
#define GITS_CBASER_RaWt (2UL << 59)
|
||||
#define GITS_CBASER_RaWb (3UL << 59)
|
||||
#define GITS_CBASER_WaWt (4UL << 59)
|
||||
#define GITS_CBASER_WaWb (5UL << 59)
|
||||
#define GITS_CBASER_RaWaWt (6UL << 59)
|
||||
#define GITS_CBASER_RaWaWb (7UL << 59)
|
||||
#define GITS_CBASER_NonShareable (0UL << 10)
|
||||
#define GITS_CBASER_InnerShareable (1UL << 10)
|
||||
#define GITS_CBASER_OuterShareable (2UL << 10)
|
||||
#define GITS_CBASER_SHAREABILITY_MASK (3UL << 10)
|
||||
|
||||
#define GITS_BASER_NR_REGS 8
|
||||
|
||||
#define GITS_BASER_VALID (1UL << 63)
|
||||
#define GITS_BASER_nCnB (0UL << 59)
|
||||
#define GITS_BASER_nC (1UL << 59)
|
||||
#define GITS_BASER_RaWt (2UL << 59)
|
||||
#define GITS_BASER_RaWb (3UL << 59)
|
||||
#define GITS_BASER_WaWt (4UL << 59)
|
||||
#define GITS_BASER_WaWb (5UL << 59)
|
||||
#define GITS_BASER_RaWaWt (6UL << 59)
|
||||
#define GITS_BASER_RaWaWb (7UL << 59)
|
||||
#define GITS_BASER_TYPE_SHIFT (56)
|
||||
#define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7)
|
||||
#define GITS_BASER_ENTRY_SIZE_SHIFT (48)
|
||||
#define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0xff) + 1)
|
||||
#define GITS_BASER_NonShareable (0UL << 10)
|
||||
#define GITS_BASER_InnerShareable (1UL << 10)
|
||||
#define GITS_BASER_OuterShareable (2UL << 10)
|
||||
#define GITS_BASER_SHAREABILITY_SHIFT (10)
|
||||
#define GITS_BASER_SHAREABILITY_MASK (3UL << GITS_BASER_SHAREABILITY_SHIFT)
|
||||
#define GITS_BASER_PAGE_SIZE_SHIFT (8)
|
||||
#define GITS_BASER_PAGE_SIZE_4K (0UL << GITS_BASER_PAGE_SIZE_SHIFT)
|
||||
#define GITS_BASER_PAGE_SIZE_16K (1UL << GITS_BASER_PAGE_SIZE_SHIFT)
|
||||
#define GITS_BASER_PAGE_SIZE_64K (2UL << GITS_BASER_PAGE_SIZE_SHIFT)
|
||||
#define GITS_BASER_PAGE_SIZE_MASK (3UL << GITS_BASER_PAGE_SIZE_SHIFT)
|
||||
|
||||
#define GITS_BASER_TYPE_NONE 0
|
||||
#define GITS_BASER_TYPE_DEVICE 1
|
||||
#define GITS_BASER_TYPE_VCPU 2
|
||||
#define GITS_BASER_TYPE_CPU 3
|
||||
#define GITS_BASER_TYPE_COLLECTION 4
|
||||
#define GITS_BASER_TYPE_RESERVED5 5
|
||||
#define GITS_BASER_TYPE_RESERVED6 6
|
||||
#define GITS_BASER_TYPE_RESERVED7 7
|
||||
|
||||
/*
|
||||
* ITS commands
|
||||
*/
|
||||
#define GITS_CMD_MAPD 0x08
|
||||
#define GITS_CMD_MAPC 0x09
|
||||
#define GITS_CMD_MAPVI 0x0a
|
||||
#define GITS_CMD_MOVI 0x01
|
||||
#define GITS_CMD_DISCARD 0x0f
|
||||
#define GITS_CMD_INV 0x0c
|
||||
#define GITS_CMD_MOVALL 0x0e
|
||||
#define GITS_CMD_INVALL 0x0d
|
||||
#define GITS_CMD_INT 0x03
|
||||
#define GITS_CMD_CLEAR 0x04
|
||||
#define GITS_CMD_SYNC 0x05
|
||||
|
||||
/*
|
||||
* CPU interface registers
|
||||
*/
|
||||
|
|
@ -189,12 +295,34 @@
|
|||
|
||||
#include <linux/stringify.h>
|
||||
|
||||
/*
|
||||
* We need a value to serve as a irq-type for LPIs. Choose one that will
|
||||
* hopefully pique the interest of the reviewer.
|
||||
*/
|
||||
#define GIC_IRQ_TYPE_LPI 0xa110c8ed
|
||||
|
||||
struct rdists {
|
||||
struct {
|
||||
void __iomem *rd_base;
|
||||
struct page *pend_page;
|
||||
phys_addr_t phys_base;
|
||||
} __percpu *rdist;
|
||||
struct page *prop_page;
|
||||
int id_bits;
|
||||
u64 flags;
|
||||
};
|
||||
|
||||
static inline void gic_write_eoir(u64 irq)
|
||||
{
|
||||
asm volatile("msr_s " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" (irq));
|
||||
isb();
|
||||
}
|
||||
|
||||
struct irq_domain;
|
||||
int its_cpu_init(void);
|
||||
int its_init(struct device_node *node, struct rdists *rdists,
|
||||
struct irq_domain *domain);
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -91,6 +91,8 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <linux/irqdomain.h>
|
||||
|
||||
struct device_node;
|
||||
|
||||
extern struct irq_chip gic_arch_extn;
|
||||
|
|
@ -106,6 +108,8 @@ static inline void gic_init(unsigned int nr, int start,
|
|||
gic_init_bases(nr, start, dist, cpu, 0, NULL);
|
||||
}
|
||||
|
||||
int gicv2m_of_init(struct device_node *node, struct irq_domain *parent);
|
||||
|
||||
void gic_send_sgi(unsigned int cpu_id, unsigned int irq);
|
||||
int gic_get_cpu_id(unsigned int cpu);
|
||||
void gic_migrate_target(unsigned int new_cpu_id);
|
||||
|
|
|
|||
Loading…
Reference in a new issue