ARC updates for 5.3-rc7
- Support for Edge Triggered IRQs in ARC IDU intc - other fixes here and there -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJdZWFxAAoJEGnX8d3iisJe1/QP/1QlB6bDp36ONuc0wgtvyZhS /KDfgwyLK89WiH/lc2AgPL6BkFaOBSqpNe9PS8IdjRscGMJFaXnfifKBl2eX/sM3 4nkiIjAb9Fl4dLdaPs/51p+wvHlkdD9pzI5SYJl2IeNCZRNjjixBlaF8fezONtlu 2yuzmikeggcT7NZGnZ5IQGj6CWRm7Drb5J4mfmZu3HJ+BJOnXZpdza3q3WduT3DC 6tUA/xtUXq8sGpylXL2MgA34SbgjBDmxW8Kv32sQp6mipGJwq4jF4+n8rxF/znCe 6ILiqOwp7CjEHmpYTn2cxMC5FTP0BuvnLh/ECEFKUWgIH4/A3zy/RJOKhbZ0P0rV +vraRvdjOA2/0P6Y1A+cGGYP2c3HwmSgHmtXwd/QRfesX2/Y7jhMlEOXZ9H2K6CC zTqobUWQ4tFprz1P0H6p1h7Z/tJv/q4TNMZR5tcQyjwT6i7Sw+ReffTnwpPMr92V GAZu6sahsJCOqRqk0MfaZVa54r+UlE8bbapGZo+7fZ9+UVrxLKgWwfnYbe/6eSHX osddo3zoLuBrgq2gt/ZMseeQRdRYeH8p/3jgnEws2G/uen7GjAw9m0c3Yrs+ibVS oNp3DNk8wkzgrLgC7xXhBkwyok85SEoCfZoQg96DXo365G0YyHZyHCI2HzIAP4oy wtRcqnsQgEtvV1s7RiTU =CJKr -----END PGP SIGNATURE----- Merge tag 'arc-5.3-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc Pull ARC updates from Vineet Gupta: - support for Edge Triggered IRQs in ARC IDU intc - other fixes here and there * tag 'arc-5.3-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: arc: prefer __section from compiler_attributes.h dt-bindings: IDU-intc: Add support for edge-triggered interrupts dt-bindings: IDU-intc: Clean up documentation ARCv2: IDU-intc: Add support for edge-triggered interrupts ARC: unwind: Mark expected switch fall-throughs ARC: [plat-hsdk]: allow to switch between AXI DMAC port configurations ARC: fix typo in setup_dma_ops log message ARCv2: entry: early return from exception need not clear U & DE bits
This commit is contained in:
commit
6525771f58
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@ -1,20 +1,30 @@
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* ARC-HS Interrupt Distribution Unit
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This optional 2nd level interrupt controller can be used in SMP configurations for
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dynamic IRQ routing, load balancing of common/external IRQs towards core intc.
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This optional 2nd level interrupt controller can be used in SMP configurations
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for dynamic IRQ routing, load balancing of common/external IRQs towards core
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intc.
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Properties:
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- compatible: "snps,archs-idu-intc"
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- interrupt-controller: This is an interrupt controller.
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- #interrupt-cells: Must be <1>.
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- #interrupt-cells: Must be <1> or <2>.
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Value of the cell specifies the "common" IRQ from peripheral to IDU. Number N
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of the particular interrupt line of IDU corresponds to the line N+24 of the
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core interrupt controller.
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Value of the first cell specifies the "common" IRQ from peripheral to IDU.
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Number N of the particular interrupt line of IDU corresponds to the line N+24
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of the core interrupt controller.
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intc accessed via the special ARC AUX register interface, hence "reg" property
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is not specified.
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The (optional) second cell specifies any of the following flags:
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- bits[3:0] trigger type and level flags
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1 = low-to-high edge triggered
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2 = NOT SUPPORTED (high-to-low edge triggered)
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4 = active high level-sensitive <<< DEFAULT
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8 = NOT SUPPORTED (active low level-sensitive)
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When no second cell is specified, the interrupt is assumed to be level
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sensitive.
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The interrupt controller is accessed via the special ARC AUX register
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interface, hence "reg" property is not specified.
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Example:
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core_intc: core-interrupt-controller {
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@ -12,3 +12,6 @@ dtb-y := $(builtindtb-y).dtb
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# for CONFIG_OF_ALL_DTBS test
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dtstree := $(srctree)/$(src)
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dtb- := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts))
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# board-specific dtc flags
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DTC_FLAGS_hsdk += --pad 20
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@ -256,7 +256,7 @@
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.macro FAKE_RET_FROM_EXCPN
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lr r9, [status32]
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bic r9, r9, (STATUS_U_MASK|STATUS_DE_MASK|STATUS_AE_MASK)
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bic r9, r9, STATUS_AE_MASK
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or r9, r9, STATUS_IE_MASK
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kflag r9
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.endm
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@ -62,15 +62,15 @@
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#else /* !__ASSEMBLY__ */
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#ifdef CONFIG_ARC_HAS_ICCM
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#define __arcfp_code __attribute__((__section__(".text.arcfp")))
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#define __arcfp_code __section(.text.arcfp)
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#else
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#define __arcfp_code __attribute__((__section__(".text")))
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#define __arcfp_code __section(.text)
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#endif
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#ifdef CONFIG_ARC_HAS_DCCM
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#define __arcfp_data __attribute__((__section__(".data.arcfp")))
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#define __arcfp_data __section(.data.arcfp)
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#else
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#define __arcfp_data __attribute__((__section__(".data")))
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#define __arcfp_data __section(.data)
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#endif
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#endif /* __ASSEMBLY__ */
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@ -53,8 +53,7 @@ extern const struct machine_desc __arch_info_begin[], __arch_info_end[];
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*/
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#define MACHINE_START(_type, _name) \
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static const struct machine_desc __mach_desc_##_type \
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__used \
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__attribute__((__section__(".arch.info.init"))) = { \
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__used __section(.arch.info.init) = { \
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.name = _name,
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#define MACHINE_END \
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@ -202,8 +202,8 @@ static void idu_set_dest(unsigned int cmn_irq, unsigned int cpu_mask)
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__mcip_cmd_data(CMD_IDU_SET_DEST, cmn_irq, cpu_mask);
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}
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static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl,
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unsigned int distr)
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static void idu_set_mode(unsigned int cmn_irq, bool set_lvl, unsigned int lvl,
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bool set_distr, unsigned int distr)
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{
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union {
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unsigned int word;
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@ -212,8 +212,11 @@ static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl,
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};
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} data;
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data.distr = distr;
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data.lvl = lvl;
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data.word = __mcip_cmd_read(CMD_IDU_READ_MODE, cmn_irq);
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if (set_distr)
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data.distr = distr;
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if (set_lvl)
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data.lvl = lvl;
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__mcip_cmd_data(CMD_IDU_SET_MODE, cmn_irq, data.word);
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}
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@ -240,6 +243,25 @@ static void idu_irq_unmask(struct irq_data *data)
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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}
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static void idu_irq_ack(struct irq_data *data)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&mcip_lock, flags);
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__mcip_cmd(CMD_IDU_ACK_CIRQ, data->hwirq);
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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}
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static void idu_irq_mask_ack(struct irq_data *data)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&mcip_lock, flags);
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__mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 1);
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__mcip_cmd(CMD_IDU_ACK_CIRQ, data->hwirq);
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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}
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static int
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idu_irq_set_affinity(struct irq_data *data, const struct cpumask *cpumask,
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bool force)
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@ -263,13 +285,36 @@ idu_irq_set_affinity(struct irq_data *data, const struct cpumask *cpumask,
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else
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distribution_mode = IDU_M_DISTRI_RR;
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idu_set_mode(data->hwirq, IDU_M_TRIG_LEVEL, distribution_mode);
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idu_set_mode(data->hwirq, false, 0, true, distribution_mode);
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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return IRQ_SET_MASK_OK;
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}
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static int idu_irq_set_type(struct irq_data *data, u32 type)
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{
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unsigned long flags;
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/*
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* ARCv2 IDU HW does not support inverse polarity, so these are the
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* only interrupt types supported.
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*/
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if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH))
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return -EINVAL;
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raw_spin_lock_irqsave(&mcip_lock, flags);
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idu_set_mode(data->hwirq, true,
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type & IRQ_TYPE_EDGE_RISING ? IDU_M_TRIG_EDGE :
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IDU_M_TRIG_LEVEL,
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false, 0);
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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return 0;
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}
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static void idu_irq_enable(struct irq_data *data)
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{
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/*
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@ -289,7 +334,10 @@ static struct irq_chip idu_irq_chip = {
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.name = "MCIP IDU Intc",
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.irq_mask = idu_irq_mask,
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.irq_unmask = idu_irq_unmask,
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.irq_ack = idu_irq_ack,
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.irq_mask_ack = idu_irq_mask_ack,
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.irq_enable = idu_irq_enable,
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.irq_set_type = idu_irq_set_type,
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#ifdef CONFIG_SMP
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.irq_set_affinity = idu_irq_set_affinity,
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#endif
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@ -317,7 +365,7 @@ static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t
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}
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static const struct irq_domain_ops idu_irq_ops = {
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.xlate = irq_domain_xlate_onecell,
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.xlate = irq_domain_xlate_onetwocell,
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.map = idu_irq_map,
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};
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@ -826,7 +826,7 @@ static int processCFI(const u8 *start, const u8 *end, unsigned long targetLoc,
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case DW_CFA_def_cfa:
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state->cfa.reg = get_uleb128(&ptr.p8, end);
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unw_debug("cfa_def_cfa: r%lu ", state->cfa.reg);
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/*nobreak*/
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/* fall through */
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case DW_CFA_def_cfa_offset:
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state->cfa.offs = get_uleb128(&ptr.p8, end);
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unw_debug("cfa_def_cfa_offset: 0x%lx ",
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@ -834,7 +834,7 @@ static int processCFI(const u8 *start, const u8 *end, unsigned long targetLoc,
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break;
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case DW_CFA_def_cfa_sf:
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state->cfa.reg = get_uleb128(&ptr.p8, end);
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/*nobreak */
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/* fall through */
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case DW_CFA_def_cfa_offset_sf:
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state->cfa.offs = get_sleb128(&ptr.p8, end)
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* state->dataAlign;
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|
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@ -101,7 +101,7 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
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if (is_isa_arcv2() && ioc_enable && coherent)
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dev->dma_coherent = true;
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dev_info(dev, "use %sncoherent DMA ops\n",
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dev_info(dev, "use %scoherent DMA ops\n",
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dev->dma_coherent ? "" : "non");
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}
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@ -6,11 +6,15 @@
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*/
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#include <linux/init.h>
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#include <linux/of_fdt.h>
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#include <linux/libfdt.h>
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#include <linux/smp.h>
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#include <asm/arcregs.h>
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#include <asm/io.h>
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#include <asm/mach_desc.h>
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int arc_hsdk_axi_dmac_coherent __section(.data) = 0;
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#define ARC_CCM_UNUSED_ADDR 0x60000000
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static void __init hsdk_init_per_cpu(unsigned int cpu)
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@ -97,6 +101,42 @@ static void __init hsdk_enable_gpio_intc_wire(void)
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iowrite32(GPIO_INT_CONNECTED_MASK, (void __iomem *) GPIO_INTEN);
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}
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static int __init hsdk_tweak_node_coherency(const char *path, bool coherent)
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{
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void *fdt = initial_boot_params;
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const void *prop;
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int node, ret;
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bool dt_coh_set;
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node = fdt_path_offset(fdt, path);
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if (node < 0)
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goto tweak_fail;
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prop = fdt_getprop(fdt, node, "dma-coherent", &ret);
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if (!prop && ret != -FDT_ERR_NOTFOUND)
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goto tweak_fail;
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dt_coh_set = ret != -FDT_ERR_NOTFOUND;
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ret = 0;
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/* need to remove "dma-coherent" property */
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if (dt_coh_set && !coherent)
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ret = fdt_delprop(fdt, node, "dma-coherent");
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/* need to set "dma-coherent" property */
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if (!dt_coh_set && coherent)
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ret = fdt_setprop(fdt, node, "dma-coherent", NULL, 0);
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if (ret < 0)
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goto tweak_fail;
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|
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return 0;
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|
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tweak_fail:
|
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pr_err("failed to tweak %s to %scoherent\n", path, coherent ? "" : "non");
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return -EFAULT;
|
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}
|
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enum hsdk_axi_masters {
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M_HS_CORE = 0,
|
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M_HS_RTT,
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|
@ -162,6 +202,39 @@ enum hsdk_axi_masters {
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|||
#define CREG_PAE ((void __iomem *)(CREG_BASE + 0x180))
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#define CREG_PAE_UPDT ((void __iomem *)(CREG_BASE + 0x194))
|
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|
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static void __init hsdk_init_memory_bridge_axi_dmac(void)
|
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{
|
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bool coherent = !!arc_hsdk_axi_dmac_coherent;
|
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u32 axi_m_slv1, axi_m_oft1;
|
||||
|
||||
/*
|
||||
* Don't tweak memory bridge configuration if we failed to tweak DTB
|
||||
* as we will end up in a inconsistent state.
|
||||
*/
|
||||
if (hsdk_tweak_node_coherency("/soc/dmac@80000", coherent))
|
||||
return;
|
||||
|
||||
if (coherent) {
|
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axi_m_slv1 = 0x77999999;
|
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axi_m_oft1 = 0x76DCBA98;
|
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} else {
|
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axi_m_slv1 = 0x77777777;
|
||||
axi_m_oft1 = 0x76543210;
|
||||
}
|
||||
|
||||
writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0));
|
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writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0));
|
||||
writel(axi_m_slv1, CREG_AXI_M_SLV1(M_DMAC_0));
|
||||
writel(axi_m_oft1, CREG_AXI_M_OFT1(M_DMAC_0));
|
||||
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0));
|
||||
|
||||
writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1));
|
||||
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1));
|
||||
writel(axi_m_slv1, CREG_AXI_M_SLV1(M_DMAC_1));
|
||||
writel(axi_m_oft1, CREG_AXI_M_OFT1(M_DMAC_1));
|
||||
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1));
|
||||
}
|
||||
|
||||
static void __init hsdk_init_memory_bridge(void)
|
||||
{
|
||||
u32 reg;
|
||||
|
@ -227,24 +300,14 @@ static void __init hsdk_init_memory_bridge(void)
|
|||
writel(0x76543210, CREG_AXI_M_OFT1(M_GPU));
|
||||
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_GPU));
|
||||
|
||||
writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0));
|
||||
writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_0));
|
||||
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0));
|
||||
writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_0));
|
||||
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0));
|
||||
|
||||
writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1));
|
||||
writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_1));
|
||||
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1));
|
||||
writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_1));
|
||||
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1));
|
||||
|
||||
writel(0x00000000, CREG_AXI_M_SLV0(M_DVFS));
|
||||
writel(0x60000000, CREG_AXI_M_SLV1(M_DVFS));
|
||||
writel(0x00000000, CREG_AXI_M_OFT0(M_DVFS));
|
||||
writel(0x00000000, CREG_AXI_M_OFT1(M_DVFS));
|
||||
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DVFS));
|
||||
|
||||
hsdk_init_memory_bridge_axi_dmac();
|
||||
|
||||
/*
|
||||
* PAE remapping for DMA clients does not work due to an RTL bug, so
|
||||
* CREG_PAE register must be programmed to all zeroes, otherwise it
|
||||
|
|
|
@ -46,7 +46,9 @@ struct mcip_cmd {
|
|||
#define CMD_IDU_ENABLE 0x71
|
||||
#define CMD_IDU_DISABLE 0x72
|
||||
#define CMD_IDU_SET_MODE 0x74
|
||||
#define CMD_IDU_READ_MODE 0x75
|
||||
#define CMD_IDU_SET_DEST 0x76
|
||||
#define CMD_IDU_ACK_CIRQ 0x79
|
||||
#define CMD_IDU_SET_MASK 0x7C
|
||||
|
||||
#define IDU_M_TRIG_LEVEL 0x0
|
||||
|
@ -119,4 +121,13 @@ static inline void __mcip_cmd_data(unsigned int cmd, unsigned int param,
|
|||
__mcip_cmd(cmd, param);
|
||||
}
|
||||
|
||||
/*
|
||||
* Read MCIP register
|
||||
*/
|
||||
static inline unsigned int __mcip_cmd_read(unsigned int cmd, unsigned int param)
|
||||
{
|
||||
__mcip_cmd(cmd, param);
|
||||
return read_aux_reg(ARC_REG_MCIP_READBACK);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
Loading…
Reference in a new issue